1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
9 #include <linux/bitmap.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/export.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
17 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
20 #include <linux/of_device.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/sizes.h>
24 #include <linux/slab.h>
25 #include <linux/sys_soc.h>
27 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
28 #include <asm/dma-iommu.h>
30 #define arm_iommu_create_mapping(...) NULL
31 #define arm_iommu_attach_device(...) -ENODEV
32 #define arm_iommu_release_mapping(...) do {} while (0)
33 #define arm_iommu_detach_device(...) do {} while (0)
36 #define IPMMU_CTX_MAX 8U
37 #define IPMMU_CTX_INVALID -1
39 #define IPMMU_UTLB_MAX 48U
41 struct ipmmu_features
{
42 bool use_ns_alias_offset
;
43 bool has_cache_leaf_nodes
;
44 unsigned int number_of_contexts
;
45 unsigned int num_utlbs
;
47 bool twobit_imttbcr_sl0
;
48 bool reserved_context
;
50 unsigned int ctx_offset_base
;
51 unsigned int ctx_offset_stride
;
52 unsigned int utlb_offset_base
;
55 struct ipmmu_vmsa_device
{
58 struct iommu_device iommu
;
59 struct ipmmu_vmsa_device
*root
;
60 const struct ipmmu_features
*features
;
62 spinlock_t lock
; /* Protects ctx and domains[] */
63 DECLARE_BITMAP(ctx
, IPMMU_CTX_MAX
);
64 struct ipmmu_vmsa_domain
*domains
[IPMMU_CTX_MAX
];
65 s8 utlb_ctx
[IPMMU_UTLB_MAX
];
67 struct iommu_group
*group
;
68 struct dma_iommu_mapping
*mapping
;
71 struct ipmmu_vmsa_domain
{
72 struct ipmmu_vmsa_device
*mmu
;
73 struct iommu_domain io_domain
;
75 struct io_pgtable_cfg cfg
;
76 struct io_pgtable_ops
*iop
;
78 unsigned int context_id
;
79 struct mutex mutex
; /* Protects mappings */
82 static struct ipmmu_vmsa_domain
*to_vmsa_domain(struct iommu_domain
*dom
)
84 return container_of(dom
, struct ipmmu_vmsa_domain
, io_domain
);
87 static struct ipmmu_vmsa_device
*to_ipmmu(struct device
*dev
)
89 return dev_iommu_priv_get(dev
);
92 #define TLB_LOOP_TIMEOUT 100 /* 100us */
94 /* -----------------------------------------------------------------------------
95 * Registers Definition
98 #define IM_NS_ALIAS_OFFSET 0x800
100 /* MMU "context" registers */
101 #define IMCTR 0x0000 /* R-Car Gen2/3 */
102 #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */
103 #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
104 #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
106 #define IMTTBCR 0x0008 /* R-Car Gen2/3 */
107 #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */
108 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */
109 #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */
110 #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */
111 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */
112 #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */
114 #define IMBUSCR 0x000c /* R-Car Gen2 only */
115 #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */
116 #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */
118 #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */
119 #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */
121 #define IMSTR 0x0020 /* R-Car Gen2/3 */
122 #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */
123 #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */
124 #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */
125 #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */
127 #define IMMAIR0 0x0028 /* R-Car Gen2/3 */
129 #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */
130 #define IMEUAR 0x0034 /* R-Car Gen3 only */
133 #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n))
134 #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */
135 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */
136 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */
137 #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
138 #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
140 #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n))
141 #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */
142 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */
144 /* -----------------------------------------------------------------------------
145 * Root device handling
148 static struct platform_driver ipmmu_driver
;
150 static bool ipmmu_is_root(struct ipmmu_vmsa_device
*mmu
)
152 return mmu
->root
== mmu
;
155 static int __ipmmu_check_device(struct device
*dev
, void *data
)
157 struct ipmmu_vmsa_device
*mmu
= dev_get_drvdata(dev
);
158 struct ipmmu_vmsa_device
**rootp
= data
;
160 if (ipmmu_is_root(mmu
))
166 static struct ipmmu_vmsa_device
*ipmmu_find_root(void)
168 struct ipmmu_vmsa_device
*root
= NULL
;
170 return driver_for_each_device(&ipmmu_driver
.driver
, NULL
, &root
,
171 __ipmmu_check_device
) == 0 ? root
: NULL
;
174 /* -----------------------------------------------------------------------------
178 static u32
ipmmu_read(struct ipmmu_vmsa_device
*mmu
, unsigned int offset
)
180 return ioread32(mmu
->base
+ offset
);
183 static void ipmmu_write(struct ipmmu_vmsa_device
*mmu
, unsigned int offset
,
186 iowrite32(data
, mmu
->base
+ offset
);
189 static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device
*mmu
,
190 unsigned int context_id
, unsigned int reg
)
192 return mmu
->features
->ctx_offset_base
+
193 context_id
* mmu
->features
->ctx_offset_stride
+ reg
;
196 static u32
ipmmu_ctx_read(struct ipmmu_vmsa_device
*mmu
,
197 unsigned int context_id
, unsigned int reg
)
199 return ipmmu_read(mmu
, ipmmu_ctx_reg(mmu
, context_id
, reg
));
202 static void ipmmu_ctx_write(struct ipmmu_vmsa_device
*mmu
,
203 unsigned int context_id
, unsigned int reg
, u32 data
)
205 ipmmu_write(mmu
, ipmmu_ctx_reg(mmu
, context_id
, reg
), data
);
208 static u32
ipmmu_ctx_read_root(struct ipmmu_vmsa_domain
*domain
,
211 return ipmmu_ctx_read(domain
->mmu
->root
, domain
->context_id
, reg
);
214 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain
*domain
,
215 unsigned int reg
, u32 data
)
217 ipmmu_ctx_write(domain
->mmu
->root
, domain
->context_id
, reg
, data
);
220 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain
*domain
,
221 unsigned int reg
, u32 data
)
223 if (domain
->mmu
!= domain
->mmu
->root
)
224 ipmmu_ctx_write(domain
->mmu
, domain
->context_id
, reg
, data
);
226 ipmmu_ctx_write(domain
->mmu
->root
, domain
->context_id
, reg
, data
);
229 static u32
ipmmu_utlb_reg(struct ipmmu_vmsa_device
*mmu
, unsigned int reg
)
231 return mmu
->features
->utlb_offset_base
+ reg
;
234 static void ipmmu_imuasid_write(struct ipmmu_vmsa_device
*mmu
,
235 unsigned int utlb
, u32 data
)
237 ipmmu_write(mmu
, ipmmu_utlb_reg(mmu
, IMUASID(utlb
)), data
);
240 static void ipmmu_imuctr_write(struct ipmmu_vmsa_device
*mmu
,
241 unsigned int utlb
, u32 data
)
243 ipmmu_write(mmu
, ipmmu_utlb_reg(mmu
, IMUCTR(utlb
)), data
);
246 /* -----------------------------------------------------------------------------
247 * TLB and microTLB Management
250 /* Wait for any pending TLB invalidations to complete */
251 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain
*domain
)
253 unsigned int count
= 0;
255 while (ipmmu_ctx_read_root(domain
, IMCTR
) & IMCTR_FLUSH
) {
257 if (++count
== TLB_LOOP_TIMEOUT
) {
258 dev_err_ratelimited(domain
->mmu
->dev
,
259 "TLB sync timed out -- MMU may be deadlocked\n");
266 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain
*domain
)
270 reg
= ipmmu_ctx_read_root(domain
, IMCTR
);
272 ipmmu_ctx_write_all(domain
, IMCTR
, reg
);
274 ipmmu_tlb_sync(domain
);
278 * Enable MMU translation for the microTLB.
280 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain
*domain
,
283 struct ipmmu_vmsa_device
*mmu
= domain
->mmu
;
286 * TODO: Reference-count the microTLB as several bus masters can be
287 * connected to the same microTLB.
290 /* TODO: What should we set the ASID to ? */
291 ipmmu_imuasid_write(mmu
, utlb
, 0);
292 /* TODO: Do we need to flush the microTLB ? */
293 ipmmu_imuctr_write(mmu
, utlb
, IMUCTR_TTSEL_MMU(domain
->context_id
) |
294 IMUCTR_FLUSH
| IMUCTR_MMUEN
);
295 mmu
->utlb_ctx
[utlb
] = domain
->context_id
;
299 * Disable MMU translation for the microTLB.
301 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain
*domain
,
304 struct ipmmu_vmsa_device
*mmu
= domain
->mmu
;
306 ipmmu_imuctr_write(mmu
, utlb
, 0);
307 mmu
->utlb_ctx
[utlb
] = IPMMU_CTX_INVALID
;
310 static void ipmmu_tlb_flush_all(void *cookie
)
312 struct ipmmu_vmsa_domain
*domain
= cookie
;
314 ipmmu_tlb_invalidate(domain
);
317 static void ipmmu_tlb_flush(unsigned long iova
, size_t size
,
318 size_t granule
, void *cookie
)
320 ipmmu_tlb_flush_all(cookie
);
323 static const struct iommu_flush_ops ipmmu_flush_ops
= {
324 .tlb_flush_all
= ipmmu_tlb_flush_all
,
325 .tlb_flush_walk
= ipmmu_tlb_flush
,
328 /* -----------------------------------------------------------------------------
329 * Domain/Context Management
332 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device
*mmu
,
333 struct ipmmu_vmsa_domain
*domain
)
338 spin_lock_irqsave(&mmu
->lock
, flags
);
340 ret
= find_first_zero_bit(mmu
->ctx
, mmu
->num_ctx
);
341 if (ret
!= mmu
->num_ctx
) {
342 mmu
->domains
[ret
] = domain
;
343 set_bit(ret
, mmu
->ctx
);
347 spin_unlock_irqrestore(&mmu
->lock
, flags
);
352 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device
*mmu
,
353 unsigned int context_id
)
357 spin_lock_irqsave(&mmu
->lock
, flags
);
359 clear_bit(context_id
, mmu
->ctx
);
360 mmu
->domains
[context_id
] = NULL
;
362 spin_unlock_irqrestore(&mmu
->lock
, flags
);
365 static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain
*domain
)
371 ttbr
= domain
->cfg
.arm_lpae_s1_cfg
.ttbr
;
372 ipmmu_ctx_write_root(domain
, IMTTLBR0
, ttbr
);
373 ipmmu_ctx_write_root(domain
, IMTTUBR0
, ttbr
>> 32);
377 * We use long descriptors and allocate the whole 32-bit VA space to
380 if (domain
->mmu
->features
->twobit_imttbcr_sl0
)
381 tmp
= IMTTBCR_SL0_TWOBIT_LVL_1
;
383 tmp
= IMTTBCR_SL0_LVL_1
;
385 if (domain
->mmu
->features
->cache_snoop
)
386 tmp
|= IMTTBCR_SH0_INNER_SHAREABLE
| IMTTBCR_ORGN0_WB_WA
|
389 ipmmu_ctx_write_root(domain
, IMTTBCR
, IMTTBCR_EAE
| tmp
);
392 ipmmu_ctx_write_root(domain
, IMMAIR0
,
393 domain
->cfg
.arm_lpae_s1_cfg
.mair
);
396 if (domain
->mmu
->features
->setup_imbuscr
)
397 ipmmu_ctx_write_root(domain
, IMBUSCR
,
398 ipmmu_ctx_read_root(domain
, IMBUSCR
) &
399 ~(IMBUSCR_DVM
| IMBUSCR_BUSSEL_MASK
));
403 * Clear all interrupt flags.
405 ipmmu_ctx_write_root(domain
, IMSTR
, ipmmu_ctx_read_root(domain
, IMSTR
));
409 * Enable the MMU and interrupt generation. The long-descriptor
410 * translation table format doesn't use TEX remapping. Don't enable AF
411 * software management as we have no use for it. Flush the TLB as
412 * required when modifying the context registers.
414 ipmmu_ctx_write_all(domain
, IMCTR
,
415 IMCTR_INTEN
| IMCTR_FLUSH
| IMCTR_MMUEN
);
418 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain
*domain
)
423 * Allocate the page table operations.
425 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
426 * access, Long-descriptor format" that the NStable bit being set in a
427 * table descriptor will result in the NStable and NS bits of all child
428 * entries being ignored and considered as being set. The IPMMU seems
429 * not to comply with this, as it generates a secure access page fault
430 * if any of the NStable and NS bits isn't set when running in
433 domain
->cfg
.quirks
= IO_PGTABLE_QUIRK_ARM_NS
;
434 domain
->cfg
.pgsize_bitmap
= SZ_1G
| SZ_2M
| SZ_4K
;
435 domain
->cfg
.ias
= 32;
436 domain
->cfg
.oas
= 40;
437 domain
->cfg
.tlb
= &ipmmu_flush_ops
;
438 domain
->io_domain
.geometry
.aperture_end
= DMA_BIT_MASK(32);
439 domain
->io_domain
.geometry
.force_aperture
= true;
441 * TODO: Add support for coherent walk through CCI with DVM and remove
442 * cache handling. For now, delegate it to the io-pgtable code.
444 domain
->cfg
.coherent_walk
= false;
445 domain
->cfg
.iommu_dev
= domain
->mmu
->root
->dev
;
448 * Find an unused context.
450 ret
= ipmmu_domain_allocate_context(domain
->mmu
->root
, domain
);
454 domain
->context_id
= ret
;
456 domain
->iop
= alloc_io_pgtable_ops(ARM_32_LPAE_S1
, &domain
->cfg
,
459 ipmmu_domain_free_context(domain
->mmu
->root
,
464 ipmmu_domain_setup_context(domain
);
468 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain
*domain
)
474 * Disable the context. Flush the TLB as required when modifying the
477 * TODO: Is TLB flush really needed ?
479 ipmmu_ctx_write_all(domain
, IMCTR
, IMCTR_FLUSH
);
480 ipmmu_tlb_sync(domain
);
481 ipmmu_domain_free_context(domain
->mmu
->root
, domain
->context_id
);
484 /* -----------------------------------------------------------------------------
488 static irqreturn_t
ipmmu_domain_irq(struct ipmmu_vmsa_domain
*domain
)
490 const u32 err_mask
= IMSTR_MHIT
| IMSTR_ABORT
| IMSTR_PF
| IMSTR_TF
;
491 struct ipmmu_vmsa_device
*mmu
= domain
->mmu
;
495 status
= ipmmu_ctx_read_root(domain
, IMSTR
);
496 if (!(status
& err_mask
))
499 iova
= ipmmu_ctx_read_root(domain
, IMELAR
);
500 if (IS_ENABLED(CONFIG_64BIT
))
501 iova
|= (u64
)ipmmu_ctx_read_root(domain
, IMEUAR
) << 32;
504 * Clear the error status flags. Unlike traditional interrupt flag
505 * registers that must be cleared by writing 1, this status register
506 * seems to require 0. The error address register must be read before,
507 * otherwise its value will be 0.
509 ipmmu_ctx_write_root(domain
, IMSTR
, 0);
511 /* Log fatal errors. */
512 if (status
& IMSTR_MHIT
)
513 dev_err_ratelimited(mmu
->dev
, "Multiple TLB hits @0x%lx\n",
515 if (status
& IMSTR_ABORT
)
516 dev_err_ratelimited(mmu
->dev
, "Page Table Walk Abort @0x%lx\n",
519 if (!(status
& (IMSTR_PF
| IMSTR_TF
)))
523 * Try to handle page faults and translation faults.
525 * TODO: We need to look up the faulty device based on the I/O VA. Use
526 * the IOMMU device for now.
528 if (!report_iommu_fault(&domain
->io_domain
, mmu
->dev
, iova
, 0))
531 dev_err_ratelimited(mmu
->dev
,
532 "Unhandled fault: status 0x%08x iova 0x%lx\n",
538 static irqreturn_t
ipmmu_irq(int irq
, void *dev
)
540 struct ipmmu_vmsa_device
*mmu
= dev
;
541 irqreturn_t status
= IRQ_NONE
;
545 spin_lock_irqsave(&mmu
->lock
, flags
);
548 * Check interrupts for all active contexts.
550 for (i
= 0; i
< mmu
->num_ctx
; i
++) {
551 if (!mmu
->domains
[i
])
553 if (ipmmu_domain_irq(mmu
->domains
[i
]) == IRQ_HANDLED
)
554 status
= IRQ_HANDLED
;
557 spin_unlock_irqrestore(&mmu
->lock
, flags
);
562 /* -----------------------------------------------------------------------------
566 static struct iommu_domain
*ipmmu_domain_alloc(unsigned type
)
568 struct ipmmu_vmsa_domain
*domain
;
570 if (type
!= IOMMU_DOMAIN_UNMANAGED
&& type
!= IOMMU_DOMAIN_DMA
)
573 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
577 mutex_init(&domain
->mutex
);
579 return &domain
->io_domain
;
582 static void ipmmu_domain_free(struct iommu_domain
*io_domain
)
584 struct ipmmu_vmsa_domain
*domain
= to_vmsa_domain(io_domain
);
587 * Free the domain resources. We assume that all devices have already
590 ipmmu_domain_destroy_context(domain
);
591 free_io_pgtable_ops(domain
->iop
);
595 static int ipmmu_attach_device(struct iommu_domain
*io_domain
,
598 struct iommu_fwspec
*fwspec
= dev_iommu_fwspec_get(dev
);
599 struct ipmmu_vmsa_device
*mmu
= to_ipmmu(dev
);
600 struct ipmmu_vmsa_domain
*domain
= to_vmsa_domain(io_domain
);
605 dev_err(dev
, "Cannot attach to IPMMU\n");
609 mutex_lock(&domain
->mutex
);
612 /* The domain hasn't been used yet, initialize it. */
614 ret
= ipmmu_domain_init_context(domain
);
616 dev_err(dev
, "Unable to initialize IPMMU context\n");
619 dev_info(dev
, "Using IPMMU context %u\n",
622 } else if (domain
->mmu
!= mmu
) {
624 * Something is wrong, we can't attach two devices using
625 * different IOMMUs to the same domain.
627 dev_err(dev
, "Can't attach IPMMU %s to domain on IPMMU %s\n",
628 dev_name(mmu
->dev
), dev_name(domain
->mmu
->dev
));
631 dev_info(dev
, "Reusing IPMMU context %u\n", domain
->context_id
);
633 mutex_unlock(&domain
->mutex
);
638 for (i
= 0; i
< fwspec
->num_ids
; ++i
)
639 ipmmu_utlb_enable(domain
, fwspec
->ids
[i
]);
644 static void ipmmu_detach_device(struct iommu_domain
*io_domain
,
647 struct iommu_fwspec
*fwspec
= dev_iommu_fwspec_get(dev
);
648 struct ipmmu_vmsa_domain
*domain
= to_vmsa_domain(io_domain
);
651 for (i
= 0; i
< fwspec
->num_ids
; ++i
)
652 ipmmu_utlb_disable(domain
, fwspec
->ids
[i
]);
655 * TODO: Optimize by disabling the context when no device is attached.
659 static int ipmmu_map(struct iommu_domain
*io_domain
, unsigned long iova
,
660 phys_addr_t paddr
, size_t size
, int prot
, gfp_t gfp
)
662 struct ipmmu_vmsa_domain
*domain
= to_vmsa_domain(io_domain
);
667 return domain
->iop
->map(domain
->iop
, iova
, paddr
, size
, prot
, gfp
);
670 static size_t ipmmu_unmap(struct iommu_domain
*io_domain
, unsigned long iova
,
671 size_t size
, struct iommu_iotlb_gather
*gather
)
673 struct ipmmu_vmsa_domain
*domain
= to_vmsa_domain(io_domain
);
675 return domain
->iop
->unmap(domain
->iop
, iova
, size
, gather
);
678 static void ipmmu_flush_iotlb_all(struct iommu_domain
*io_domain
)
680 struct ipmmu_vmsa_domain
*domain
= to_vmsa_domain(io_domain
);
683 ipmmu_tlb_flush_all(domain
);
686 static void ipmmu_iotlb_sync(struct iommu_domain
*io_domain
,
687 struct iommu_iotlb_gather
*gather
)
689 ipmmu_flush_iotlb_all(io_domain
);
692 static phys_addr_t
ipmmu_iova_to_phys(struct iommu_domain
*io_domain
,
695 struct ipmmu_vmsa_domain
*domain
= to_vmsa_domain(io_domain
);
697 /* TODO: Is locking needed ? */
699 return domain
->iop
->iova_to_phys(domain
->iop
, iova
);
702 static int ipmmu_init_platform_device(struct device
*dev
,
703 struct of_phandle_args
*args
)
705 struct platform_device
*ipmmu_pdev
;
707 ipmmu_pdev
= of_find_device_by_node(args
->np
);
711 dev_iommu_priv_set(dev
, platform_get_drvdata(ipmmu_pdev
));
716 static const struct soc_device_attribute soc_needs_opt_in
[] = {
717 { .family
= "R-Car Gen3", },
718 { .family
= "RZ/G2", },
722 static const struct soc_device_attribute soc_denylist
[] = {
723 { .soc_id
= "r8a774a1", },
724 { .soc_id
= "r8a7795", .revision
= "ES1.*" },
725 { .soc_id
= "r8a7795", .revision
= "ES2.*" },
726 { .soc_id
= "r8a7796", },
730 static const char * const devices_allowlist
[] = {
737 static bool ipmmu_device_is_allowed(struct device
*dev
)
742 * R-Car Gen3 and RZ/G2 use the allow list to opt-in devices.
743 * For Other SoCs, this returns true anyway.
745 if (!soc_device_match(soc_needs_opt_in
))
748 /* Check whether this SoC can use the IPMMU correctly or not */
749 if (soc_device_match(soc_denylist
))
752 /* Check whether this device can work with the IPMMU */
753 for (i
= 0; i
< ARRAY_SIZE(devices_allowlist
); i
++) {
754 if (!strcmp(dev_name(dev
), devices_allowlist
[i
]))
758 /* Otherwise, do not allow use of IPMMU */
762 static int ipmmu_of_xlate(struct device
*dev
,
763 struct of_phandle_args
*spec
)
765 if (!ipmmu_device_is_allowed(dev
))
768 iommu_fwspec_add_ids(dev
, spec
->args
, 1);
770 /* Initialize once - xlate() will call multiple times */
774 return ipmmu_init_platform_device(dev
, spec
);
777 static int ipmmu_init_arm_mapping(struct device
*dev
)
779 struct ipmmu_vmsa_device
*mmu
= to_ipmmu(dev
);
783 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
784 * VAs. This will allocate a corresponding IOMMU domain.
787 * - Create one mapping per context (TLB).
788 * - Make the mapping size configurable ? We currently use a 2GB mapping
789 * at a 1GB offset to ensure that NULL VAs will fault.
792 struct dma_iommu_mapping
*mapping
;
794 mapping
= arm_iommu_create_mapping(&platform_bus_type
,
796 if (IS_ERR(mapping
)) {
797 dev_err(mmu
->dev
, "failed to create ARM IOMMU mapping\n");
798 ret
= PTR_ERR(mapping
);
802 mmu
->mapping
= mapping
;
805 /* Attach the ARM VA mapping to the device. */
806 ret
= arm_iommu_attach_device(dev
, mmu
->mapping
);
808 dev_err(dev
, "Failed to attach device to VA mapping\n");
816 arm_iommu_release_mapping(mmu
->mapping
);
821 static struct iommu_device
*ipmmu_probe_device(struct device
*dev
)
823 struct ipmmu_vmsa_device
*mmu
= to_ipmmu(dev
);
826 * Only let through devices that have been verified in xlate()
829 return ERR_PTR(-ENODEV
);
834 static void ipmmu_probe_finalize(struct device
*dev
)
838 if (IS_ENABLED(CONFIG_ARM
) && !IS_ENABLED(CONFIG_IOMMU_DMA
))
839 ret
= ipmmu_init_arm_mapping(dev
);
842 dev_err(dev
, "Can't create IOMMU mapping - DMA-OPS will not work\n");
845 static void ipmmu_release_device(struct device
*dev
)
847 arm_iommu_detach_device(dev
);
850 static struct iommu_group
*ipmmu_find_group(struct device
*dev
)
852 struct ipmmu_vmsa_device
*mmu
= to_ipmmu(dev
);
853 struct iommu_group
*group
;
856 return iommu_group_ref_get(mmu
->group
);
858 group
= iommu_group_alloc();
865 static const struct iommu_ops ipmmu_ops
= {
866 .domain_alloc
= ipmmu_domain_alloc
,
867 .domain_free
= ipmmu_domain_free
,
868 .attach_dev
= ipmmu_attach_device
,
869 .detach_dev
= ipmmu_detach_device
,
871 .unmap
= ipmmu_unmap
,
872 .flush_iotlb_all
= ipmmu_flush_iotlb_all
,
873 .iotlb_sync
= ipmmu_iotlb_sync
,
874 .iova_to_phys
= ipmmu_iova_to_phys
,
875 .probe_device
= ipmmu_probe_device
,
876 .release_device
= ipmmu_release_device
,
877 .probe_finalize
= ipmmu_probe_finalize
,
878 .device_group
= IS_ENABLED(CONFIG_ARM
) && !IS_ENABLED(CONFIG_IOMMU_DMA
)
879 ? generic_device_group
: ipmmu_find_group
,
880 .pgsize_bitmap
= SZ_1G
| SZ_2M
| SZ_4K
,
881 .of_xlate
= ipmmu_of_xlate
,
884 /* -----------------------------------------------------------------------------
885 * Probe/remove and init
888 static void ipmmu_device_reset(struct ipmmu_vmsa_device
*mmu
)
892 /* Disable all contexts. */
893 for (i
= 0; i
< mmu
->num_ctx
; ++i
)
894 ipmmu_ctx_write(mmu
, i
, IMCTR
, 0);
897 static const struct ipmmu_features ipmmu_features_default
= {
898 .use_ns_alias_offset
= true,
899 .has_cache_leaf_nodes
= false,
900 .number_of_contexts
= 1, /* software only tested with one context */
902 .setup_imbuscr
= true,
903 .twobit_imttbcr_sl0
= false,
904 .reserved_context
= false,
906 .ctx_offset_base
= 0,
907 .ctx_offset_stride
= 0x40,
908 .utlb_offset_base
= 0,
911 static const struct ipmmu_features ipmmu_features_rcar_gen3
= {
912 .use_ns_alias_offset
= false,
913 .has_cache_leaf_nodes
= true,
914 .number_of_contexts
= 8,
916 .setup_imbuscr
= false,
917 .twobit_imttbcr_sl0
= true,
918 .reserved_context
= true,
919 .cache_snoop
= false,
920 .ctx_offset_base
= 0,
921 .ctx_offset_stride
= 0x40,
922 .utlb_offset_base
= 0,
925 static const struct of_device_id ipmmu_of_ids
[] = {
927 .compatible
= "renesas,ipmmu-vmsa",
928 .data
= &ipmmu_features_default
,
930 .compatible
= "renesas,ipmmu-r8a774a1",
931 .data
= &ipmmu_features_rcar_gen3
,
933 .compatible
= "renesas,ipmmu-r8a774b1",
934 .data
= &ipmmu_features_rcar_gen3
,
936 .compatible
= "renesas,ipmmu-r8a774c0",
937 .data
= &ipmmu_features_rcar_gen3
,
939 .compatible
= "renesas,ipmmu-r8a774e1",
940 .data
= &ipmmu_features_rcar_gen3
,
942 .compatible
= "renesas,ipmmu-r8a7795",
943 .data
= &ipmmu_features_rcar_gen3
,
945 .compatible
= "renesas,ipmmu-r8a7796",
946 .data
= &ipmmu_features_rcar_gen3
,
948 .compatible
= "renesas,ipmmu-r8a77961",
949 .data
= &ipmmu_features_rcar_gen3
,
951 .compatible
= "renesas,ipmmu-r8a77965",
952 .data
= &ipmmu_features_rcar_gen3
,
954 .compatible
= "renesas,ipmmu-r8a77970",
955 .data
= &ipmmu_features_rcar_gen3
,
957 .compatible
= "renesas,ipmmu-r8a77990",
958 .data
= &ipmmu_features_rcar_gen3
,
960 .compatible
= "renesas,ipmmu-r8a77995",
961 .data
= &ipmmu_features_rcar_gen3
,
967 static int ipmmu_probe(struct platform_device
*pdev
)
969 struct ipmmu_vmsa_device
*mmu
;
970 struct resource
*res
;
974 mmu
= devm_kzalloc(&pdev
->dev
, sizeof(*mmu
), GFP_KERNEL
);
976 dev_err(&pdev
->dev
, "cannot allocate device data\n");
980 mmu
->dev
= &pdev
->dev
;
981 spin_lock_init(&mmu
->lock
);
982 bitmap_zero(mmu
->ctx
, IPMMU_CTX_MAX
);
983 mmu
->features
= of_device_get_match_data(&pdev
->dev
);
984 memset(mmu
->utlb_ctx
, IPMMU_CTX_INVALID
, mmu
->features
->num_utlbs
);
985 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(40));
989 /* Map I/O memory and request IRQ. */
990 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
991 mmu
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
992 if (IS_ERR(mmu
->base
))
993 return PTR_ERR(mmu
->base
);
996 * The IPMMU has two register banks, for secure and non-secure modes.
997 * The bank mapped at the beginning of the IPMMU address space
998 * corresponds to the running mode of the CPU. When running in secure
999 * mode the non-secure register bank is also available at an offset.
1001 * Secure mode operation isn't clearly documented and is thus currently
1002 * not implemented in the driver. Furthermore, preliminary tests of
1003 * non-secure operation with the main register bank were not successful.
1004 * Offset the registers base unconditionally to point to the non-secure
1005 * alias space for now.
1007 if (mmu
->features
->use_ns_alias_offset
)
1008 mmu
->base
+= IM_NS_ALIAS_OFFSET
;
1010 mmu
->num_ctx
= min(IPMMU_CTX_MAX
, mmu
->features
->number_of_contexts
);
1013 * Determine if this IPMMU instance is a root device by checking for
1014 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
1016 if (!mmu
->features
->has_cache_leaf_nodes
||
1017 !of_find_property(pdev
->dev
.of_node
, "renesas,ipmmu-main", NULL
))
1020 mmu
->root
= ipmmu_find_root();
1023 * Wait until the root device has been registered for sure.
1026 return -EPROBE_DEFER
;
1028 /* Root devices have mandatory IRQs */
1029 if (ipmmu_is_root(mmu
)) {
1030 irq
= platform_get_irq(pdev
, 0);
1034 ret
= devm_request_irq(&pdev
->dev
, irq
, ipmmu_irq
, 0,
1035 dev_name(&pdev
->dev
), mmu
);
1037 dev_err(&pdev
->dev
, "failed to request IRQ %d\n", irq
);
1041 ipmmu_device_reset(mmu
);
1043 if (mmu
->features
->reserved_context
) {
1044 dev_info(&pdev
->dev
, "IPMMU context 0 is reserved\n");
1045 set_bit(0, mmu
->ctx
);
1050 * Register the IPMMU to the IOMMU subsystem in the following cases:
1051 * - R-Car Gen2 IPMMU (all devices registered)
1052 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
1054 if (!mmu
->features
->has_cache_leaf_nodes
|| !ipmmu_is_root(mmu
)) {
1055 ret
= iommu_device_sysfs_add(&mmu
->iommu
, &pdev
->dev
, NULL
,
1056 dev_name(&pdev
->dev
));
1060 ret
= iommu_device_register(&mmu
->iommu
, &ipmmu_ops
, &pdev
->dev
);
1064 #if defined(CONFIG_IOMMU_DMA)
1065 if (!iommu_present(&platform_bus_type
))
1066 bus_set_iommu(&platform_bus_type
, &ipmmu_ops
);
1071 * We can't create the ARM mapping here as it requires the bus to have
1072 * an IOMMU, which only happens when bus_set_iommu() is called in
1073 * ipmmu_init() after the probe function returns.
1076 platform_set_drvdata(pdev
, mmu
);
1081 static int ipmmu_remove(struct platform_device
*pdev
)
1083 struct ipmmu_vmsa_device
*mmu
= platform_get_drvdata(pdev
);
1085 iommu_device_sysfs_remove(&mmu
->iommu
);
1086 iommu_device_unregister(&mmu
->iommu
);
1088 arm_iommu_release_mapping(mmu
->mapping
);
1090 ipmmu_device_reset(mmu
);
1095 #ifdef CONFIG_PM_SLEEP
1096 static int ipmmu_resume_noirq(struct device
*dev
)
1098 struct ipmmu_vmsa_device
*mmu
= dev_get_drvdata(dev
);
1101 /* Reset root MMU and restore contexts */
1102 if (ipmmu_is_root(mmu
)) {
1103 ipmmu_device_reset(mmu
);
1105 for (i
= 0; i
< mmu
->num_ctx
; i
++) {
1106 if (!mmu
->domains
[i
])
1109 ipmmu_domain_setup_context(mmu
->domains
[i
]);
1113 /* Re-enable active micro-TLBs */
1114 for (i
= 0; i
< mmu
->features
->num_utlbs
; i
++) {
1115 if (mmu
->utlb_ctx
[i
] == IPMMU_CTX_INVALID
)
1118 ipmmu_utlb_enable(mmu
->root
->domains
[mmu
->utlb_ctx
[i
]], i
);
1124 static const struct dev_pm_ops ipmmu_pm
= {
1125 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL
, ipmmu_resume_noirq
)
1127 #define DEV_PM_OPS &ipmmu_pm
1129 #define DEV_PM_OPS NULL
1130 #endif /* CONFIG_PM_SLEEP */
1132 static struct platform_driver ipmmu_driver
= {
1134 .name
= "ipmmu-vmsa",
1135 .of_match_table
= of_match_ptr(ipmmu_of_ids
),
1138 .probe
= ipmmu_probe
,
1139 .remove
= ipmmu_remove
,
1142 static int __init
ipmmu_init(void)
1144 struct device_node
*np
;
1145 static bool setup_done
;
1151 np
= of_find_matching_node(NULL
, ipmmu_of_ids
);
1157 ret
= platform_driver_register(&ipmmu_driver
);
1161 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
1162 if (!iommu_present(&platform_bus_type
))
1163 bus_set_iommu(&platform_bus_type
, &ipmmu_ops
);
1169 subsys_initcall(ipmmu_init
);