2 * IOMMU API for SMMU in Tegra30
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #define pr_fmt(fmt) "%s(): " fmt, __func__
22 #include <linux/err.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/spinlock.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/device.h>
31 #include <linux/sched.h>
32 #include <linux/iommu.h>
35 #include <linux/of_iommu.h>
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
38 #include <linux/tegra-ahb.h>
41 #include <asm/cacheflush.h>
66 #define HWG_AFI (1 << HWGRP_AFI)
67 #define HWG_AVPC (1 << HWGRP_AVPC)
68 #define HWG_DC (1 << HWGRP_DC)
69 #define HWG_DCB (1 << HWGRP_DCB)
70 #define HWG_EPP (1 << HWGRP_EPP)
71 #define HWG_G2 (1 << HWGRP_G2)
72 #define HWG_HC (1 << HWGRP_HC)
73 #define HWG_HDA (1 << HWGRP_HDA)
74 #define HWG_ISP (1 << HWGRP_ISP)
75 #define HWG_MPE (1 << HWGRP_MPE)
76 #define HWG_NV (1 << HWGRP_NV)
77 #define HWG_NV2 (1 << HWGRP_NV2)
78 #define HWG_PPCS (1 << HWGRP_PPCS)
79 #define HWG_SATA (1 << HWGRP_SATA)
80 #define HWG_VDE (1 << HWGRP_VDE)
81 #define HWG_VI (1 << HWGRP_VI)
83 /* bitmap of the page sizes currently supported */
84 #define SMMU_IOMMU_PGSIZES (SZ_4K)
86 #define SMMU_CONFIG 0x10
87 #define SMMU_CONFIG_DISABLE 0
88 #define SMMU_CONFIG_ENABLE 1
90 /* REVISIT: To support multiple MCs */
100 #define SMMU_CACHE_CONFIG_BASE 0x14
101 #define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
102 #define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
104 #define SMMU_CACHE_CONFIG_STATS_SHIFT 31
105 #define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
106 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30
107 #define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
109 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
110 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
111 #define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
113 #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
114 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
115 #define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
117 #define SMMU_PTB_ASID 0x1c
118 #define SMMU_PTB_ASID_CURRENT_SHIFT 0
120 #define SMMU_PTB_DATA 0x20
121 #define SMMU_PTB_DATA_RESET_VAL 0
122 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
123 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
124 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
126 #define SMMU_TLB_FLUSH 0x30
127 #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
128 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
129 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
130 #define SMMU_TLB_FLUSH_ASID_SHIFT 29
131 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
132 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
133 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
135 #define SMMU_PTC_FLUSH 0x34
136 #define SMMU_PTC_FLUSH_TYPE_ALL 0
137 #define SMMU_PTC_FLUSH_TYPE_ADR 1
138 #define SMMU_PTC_FLUSH_ADR_SHIFT 4
140 #define SMMU_ASID_SECURITY 0x38
142 #define SMMU_STATS_CACHE_COUNT_BASE 0x1f0
144 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
145 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
147 #define SMMU_TRANSLATION_ENABLE_0 0x228
148 #define SMMU_TRANSLATION_ENABLE_1 0x22c
149 #define SMMU_TRANSLATION_ENABLE_2 0x230
151 #define SMMU_AFI_ASID 0x238 /* PCIE */
152 #define SMMU_AVPC_ASID 0x23c /* AVP */
153 #define SMMU_DC_ASID 0x240 /* Display controller */
154 #define SMMU_DCB_ASID 0x244 /* Display controller B */
155 #define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
156 #define SMMU_G2_ASID 0x24c /* 2D engine */
157 #define SMMU_HC_ASID 0x250 /* Host1x */
158 #define SMMU_HDA_ASID 0x254 /* High-def audio */
159 #define SMMU_ISP_ASID 0x258 /* Image signal processor */
160 #define SMMU_MPE_ASID 0x264 /* MPEG encoder */
161 #define SMMU_NV_ASID 0x268 /* (3D) */
162 #define SMMU_NV2_ASID 0x26c /* (3D) */
163 #define SMMU_PPCS_ASID 0x270 /* AHB */
164 #define SMMU_SATA_ASID 0x278 /* SATA */
165 #define SMMU_VDE_ASID 0x27c /* Video decoder */
166 #define SMMU_VI_ASID 0x280 /* Video input */
168 #define SMMU_PDE_NEXT_SHIFT 28
170 #define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
171 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
172 #define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
173 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
174 #define SMMU_TLB_FLUSH_VA(iova, which) \
175 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
176 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
177 SMMU_TLB_FLUSH_VA_MATCH_##which)
178 #define SMMU_PTB_ASID_CUR(n) \
179 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
180 #define SMMU_TLB_FLUSH_ASID_MATCH_disable \
181 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
182 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
183 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
184 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
185 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
187 #define SMMU_PAGE_SHIFT 12
188 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
189 #define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
191 #define SMMU_PDIR_COUNT 1024
192 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
193 #define SMMU_PTBL_COUNT 1024
194 #define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
195 #define SMMU_PDIR_SHIFT 12
196 #define SMMU_PDE_SHIFT 12
197 #define SMMU_PTE_SHIFT 12
198 #define SMMU_PFN_MASK 0x000fffff
200 #define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
201 #define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
202 #define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22)
204 #define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
205 #define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
206 #define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
207 #define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
208 #define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
210 #define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
212 #define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
213 #define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
214 #define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
216 #define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
217 #define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
219 #define SMMU_MK_PDIR(page, attr) \
220 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
221 #define SMMU_MK_PDE(page, attr) \
222 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
223 #define SMMU_EX_PTBL_PAGE(pde) \
224 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
225 #define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
227 #define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
228 #define SMMU_ASID_DISABLE 0
229 #define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
231 #define NUM_SMMU_REG_BANKS 3
233 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
234 #define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
235 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
236 #define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
238 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
240 static const u32 smmu_hwgrp_asid_reg
[] = {
258 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
261 * Per client for address space
265 struct list_head list
;
274 struct smmu_device
*smmu
; /* back pointer to container */
276 spinlock_t lock
; /* for pagetable */
277 struct page
*pdir_page
;
278 unsigned long pdir_attr
;
279 unsigned long pde_attr
;
280 unsigned long pte_attr
;
281 unsigned int *pte_count
;
283 struct list_head client
;
284 spinlock_t client_lock
; /* for client list */
287 struct smmu_debugfs_info
{
288 struct smmu_device
*smmu
;
294 * Per SMMU device - IOMMU device
297 void __iomem
*regs
[NUM_SMMU_REG_BANKS
];
298 unsigned long iovmm_base
; /* remappable base address */
299 unsigned long page_count
; /* total remappable size */
303 struct page
*avp_vector_page
; /* dummy page shared by all AS's */
306 * Register image savers for suspend/resume
308 unsigned long translation_enable_0
;
309 unsigned long translation_enable_1
;
310 unsigned long translation_enable_2
;
311 unsigned long asid_security
;
313 struct dentry
*debugfs_root
;
314 struct smmu_debugfs_info
*debugfs_info
;
316 struct device_node
*ahb
;
319 struct smmu_as as
[0]; /* Run-time allocated array */
322 static struct smmu_device
*smmu_handle
; /* unique for a system */
325 * SMMU register accessors
327 static inline u32
smmu_read(struct smmu_device
*smmu
, size_t offs
)
331 return readl(smmu
->regs
[0] + offs
- 0x10);
332 BUG_ON(offs
< 0x1f0);
334 return readl(smmu
->regs
[1] + offs
- 0x1f0);
335 BUG_ON(offs
< 0x228);
337 return readl(smmu
->regs
[2] + offs
- 0x228);
341 static inline void smmu_write(struct smmu_device
*smmu
, u32 val
, size_t offs
)
345 writel(val
, smmu
->regs
[0] + offs
- 0x10);
348 BUG_ON(offs
< 0x1f0);
350 writel(val
, smmu
->regs
[1] + offs
- 0x1f0);
353 BUG_ON(offs
< 0x228);
355 writel(val
, smmu
->regs
[2] + offs
- 0x228);
361 #define VA_PAGE_TO_PA(va, page) \
362 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
364 #define FLUSH_CPU_DCACHE(va, page, size) \
366 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
367 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
368 outer_flush_range(_pa_, _pa_+(size_t)(size)); \
372 * Any interaction between any block on PPSB and a block on APB or AHB
373 * must have these read-back barriers to ensure the APB/AHB bus
374 * transaction is complete before initiating activity on the PPSB
377 #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
379 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
381 static int __smmu_client_set_hwgrp(struct smmu_client
*c
,
382 unsigned long map
, int on
)
385 struct smmu_as
*as
= c
->as
;
386 u32 val
, offs
, mask
= SMMU_ASID_ENABLE(as
->asid
);
387 struct smmu_device
*smmu
= as
->smmu
;
393 map
= smmu_client_hwgrp(c
);
395 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
396 offs
= HWGRP_ASID_REG(i
);
397 val
= smmu_read(smmu
, offs
);
399 if (WARN_ON(val
& mask
))
403 WARN_ON((val
& mask
) == mask
);
406 smmu_write(smmu
, val
, offs
);
408 FLUSH_SMMU_REGS(smmu
);
413 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
414 offs
= HWGRP_ASID_REG(i
);
415 val
= smmu_read(smmu
, offs
);
417 smmu_write(smmu
, val
, offs
);
422 static int smmu_client_set_hwgrp(struct smmu_client
*c
, u32 map
, int on
)
426 struct smmu_as
*as
= c
->as
;
427 struct smmu_device
*smmu
= as
->smmu
;
429 spin_lock_irqsave(&smmu
->lock
, flags
);
430 val
= __smmu_client_set_hwgrp(c
, map
, on
);
431 spin_unlock_irqrestore(&smmu
->lock
, flags
);
436 * Flush all TLB entries and all PTC entries
437 * Caller must lock smmu
439 static void smmu_flush_regs(struct smmu_device
*smmu
, int enable
)
443 smmu_write(smmu
, SMMU_PTC_FLUSH_TYPE_ALL
, SMMU_PTC_FLUSH
);
444 FLUSH_SMMU_REGS(smmu
);
445 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
446 SMMU_TLB_FLUSH_ASID_MATCH_disable
;
447 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
450 smmu_write(smmu
, SMMU_CONFIG_ENABLE
, SMMU_CONFIG
);
451 FLUSH_SMMU_REGS(smmu
);
454 static int smmu_setup_regs(struct smmu_device
*smmu
)
459 for (i
= 0; i
< smmu
->num_as
; i
++) {
460 struct smmu_as
*as
= &smmu
->as
[i
];
461 struct smmu_client
*c
;
463 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
464 val
= as
->pdir_page
?
465 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
) :
466 SMMU_PTB_DATA_RESET_VAL
;
467 smmu_write(smmu
, val
, SMMU_PTB_DATA
);
469 list_for_each_entry(c
, &as
->client
, list
)
470 __smmu_client_set_hwgrp(c
, c
->hwgrp
, 1);
473 smmu_write(smmu
, smmu
->translation_enable_0
, SMMU_TRANSLATION_ENABLE_0
);
474 smmu_write(smmu
, smmu
->translation_enable_1
, SMMU_TRANSLATION_ENABLE_1
);
475 smmu_write(smmu
, smmu
->translation_enable_2
, SMMU_TRANSLATION_ENABLE_2
);
476 smmu_write(smmu
, smmu
->asid_security
, SMMU_ASID_SECURITY
);
477 smmu_write(smmu
, SMMU_TLB_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_TLB
));
478 smmu_write(smmu
, SMMU_PTC_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_PTC
));
480 smmu_flush_regs(smmu
, 1);
482 return tegra_ahb_enable_smmu(smmu
->ahb
);
485 static void flush_ptc_and_tlb(struct smmu_device
*smmu
,
486 struct smmu_as
*as
, dma_addr_t iova
,
487 unsigned long *pte
, struct page
*page
, int is_pde
)
490 unsigned long tlb_flush_va
= is_pde
491 ? SMMU_TLB_FLUSH_VA(iova
, SECTION
)
492 : SMMU_TLB_FLUSH_VA(iova
, GROUP
);
494 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pte
, page
);
495 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
496 FLUSH_SMMU_REGS(smmu
);
498 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
499 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
500 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
501 FLUSH_SMMU_REGS(smmu
);
504 static void free_ptbl(struct smmu_as
*as
, dma_addr_t iova
)
506 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
507 unsigned long *pdir
= (unsigned long *)page_address(as
->pdir_page
);
509 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
510 dev_dbg(as
->smmu
->dev
, "pdn: %lx\n", pdn
);
512 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
513 __free_page(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
514 pdir
[pdn
] = _PDE_VACANT(pdn
);
515 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
516 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
521 static void free_pdir(struct smmu_as
*as
)
525 struct device
*dev
= as
->smmu
->dev
;
530 addr
= as
->smmu
->iovmm_base
;
531 count
= as
->smmu
->page_count
;
532 while (count
-- > 0) {
534 addr
+= SMMU_PAGE_SIZE
* SMMU_PTBL_COUNT
;
536 ClearPageReserved(as
->pdir_page
);
537 __free_page(as
->pdir_page
);
538 as
->pdir_page
= NULL
;
539 devm_kfree(dev
, as
->pte_count
);
540 as
->pte_count
= NULL
;
544 * Maps PTBL for given iova and returns the PTE address
545 * Caller must unmap the mapped PTBL returned in *ptbl_page_p
547 static unsigned long *locate_pte(struct smmu_as
*as
,
548 dma_addr_t iova
, bool allocate
,
549 struct page
**ptbl_page_p
,
550 unsigned int **count
)
552 unsigned long ptn
= SMMU_ADDR_TO_PFN(iova
);
553 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
554 unsigned long *pdir
= page_address(as
->pdir_page
);
557 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
558 /* Mapped entry table already exists */
559 *ptbl_page_p
= SMMU_EX_PTBL_PAGE(pdir
[pdn
]);
560 ptbl
= page_address(*ptbl_page_p
);
561 } else if (!allocate
) {
565 unsigned long addr
= SMMU_PDN_TO_ADDR(pdn
);
567 /* Vacant - allocate a new page table */
568 dev_dbg(as
->smmu
->dev
, "New PTBL pdn: %lx\n", pdn
);
570 *ptbl_page_p
= alloc_page(GFP_ATOMIC
);
572 dev_err(as
->smmu
->dev
,
573 "failed to allocate smmu_device page table\n");
576 SetPageReserved(*ptbl_page_p
);
577 ptbl
= (unsigned long *)page_address(*ptbl_page_p
);
578 for (pn
= 0; pn
< SMMU_PTBL_COUNT
;
579 pn
++, addr
+= SMMU_PAGE_SIZE
) {
580 ptbl
[pn
] = _PTE_VACANT(addr
);
582 FLUSH_CPU_DCACHE(ptbl
, *ptbl_page_p
, SMMU_PTBL_SIZE
);
583 pdir
[pdn
] = SMMU_MK_PDE(*ptbl_page_p
,
584 as
->pde_attr
| _PDE_NEXT
);
585 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
586 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
589 *count
= &as
->pte_count
[pdn
];
591 return &ptbl
[ptn
% SMMU_PTBL_COUNT
];
594 #ifdef CONFIG_SMMU_SIG_DEBUG
595 static void put_signature(struct smmu_as
*as
,
596 dma_addr_t iova
, unsigned long pfn
)
599 unsigned long *vaddr
;
601 page
= pfn_to_page(pfn
);
602 vaddr
= page_address(page
);
607 vaddr
[1] = pfn
<< PAGE_SHIFT
;
608 FLUSH_CPU_DCACHE(vaddr
, page
, sizeof(vaddr
[0]) * 2);
611 static inline void put_signature(struct smmu_as
*as
,
612 unsigned long addr
, unsigned long pfn
)
618 * Caller must not hold as->lock
620 static int alloc_pdir(struct smmu_as
*as
)
622 unsigned long *pdir
, flags
;
625 struct smmu_device
*smmu
= as
->smmu
;
630 * do the allocation, then grab as->lock
632 cnt
= devm_kzalloc(smmu
->dev
,
633 sizeof(cnt
[0]) * SMMU_PDIR_COUNT
,
635 page
= alloc_page(GFP_KERNEL
| __GFP_DMA
);
637 spin_lock_irqsave(&as
->lock
, flags
);
640 /* We raced, free the redundant */
646 dev_err(smmu
->dev
, "failed to allocate at %s\n", __func__
);
651 as
->pdir_page
= page
;
654 SetPageReserved(as
->pdir_page
);
655 pdir
= page_address(as
->pdir_page
);
657 for (pdn
= 0; pdn
< SMMU_PDIR_COUNT
; pdn
++)
658 pdir
[pdn
] = _PDE_VACANT(pdn
);
659 FLUSH_CPU_DCACHE(pdir
, as
->pdir_page
, SMMU_PDIR_SIZE
);
660 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pdir
, as
->pdir_page
);
661 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
662 FLUSH_SMMU_REGS(as
->smmu
);
663 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
664 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
665 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
666 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
667 FLUSH_SMMU_REGS(as
->smmu
);
669 spin_unlock_irqrestore(&as
->lock
, flags
);
674 spin_unlock_irqrestore(&as
->lock
, flags
);
676 devm_kfree(smmu
->dev
, cnt
);
682 static void __smmu_iommu_unmap(struct smmu_as
*as
, dma_addr_t iova
)
688 pte
= locate_pte(as
, iova
, false, &page
, &count
);
692 if (WARN_ON(*pte
== _PTE_VACANT(iova
)))
695 *pte
= _PTE_VACANT(iova
);
696 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
697 flush_ptc_and_tlb(as
->smmu
, as
, iova
, pte
, page
, 0);
702 static void __smmu_iommu_map_pfn(struct smmu_as
*as
, dma_addr_t iova
,
705 struct smmu_device
*smmu
= as
->smmu
;
710 pte
= locate_pte(as
, iova
, true, &page
, &count
);
714 if (*pte
== _PTE_VACANT(iova
))
716 *pte
= SMMU_PFN_TO_PTE(pfn
, as
->pte_attr
);
717 if (unlikely((*pte
== _PTE_VACANT(iova
))))
719 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
720 flush_ptc_and_tlb(smmu
, as
, iova
, pte
, page
, 0);
721 put_signature(as
, iova
, pfn
);
724 static int smmu_iommu_map(struct iommu_domain
*domain
, unsigned long iova
,
725 phys_addr_t pa
, size_t bytes
, int prot
)
727 struct smmu_as
*as
= domain
->priv
;
728 unsigned long pfn
= __phys_to_pfn(pa
);
731 dev_dbg(as
->smmu
->dev
, "[%d] %08lx:%08x\n", as
->asid
, iova
, pa
);
736 spin_lock_irqsave(&as
->lock
, flags
);
737 __smmu_iommu_map_pfn(as
, iova
, pfn
);
738 spin_unlock_irqrestore(&as
->lock
, flags
);
742 static size_t smmu_iommu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
745 struct smmu_as
*as
= domain
->priv
;
748 dev_dbg(as
->smmu
->dev
, "[%d] %08lx\n", as
->asid
, iova
);
750 spin_lock_irqsave(&as
->lock
, flags
);
751 __smmu_iommu_unmap(as
, iova
);
752 spin_unlock_irqrestore(&as
->lock
, flags
);
753 return SMMU_PAGE_SIZE
;
756 static phys_addr_t
smmu_iommu_iova_to_phys(struct iommu_domain
*domain
,
759 struct smmu_as
*as
= domain
->priv
;
766 spin_lock_irqsave(&as
->lock
, flags
);
768 pte
= locate_pte(as
, iova
, true, &page
, &count
);
769 pfn
= *pte
& SMMU_PFN_MASK
;
770 WARN_ON(!pfn_valid(pfn
));
771 dev_dbg(as
->smmu
->dev
,
772 "iova:%08lx pfn:%08lx asid:%d\n", iova
, pfn
, as
->asid
);
774 spin_unlock_irqrestore(&as
->lock
, flags
);
775 return PFN_PHYS(pfn
);
778 static int smmu_iommu_domain_has_cap(struct iommu_domain
*domain
,
784 static int smmu_iommu_attach_dev(struct iommu_domain
*domain
,
787 struct smmu_as
*as
= domain
->priv
;
788 struct smmu_device
*smmu
= as
->smmu
;
789 struct smmu_client
*client
, *c
;
793 client
= devm_kzalloc(smmu
->dev
, sizeof(*c
), GFP_KERNEL
);
798 map
= (unsigned long)dev
->platform_data
;
802 err
= smmu_client_enable_hwgrp(client
, map
);
806 spin_lock(&as
->client_lock
);
807 list_for_each_entry(c
, &as
->client
, list
) {
810 "%s is already attached\n", dev_name(c
->dev
));
815 list_add(&client
->list
, &as
->client
);
816 spin_unlock(&as
->client_lock
);
819 * Reserve "page zero" for AVP vectors using a common dummy
822 if (map
& HWG_AVPC
) {
825 page
= as
->smmu
->avp_vector_page
;
826 __smmu_iommu_map_pfn(as
, 0, page_to_pfn(page
));
828 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
831 dev_dbg(smmu
->dev
, "%s is attached\n", dev_name(dev
));
835 smmu_client_disable_hwgrp(client
);
836 spin_unlock(&as
->client_lock
);
838 devm_kfree(smmu
->dev
, client
);
842 static void smmu_iommu_detach_dev(struct iommu_domain
*domain
,
845 struct smmu_as
*as
= domain
->priv
;
846 struct smmu_device
*smmu
= as
->smmu
;
847 struct smmu_client
*c
;
849 spin_lock(&as
->client_lock
);
851 list_for_each_entry(c
, &as
->client
, list
) {
853 smmu_client_disable_hwgrp(c
);
855 devm_kfree(smmu
->dev
, c
);
858 "%s is detached\n", dev_name(c
->dev
));
862 dev_err(smmu
->dev
, "Couldn't find %s\n", dev_name(dev
));
864 spin_unlock(&as
->client_lock
);
867 static int smmu_iommu_domain_init(struct iommu_domain
*domain
)
869 int i
, err
= -EAGAIN
;
872 struct smmu_device
*smmu
= smmu_handle
;
874 /* Look for a free AS with lock held */
875 for (i
= 0; i
< smmu
->num_as
; i
++) {
881 err
= alloc_pdir(as
);
888 if (i
== smmu
->num_as
)
889 dev_err(smmu
->dev
, "no free AS\n");
893 spin_lock_irqsave(&smmu
->lock
, flags
);
895 /* Update PDIR register */
896 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
898 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
), SMMU_PTB_DATA
);
899 FLUSH_SMMU_REGS(smmu
);
901 spin_unlock_irqrestore(&smmu
->lock
, flags
);
905 domain
->geometry
.aperture_start
= smmu
->iovmm_base
;
906 domain
->geometry
.aperture_end
= smmu
->iovmm_base
+
907 smmu
->page_count
* SMMU_PAGE_SIZE
- 1;
908 domain
->geometry
.force_aperture
= true;
910 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
915 static void smmu_iommu_domain_destroy(struct iommu_domain
*domain
)
917 struct smmu_as
*as
= domain
->priv
;
918 struct smmu_device
*smmu
= as
->smmu
;
921 spin_lock_irqsave(&as
->lock
, flags
);
924 spin_lock(&smmu
->lock
);
925 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
926 smmu_write(smmu
, SMMU_PTB_DATA_RESET_VAL
, SMMU_PTB_DATA
);
927 FLUSH_SMMU_REGS(smmu
);
928 spin_unlock(&smmu
->lock
);
933 if (!list_empty(&as
->client
)) {
934 struct smmu_client
*c
;
936 list_for_each_entry(c
, &as
->client
, list
)
937 smmu_iommu_detach_dev(domain
, c
->dev
);
940 spin_unlock_irqrestore(&as
->lock
, flags
);
943 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
946 static struct iommu_ops smmu_iommu_ops
= {
947 .domain_init
= smmu_iommu_domain_init
,
948 .domain_destroy
= smmu_iommu_domain_destroy
,
949 .attach_dev
= smmu_iommu_attach_dev
,
950 .detach_dev
= smmu_iommu_detach_dev
,
951 .map
= smmu_iommu_map
,
952 .unmap
= smmu_iommu_unmap
,
953 .iova_to_phys
= smmu_iommu_iova_to_phys
,
954 .domain_has_cap
= smmu_iommu_domain_has_cap
,
955 .pgsize_bitmap
= SMMU_IOMMU_PGSIZES
,
958 /* Should be in the order of enum */
959 static const char * const smmu_debugfs_mc
[] = { "mc", };
960 static const char * const smmu_debugfs_cache
[] = { "tlb", "ptc", };
962 static ssize_t
smmu_debugfs_stats_write(struct file
*file
,
963 const char __user
*buffer
,
964 size_t count
, loff_t
*pos
)
966 struct smmu_debugfs_info
*info
;
967 struct smmu_device
*smmu
;
975 const char * const command
[] = {
980 char str
[] = "reset";
984 count
= min_t(size_t, count
, sizeof(str
));
985 if (copy_from_user(str
, buffer
, count
))
988 for (i
= 0; i
< ARRAY_SIZE(command
); i
++)
989 if (strncmp(str
, command
[i
],
990 strlen(command
[i
])) == 0)
993 if (i
== ARRAY_SIZE(command
))
996 dent
= file
->f_dentry
;
997 info
= dent
->d_inode
->i_private
;
1000 offs
= SMMU_CACHE_CONFIG(info
->cache
);
1001 val
= smmu_read(smmu
, offs
);
1004 val
&= ~SMMU_CACHE_CONFIG_STATS_ENABLE
;
1005 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1006 smmu_write(smmu
, val
, offs
);
1009 val
|= SMMU_CACHE_CONFIG_STATS_ENABLE
;
1010 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1011 smmu_write(smmu
, val
, offs
);
1014 val
|= SMMU_CACHE_CONFIG_STATS_TEST
;
1015 smmu_write(smmu
, val
, offs
);
1016 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1017 smmu_write(smmu
, val
, offs
);
1024 dev_dbg(smmu
->dev
, "%s() %08x, %08x @%08x\n", __func__
,
1025 val
, smmu_read(smmu
, offs
), offs
);
1030 static int smmu_debugfs_stats_show(struct seq_file
*s
, void *v
)
1032 struct smmu_debugfs_info
*info
;
1033 struct smmu_device
*smmu
;
1034 struct dentry
*dent
;
1036 const char * const stats
[] = { "hit", "miss", };
1038 dent
= d_find_alias(s
->private);
1039 info
= dent
->d_inode
->i_private
;
1042 for (i
= 0; i
< ARRAY_SIZE(stats
); i
++) {
1046 offs
= SMMU_STATS_CACHE_COUNT(info
->mc
, info
->cache
, i
);
1047 val
= smmu_read(smmu
, offs
);
1048 seq_printf(s
, "%s:%08x ", stats
[i
], val
);
1050 dev_dbg(smmu
->dev
, "%s() %s %08x @%08x\n", __func__
,
1051 stats
[i
], val
, offs
);
1053 seq_printf(s
, "\n");
1059 static int smmu_debugfs_stats_open(struct inode
*inode
, struct file
*file
)
1061 return single_open(file
, smmu_debugfs_stats_show
, inode
);
1064 static const struct file_operations smmu_debugfs_stats_fops
= {
1065 .open
= smmu_debugfs_stats_open
,
1067 .llseek
= seq_lseek
,
1068 .release
= single_release
,
1069 .write
= smmu_debugfs_stats_write
,
1072 static void smmu_debugfs_delete(struct smmu_device
*smmu
)
1074 debugfs_remove_recursive(smmu
->debugfs_root
);
1075 kfree(smmu
->debugfs_info
);
1078 static void smmu_debugfs_create(struct smmu_device
*smmu
)
1082 struct dentry
*root
;
1084 bytes
= ARRAY_SIZE(smmu_debugfs_mc
) * ARRAY_SIZE(smmu_debugfs_cache
) *
1085 sizeof(*smmu
->debugfs_info
);
1086 smmu
->debugfs_info
= kmalloc(bytes
, GFP_KERNEL
);
1087 if (!smmu
->debugfs_info
)
1090 root
= debugfs_create_dir(dev_name(smmu
->dev
), NULL
);
1093 smmu
->debugfs_root
= root
;
1095 for (i
= 0; i
< ARRAY_SIZE(smmu_debugfs_mc
); i
++) {
1099 mc
= debugfs_create_dir(smmu_debugfs_mc
[i
], root
);
1103 for (j
= 0; j
< ARRAY_SIZE(smmu_debugfs_cache
); j
++) {
1104 struct dentry
*cache
;
1105 struct smmu_debugfs_info
*info
;
1107 info
= smmu
->debugfs_info
;
1108 info
+= i
* ARRAY_SIZE(smmu_debugfs_mc
) + j
;
1113 cache
= debugfs_create_file(smmu_debugfs_cache
[j
],
1114 S_IWUGO
| S_IRUGO
, mc
,
1116 &smmu_debugfs_stats_fops
);
1125 smmu_debugfs_delete(smmu
);
1128 static int tegra_smmu_suspend(struct device
*dev
)
1130 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1132 smmu
->translation_enable_0
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_0
);
1133 smmu
->translation_enable_1
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_1
);
1134 smmu
->translation_enable_2
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_2
);
1135 smmu
->asid_security
= smmu_read(smmu
, SMMU_ASID_SECURITY
);
1139 static int tegra_smmu_resume(struct device
*dev
)
1141 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1142 unsigned long flags
;
1145 spin_lock_irqsave(&smmu
->lock
, flags
);
1146 err
= smmu_setup_regs(smmu
);
1147 spin_unlock_irqrestore(&smmu
->lock
, flags
);
1151 static int tegra_smmu_probe(struct platform_device
*pdev
)
1153 struct smmu_device
*smmu
;
1154 struct device
*dev
= &pdev
->dev
;
1155 int i
, asids
, err
= 0;
1156 dma_addr_t
uninitialized_var(base
);
1157 size_t bytes
, uninitialized_var(size
);
1162 BUILD_BUG_ON(PAGE_SHIFT
!= SMMU_PAGE_SHIFT
);
1164 if (of_property_read_u32(dev
->of_node
, "nvidia,#asids", &asids
))
1167 bytes
= sizeof(*smmu
) + asids
* sizeof(*smmu
->as
);
1168 smmu
= devm_kzalloc(dev
, bytes
, GFP_KERNEL
);
1170 dev_err(dev
, "failed to allocate smmu_device\n");
1174 for (i
= 0; i
< ARRAY_SIZE(smmu
->regs
); i
++) {
1175 struct resource
*res
;
1177 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
1180 smmu
->regs
[i
] = devm_ioremap_resource(&pdev
->dev
, res
);
1181 if (IS_ERR(smmu
->regs
[i
]))
1182 return PTR_ERR(smmu
->regs
[i
]);
1185 err
= of_get_dma_window(dev
->of_node
, NULL
, 0, NULL
, &base
, &size
);
1189 if (size
& SMMU_PAGE_MASK
)
1192 size
>>= SMMU_PAGE_SHIFT
;
1196 smmu
->ahb
= of_parse_phandle(dev
->of_node
, "nvidia,ahb", 0);
1201 smmu
->num_as
= asids
;
1202 smmu
->iovmm_base
= base
;
1203 smmu
->page_count
= size
;
1205 smmu
->translation_enable_0
= ~0;
1206 smmu
->translation_enable_1
= ~0;
1207 smmu
->translation_enable_2
= ~0;
1208 smmu
->asid_security
= 0;
1210 for (i
= 0; i
< smmu
->num_as
; i
++) {
1211 struct smmu_as
*as
= &smmu
->as
[i
];
1215 as
->pdir_attr
= _PDIR_ATTR
;
1216 as
->pde_attr
= _PDE_ATTR
;
1217 as
->pte_attr
= _PTE_ATTR
;
1219 spin_lock_init(&as
->lock
);
1220 INIT_LIST_HEAD(&as
->client
);
1222 spin_lock_init(&smmu
->lock
);
1223 err
= smmu_setup_regs(smmu
);
1226 platform_set_drvdata(pdev
, smmu
);
1228 smmu
->avp_vector_page
= alloc_page(GFP_KERNEL
);
1229 if (!smmu
->avp_vector_page
)
1232 smmu_debugfs_create(smmu
);
1234 bus_set_iommu(&platform_bus_type
, &smmu_iommu_ops
);
1238 static int tegra_smmu_remove(struct platform_device
*pdev
)
1240 struct smmu_device
*smmu
= platform_get_drvdata(pdev
);
1243 smmu_debugfs_delete(smmu
);
1245 smmu_write(smmu
, SMMU_CONFIG_DISABLE
, SMMU_CONFIG
);
1246 for (i
= 0; i
< smmu
->num_as
; i
++)
1247 free_pdir(&smmu
->as
[i
]);
1248 __free_page(smmu
->avp_vector_page
);
1253 const struct dev_pm_ops tegra_smmu_pm_ops
= {
1254 .suspend
= tegra_smmu_suspend
,
1255 .resume
= tegra_smmu_resume
,
1259 static struct of_device_id tegra_smmu_of_match
[] = {
1260 { .compatible
= "nvidia,tegra30-smmu", },
1263 MODULE_DEVICE_TABLE(of
, tegra_smmu_of_match
);
1266 static struct platform_driver tegra_smmu_driver
= {
1267 .probe
= tegra_smmu_probe
,
1268 .remove
= tegra_smmu_remove
,
1270 .owner
= THIS_MODULE
,
1271 .name
= "tegra-smmu",
1272 .pm
= &tegra_smmu_pm_ops
,
1273 .of_match_table
= of_match_ptr(tegra_smmu_of_match
),
1277 static int tegra_smmu_init(void)
1279 return platform_driver_register(&tegra_smmu_driver
);
1282 static void __exit
tegra_smmu_exit(void)
1284 platform_driver_unregister(&tegra_smmu_driver
);
1287 subsys_initcall(tegra_smmu_init
);
1288 module_exit(tegra_smmu_exit
);
1290 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1291 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1292 MODULE_ALIAS("platform:tegra-smmu");
1293 MODULE_LICENSE("GPL v2");