2 * IOMMU API for SMMU in Tegra30
4 * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #define pr_fmt(fmt) "%s(): " fmt, __func__
22 #include <linux/err.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/spinlock.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/device.h>
31 #include <linux/sched.h>
32 #include <linux/iommu.h>
35 #include <linux/of_iommu.h>
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
39 #include <soc/tegra/ahb.h>
42 #include <asm/cacheflush.h>
67 #define HWG_AFI (1 << HWGRP_AFI)
68 #define HWG_AVPC (1 << HWGRP_AVPC)
69 #define HWG_DC (1 << HWGRP_DC)
70 #define HWG_DCB (1 << HWGRP_DCB)
71 #define HWG_EPP (1 << HWGRP_EPP)
72 #define HWG_G2 (1 << HWGRP_G2)
73 #define HWG_HC (1 << HWGRP_HC)
74 #define HWG_HDA (1 << HWGRP_HDA)
75 #define HWG_ISP (1 << HWGRP_ISP)
76 #define HWG_MPE (1 << HWGRP_MPE)
77 #define HWG_NV (1 << HWGRP_NV)
78 #define HWG_NV2 (1 << HWGRP_NV2)
79 #define HWG_PPCS (1 << HWGRP_PPCS)
80 #define HWG_SATA (1 << HWGRP_SATA)
81 #define HWG_VDE (1 << HWGRP_VDE)
82 #define HWG_VI (1 << HWGRP_VI)
84 /* bitmap of the page sizes currently supported */
85 #define SMMU_IOMMU_PGSIZES (SZ_4K)
87 #define SMMU_CONFIG 0x10
88 #define SMMU_CONFIG_DISABLE 0
89 #define SMMU_CONFIG_ENABLE 1
91 /* REVISIT: To support multiple MCs */
101 #define SMMU_CACHE_CONFIG_BASE 0x14
102 #define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
103 #define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
105 #define SMMU_CACHE_CONFIG_STATS_SHIFT 31
106 #define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
107 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30
108 #define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
110 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
111 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
112 #define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
114 #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
115 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
116 #define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
118 #define SMMU_PTB_ASID 0x1c
119 #define SMMU_PTB_ASID_CURRENT_SHIFT 0
121 #define SMMU_PTB_DATA 0x20
122 #define SMMU_PTB_DATA_RESET_VAL 0
123 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
124 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
125 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
127 #define SMMU_TLB_FLUSH 0x30
128 #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
129 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
130 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
131 #define SMMU_TLB_FLUSH_ASID_SHIFT 29
132 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
133 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
134 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
136 #define SMMU_PTC_FLUSH 0x34
137 #define SMMU_PTC_FLUSH_TYPE_ALL 0
138 #define SMMU_PTC_FLUSH_TYPE_ADR 1
139 #define SMMU_PTC_FLUSH_ADR_SHIFT 4
141 #define SMMU_ASID_SECURITY 0x38
143 #define SMMU_STATS_CACHE_COUNT_BASE 0x1f0
145 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
146 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
148 #define SMMU_TRANSLATION_ENABLE_0 0x228
149 #define SMMU_TRANSLATION_ENABLE_1 0x22c
150 #define SMMU_TRANSLATION_ENABLE_2 0x230
152 #define SMMU_AFI_ASID 0x238 /* PCIE */
153 #define SMMU_AVPC_ASID 0x23c /* AVP */
154 #define SMMU_DC_ASID 0x240 /* Display controller */
155 #define SMMU_DCB_ASID 0x244 /* Display controller B */
156 #define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
157 #define SMMU_G2_ASID 0x24c /* 2D engine */
158 #define SMMU_HC_ASID 0x250 /* Host1x */
159 #define SMMU_HDA_ASID 0x254 /* High-def audio */
160 #define SMMU_ISP_ASID 0x258 /* Image signal processor */
161 #define SMMU_MPE_ASID 0x264 /* MPEG encoder */
162 #define SMMU_NV_ASID 0x268 /* (3D) */
163 #define SMMU_NV2_ASID 0x26c /* (3D) */
164 #define SMMU_PPCS_ASID 0x270 /* AHB */
165 #define SMMU_SATA_ASID 0x278 /* SATA */
166 #define SMMU_VDE_ASID 0x27c /* Video decoder */
167 #define SMMU_VI_ASID 0x280 /* Video input */
169 #define SMMU_PDE_NEXT_SHIFT 28
171 #define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
172 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
173 #define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
174 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
175 #define SMMU_TLB_FLUSH_VA(iova, which) \
176 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
177 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
178 SMMU_TLB_FLUSH_VA_MATCH_##which)
179 #define SMMU_PTB_ASID_CUR(n) \
180 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
181 #define SMMU_TLB_FLUSH_ASID_MATCH_disable \
182 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
183 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
184 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
185 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
186 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
188 #define SMMU_PAGE_SHIFT 12
189 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
190 #define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
192 #define SMMU_PDIR_COUNT 1024
193 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
194 #define SMMU_PTBL_COUNT 1024
195 #define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
196 #define SMMU_PDIR_SHIFT 12
197 #define SMMU_PDE_SHIFT 12
198 #define SMMU_PTE_SHIFT 12
199 #define SMMU_PFN_MASK 0x000fffff
201 #define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
202 #define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
203 #define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22)
205 #define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
206 #define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
207 #define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
208 #define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
209 #define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
211 #define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
213 #define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
214 #define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
215 #define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
217 #define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
218 #define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
220 #define SMMU_MK_PDIR(page, attr) \
221 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
222 #define SMMU_MK_PDE(page, attr) \
223 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
224 #define SMMU_EX_PTBL_PAGE(pde) \
225 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
226 #define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
228 #define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
229 #define SMMU_ASID_DISABLE 0
230 #define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
232 #define NUM_SMMU_REG_BANKS 3
234 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
235 #define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
236 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
237 #define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
239 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
241 static const u32 smmu_hwgrp_asid_reg
[] = {
259 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
262 * Per client for address space
266 struct list_head list
;
275 struct smmu_device
*smmu
; /* back pointer to container */
277 spinlock_t lock
; /* for pagetable */
278 struct page
*pdir_page
;
279 unsigned long pdir_attr
;
280 unsigned long pde_attr
;
281 unsigned long pte_attr
;
282 unsigned int *pte_count
;
284 struct list_head client
;
285 spinlock_t client_lock
; /* for client list */
288 struct smmu_debugfs_info
{
289 struct smmu_device
*smmu
;
295 * Per SMMU device - IOMMU device
298 void __iomem
*regbase
; /* register offset base */
299 void __iomem
**regs
; /* register block start address array */
300 void __iomem
**rege
; /* register block end address array */
301 int nregs
; /* number of register blocks */
303 unsigned long iovmm_base
; /* remappable base address */
304 unsigned long page_count
; /* total remappable size */
308 struct page
*avp_vector_page
; /* dummy page shared by all AS's */
311 * Register image savers for suspend/resume
313 unsigned long translation_enable_0
;
314 unsigned long translation_enable_1
;
315 unsigned long translation_enable_2
;
316 unsigned long asid_security
;
318 struct dentry
*debugfs_root
;
319 struct smmu_debugfs_info
*debugfs_info
;
321 struct device_node
*ahb
;
324 struct smmu_as as
[0]; /* Run-time allocated array */
327 static struct smmu_device
*smmu_handle
; /* unique for a system */
330 * SMMU register accessors
332 static bool inline smmu_valid_reg(struct smmu_device
*smmu
,
337 for (i
= 0; i
< smmu
->nregs
; i
++) {
338 if (addr
< smmu
->regs
[i
])
340 if (addr
<= smmu
->rege
[i
])
347 static inline u32
smmu_read(struct smmu_device
*smmu
, size_t offs
)
349 void __iomem
*addr
= smmu
->regbase
+ offs
;
351 BUG_ON(!smmu_valid_reg(smmu
, addr
));
356 static inline void smmu_write(struct smmu_device
*smmu
, u32 val
, size_t offs
)
358 void __iomem
*addr
= smmu
->regbase
+ offs
;
360 BUG_ON(!smmu_valid_reg(smmu
, addr
));
365 #define VA_PAGE_TO_PA(va, page) \
366 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
368 #define FLUSH_CPU_DCACHE(va, page, size) \
370 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
371 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
372 outer_flush_range(_pa_, _pa_+(size_t)(size)); \
376 * Any interaction between any block on PPSB and a block on APB or AHB
377 * must have these read-back barriers to ensure the APB/AHB bus
378 * transaction is complete before initiating activity on the PPSB
381 #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
383 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
385 static int __smmu_client_set_hwgrp(struct smmu_client
*c
,
386 unsigned long map
, int on
)
389 struct smmu_as
*as
= c
->as
;
390 u32 val
, offs
, mask
= SMMU_ASID_ENABLE(as
->asid
);
391 struct smmu_device
*smmu
= as
->smmu
;
397 map
= smmu_client_hwgrp(c
);
399 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
400 offs
= HWGRP_ASID_REG(i
);
401 val
= smmu_read(smmu
, offs
);
403 if (WARN_ON(val
& mask
))
407 WARN_ON((val
& mask
) == mask
);
410 smmu_write(smmu
, val
, offs
);
412 FLUSH_SMMU_REGS(smmu
);
417 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
418 offs
= HWGRP_ASID_REG(i
);
419 val
= smmu_read(smmu
, offs
);
421 smmu_write(smmu
, val
, offs
);
426 static int smmu_client_set_hwgrp(struct smmu_client
*c
, u32 map
, int on
)
430 struct smmu_as
*as
= c
->as
;
431 struct smmu_device
*smmu
= as
->smmu
;
433 spin_lock_irqsave(&smmu
->lock
, flags
);
434 val
= __smmu_client_set_hwgrp(c
, map
, on
);
435 spin_unlock_irqrestore(&smmu
->lock
, flags
);
440 * Flush all TLB entries and all PTC entries
441 * Caller must lock smmu
443 static void smmu_flush_regs(struct smmu_device
*smmu
, int enable
)
447 smmu_write(smmu
, SMMU_PTC_FLUSH_TYPE_ALL
, SMMU_PTC_FLUSH
);
448 FLUSH_SMMU_REGS(smmu
);
449 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
450 SMMU_TLB_FLUSH_ASID_MATCH_disable
;
451 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
454 smmu_write(smmu
, SMMU_CONFIG_ENABLE
, SMMU_CONFIG
);
455 FLUSH_SMMU_REGS(smmu
);
458 static int smmu_setup_regs(struct smmu_device
*smmu
)
463 for (i
= 0; i
< smmu
->num_as
; i
++) {
464 struct smmu_as
*as
= &smmu
->as
[i
];
465 struct smmu_client
*c
;
467 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
468 val
= as
->pdir_page
?
469 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
) :
470 SMMU_PTB_DATA_RESET_VAL
;
471 smmu_write(smmu
, val
, SMMU_PTB_DATA
);
473 list_for_each_entry(c
, &as
->client
, list
)
474 __smmu_client_set_hwgrp(c
, c
->hwgrp
, 1);
477 smmu_write(smmu
, smmu
->translation_enable_0
, SMMU_TRANSLATION_ENABLE_0
);
478 smmu_write(smmu
, smmu
->translation_enable_1
, SMMU_TRANSLATION_ENABLE_1
);
479 smmu_write(smmu
, smmu
->translation_enable_2
, SMMU_TRANSLATION_ENABLE_2
);
480 smmu_write(smmu
, smmu
->asid_security
, SMMU_ASID_SECURITY
);
481 smmu_write(smmu
, SMMU_TLB_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_TLB
));
482 smmu_write(smmu
, SMMU_PTC_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_PTC
));
484 smmu_flush_regs(smmu
, 1);
486 return tegra_ahb_enable_smmu(smmu
->ahb
);
489 static void flush_ptc_and_tlb(struct smmu_device
*smmu
,
490 struct smmu_as
*as
, dma_addr_t iova
,
491 unsigned long *pte
, struct page
*page
, int is_pde
)
494 unsigned long tlb_flush_va
= is_pde
495 ? SMMU_TLB_FLUSH_VA(iova
, SECTION
)
496 : SMMU_TLB_FLUSH_VA(iova
, GROUP
);
498 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pte
, page
);
499 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
500 FLUSH_SMMU_REGS(smmu
);
502 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
503 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
504 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
505 FLUSH_SMMU_REGS(smmu
);
508 static void free_ptbl(struct smmu_as
*as
, dma_addr_t iova
)
510 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
511 unsigned long *pdir
= (unsigned long *)page_address(as
->pdir_page
);
513 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
514 dev_dbg(as
->smmu
->dev
, "pdn: %lx\n", pdn
);
516 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
517 __free_page(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
518 pdir
[pdn
] = _PDE_VACANT(pdn
);
519 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
520 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
525 static void free_pdir(struct smmu_as
*as
)
529 struct device
*dev
= as
->smmu
->dev
;
534 addr
= as
->smmu
->iovmm_base
;
535 count
= as
->smmu
->page_count
;
536 while (count
-- > 0) {
538 addr
+= SMMU_PAGE_SIZE
* SMMU_PTBL_COUNT
;
540 ClearPageReserved(as
->pdir_page
);
541 __free_page(as
->pdir_page
);
542 as
->pdir_page
= NULL
;
543 devm_kfree(dev
, as
->pte_count
);
544 as
->pte_count
= NULL
;
548 * Maps PTBL for given iova and returns the PTE address
549 * Caller must unmap the mapped PTBL returned in *ptbl_page_p
551 static unsigned long *locate_pte(struct smmu_as
*as
,
552 dma_addr_t iova
, bool allocate
,
553 struct page
**ptbl_page_p
,
554 unsigned int **count
)
556 unsigned long ptn
= SMMU_ADDR_TO_PFN(iova
);
557 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
558 unsigned long *pdir
= page_address(as
->pdir_page
);
561 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
562 /* Mapped entry table already exists */
563 *ptbl_page_p
= SMMU_EX_PTBL_PAGE(pdir
[pdn
]);
564 ptbl
= page_address(*ptbl_page_p
);
565 } else if (!allocate
) {
569 unsigned long addr
= SMMU_PDN_TO_ADDR(pdn
);
571 /* Vacant - allocate a new page table */
572 dev_dbg(as
->smmu
->dev
, "New PTBL pdn: %lx\n", pdn
);
574 *ptbl_page_p
= alloc_page(GFP_ATOMIC
);
576 dev_err(as
->smmu
->dev
,
577 "failed to allocate smmu_device page table\n");
580 SetPageReserved(*ptbl_page_p
);
581 ptbl
= (unsigned long *)page_address(*ptbl_page_p
);
582 for (pn
= 0; pn
< SMMU_PTBL_COUNT
;
583 pn
++, addr
+= SMMU_PAGE_SIZE
) {
584 ptbl
[pn
] = _PTE_VACANT(addr
);
586 FLUSH_CPU_DCACHE(ptbl
, *ptbl_page_p
, SMMU_PTBL_SIZE
);
587 pdir
[pdn
] = SMMU_MK_PDE(*ptbl_page_p
,
588 as
->pde_attr
| _PDE_NEXT
);
589 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
590 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
593 *count
= &as
->pte_count
[pdn
];
595 return &ptbl
[ptn
% SMMU_PTBL_COUNT
];
598 #ifdef CONFIG_SMMU_SIG_DEBUG
599 static void put_signature(struct smmu_as
*as
,
600 dma_addr_t iova
, unsigned long pfn
)
603 unsigned long *vaddr
;
605 page
= pfn_to_page(pfn
);
606 vaddr
= page_address(page
);
611 vaddr
[1] = pfn
<< PAGE_SHIFT
;
612 FLUSH_CPU_DCACHE(vaddr
, page
, sizeof(vaddr
[0]) * 2);
615 static inline void put_signature(struct smmu_as
*as
,
616 unsigned long addr
, unsigned long pfn
)
622 * Caller must not hold as->lock
624 static int alloc_pdir(struct smmu_as
*as
)
626 unsigned long *pdir
, flags
;
629 struct smmu_device
*smmu
= as
->smmu
;
634 * do the allocation, then grab as->lock
636 cnt
= devm_kzalloc(smmu
->dev
,
637 sizeof(cnt
[0]) * SMMU_PDIR_COUNT
,
639 page
= alloc_page(GFP_KERNEL
| __GFP_DMA
);
641 spin_lock_irqsave(&as
->lock
, flags
);
644 /* We raced, free the redundant */
650 dev_err(smmu
->dev
, "failed to allocate at %s\n", __func__
);
655 as
->pdir_page
= page
;
658 SetPageReserved(as
->pdir_page
);
659 pdir
= page_address(as
->pdir_page
);
661 for (pdn
= 0; pdn
< SMMU_PDIR_COUNT
; pdn
++)
662 pdir
[pdn
] = _PDE_VACANT(pdn
);
663 FLUSH_CPU_DCACHE(pdir
, as
->pdir_page
, SMMU_PDIR_SIZE
);
664 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pdir
, as
->pdir_page
);
665 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
666 FLUSH_SMMU_REGS(as
->smmu
);
667 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
668 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
669 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
670 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
671 FLUSH_SMMU_REGS(as
->smmu
);
673 spin_unlock_irqrestore(&as
->lock
, flags
);
678 spin_unlock_irqrestore(&as
->lock
, flags
);
680 devm_kfree(smmu
->dev
, cnt
);
686 static void __smmu_iommu_unmap(struct smmu_as
*as
, dma_addr_t iova
)
692 pte
= locate_pte(as
, iova
, false, &page
, &count
);
696 if (WARN_ON(*pte
== _PTE_VACANT(iova
)))
699 *pte
= _PTE_VACANT(iova
);
700 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
701 flush_ptc_and_tlb(as
->smmu
, as
, iova
, pte
, page
, 0);
706 static void __smmu_iommu_map_pfn(struct smmu_as
*as
, dma_addr_t iova
,
709 struct smmu_device
*smmu
= as
->smmu
;
714 pte
= locate_pte(as
, iova
, true, &page
, &count
);
718 if (*pte
== _PTE_VACANT(iova
))
720 *pte
= SMMU_PFN_TO_PTE(pfn
, as
->pte_attr
);
721 if (unlikely((*pte
== _PTE_VACANT(iova
))))
723 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
724 flush_ptc_and_tlb(smmu
, as
, iova
, pte
, page
, 0);
725 put_signature(as
, iova
, pfn
);
728 static int smmu_iommu_map(struct iommu_domain
*domain
, unsigned long iova
,
729 phys_addr_t pa
, size_t bytes
, int prot
)
731 struct smmu_as
*as
= domain
->priv
;
732 unsigned long pfn
= __phys_to_pfn(pa
);
735 dev_dbg(as
->smmu
->dev
, "[%d] %08lx:%pa\n", as
->asid
, iova
, &pa
);
740 spin_lock_irqsave(&as
->lock
, flags
);
741 __smmu_iommu_map_pfn(as
, iova
, pfn
);
742 spin_unlock_irqrestore(&as
->lock
, flags
);
746 static size_t smmu_iommu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
749 struct smmu_as
*as
= domain
->priv
;
752 dev_dbg(as
->smmu
->dev
, "[%d] %08lx\n", as
->asid
, iova
);
754 spin_lock_irqsave(&as
->lock
, flags
);
755 __smmu_iommu_unmap(as
, iova
);
756 spin_unlock_irqrestore(&as
->lock
, flags
);
757 return SMMU_PAGE_SIZE
;
760 static phys_addr_t
smmu_iommu_iova_to_phys(struct iommu_domain
*domain
,
763 struct smmu_as
*as
= domain
->priv
;
770 spin_lock_irqsave(&as
->lock
, flags
);
772 pte
= locate_pte(as
, iova
, true, &page
, &count
);
773 pfn
= *pte
& SMMU_PFN_MASK
;
774 WARN_ON(!pfn_valid(pfn
));
775 dev_dbg(as
->smmu
->dev
,
776 "iova:%08llx pfn:%08lx asid:%d\n", (unsigned long long)iova
,
779 spin_unlock_irqrestore(&as
->lock
, flags
);
780 return PFN_PHYS(pfn
);
783 static int smmu_iommu_domain_has_cap(struct iommu_domain
*domain
,
789 static int smmu_iommu_attach_dev(struct iommu_domain
*domain
,
792 struct smmu_as
*as
= domain
->priv
;
793 struct smmu_device
*smmu
= as
->smmu
;
794 struct smmu_client
*client
, *c
;
798 client
= devm_kzalloc(smmu
->dev
, sizeof(*c
), GFP_KERNEL
);
803 map
= (unsigned long)dev
->platform_data
;
807 err
= smmu_client_enable_hwgrp(client
, map
);
811 spin_lock(&as
->client_lock
);
812 list_for_each_entry(c
, &as
->client
, list
) {
815 "%s is already attached\n", dev_name(c
->dev
));
820 list_add(&client
->list
, &as
->client
);
821 spin_unlock(&as
->client_lock
);
824 * Reserve "page zero" for AVP vectors using a common dummy
827 if (map
& HWG_AVPC
) {
830 page
= as
->smmu
->avp_vector_page
;
831 __smmu_iommu_map_pfn(as
, 0, page_to_pfn(page
));
833 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
836 dev_dbg(smmu
->dev
, "%s is attached\n", dev_name(dev
));
840 smmu_client_disable_hwgrp(client
);
841 spin_unlock(&as
->client_lock
);
843 devm_kfree(smmu
->dev
, client
);
847 static void smmu_iommu_detach_dev(struct iommu_domain
*domain
,
850 struct smmu_as
*as
= domain
->priv
;
851 struct smmu_device
*smmu
= as
->smmu
;
852 struct smmu_client
*c
;
854 spin_lock(&as
->client_lock
);
856 list_for_each_entry(c
, &as
->client
, list
) {
858 smmu_client_disable_hwgrp(c
);
860 devm_kfree(smmu
->dev
, c
);
863 "%s is detached\n", dev_name(c
->dev
));
867 dev_err(smmu
->dev
, "Couldn't find %s\n", dev_name(dev
));
869 spin_unlock(&as
->client_lock
);
872 static int smmu_iommu_domain_init(struct iommu_domain
*domain
)
874 int i
, err
= -EAGAIN
;
877 struct smmu_device
*smmu
= smmu_handle
;
879 /* Look for a free AS with lock held */
880 for (i
= 0; i
< smmu
->num_as
; i
++) {
886 err
= alloc_pdir(as
);
893 if (i
== smmu
->num_as
)
894 dev_err(smmu
->dev
, "no free AS\n");
898 spin_lock_irqsave(&smmu
->lock
, flags
);
900 /* Update PDIR register */
901 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
903 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
), SMMU_PTB_DATA
);
904 FLUSH_SMMU_REGS(smmu
);
906 spin_unlock_irqrestore(&smmu
->lock
, flags
);
910 domain
->geometry
.aperture_start
= smmu
->iovmm_base
;
911 domain
->geometry
.aperture_end
= smmu
->iovmm_base
+
912 smmu
->page_count
* SMMU_PAGE_SIZE
- 1;
913 domain
->geometry
.force_aperture
= true;
915 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
920 static void smmu_iommu_domain_destroy(struct iommu_domain
*domain
)
922 struct smmu_as
*as
= domain
->priv
;
923 struct smmu_device
*smmu
= as
->smmu
;
926 spin_lock_irqsave(&as
->lock
, flags
);
929 spin_lock(&smmu
->lock
);
930 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
931 smmu_write(smmu
, SMMU_PTB_DATA_RESET_VAL
, SMMU_PTB_DATA
);
932 FLUSH_SMMU_REGS(smmu
);
933 spin_unlock(&smmu
->lock
);
938 if (!list_empty(&as
->client
)) {
939 struct smmu_client
*c
;
941 list_for_each_entry(c
, &as
->client
, list
)
942 smmu_iommu_detach_dev(domain
, c
->dev
);
945 spin_unlock_irqrestore(&as
->lock
, flags
);
948 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
951 static const struct iommu_ops smmu_iommu_ops
= {
952 .domain_init
= smmu_iommu_domain_init
,
953 .domain_destroy
= smmu_iommu_domain_destroy
,
954 .attach_dev
= smmu_iommu_attach_dev
,
955 .detach_dev
= smmu_iommu_detach_dev
,
956 .map
= smmu_iommu_map
,
957 .unmap
= smmu_iommu_unmap
,
958 .iova_to_phys
= smmu_iommu_iova_to_phys
,
959 .domain_has_cap
= smmu_iommu_domain_has_cap
,
960 .pgsize_bitmap
= SMMU_IOMMU_PGSIZES
,
963 /* Should be in the order of enum */
964 static const char * const smmu_debugfs_mc
[] = { "mc", };
965 static const char * const smmu_debugfs_cache
[] = { "tlb", "ptc", };
967 static ssize_t
smmu_debugfs_stats_write(struct file
*file
,
968 const char __user
*buffer
,
969 size_t count
, loff_t
*pos
)
971 struct smmu_debugfs_info
*info
;
972 struct smmu_device
*smmu
;
979 const char * const command
[] = {
984 char str
[] = "reset";
988 count
= min_t(size_t, count
, sizeof(str
));
989 if (copy_from_user(str
, buffer
, count
))
992 for (i
= 0; i
< ARRAY_SIZE(command
); i
++)
993 if (strncmp(str
, command
[i
],
994 strlen(command
[i
])) == 0)
997 if (i
== ARRAY_SIZE(command
))
1000 info
= file_inode(file
)->i_private
;
1003 offs
= SMMU_CACHE_CONFIG(info
->cache
);
1004 val
= smmu_read(smmu
, offs
);
1007 val
&= ~SMMU_CACHE_CONFIG_STATS_ENABLE
;
1008 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1009 smmu_write(smmu
, val
, offs
);
1012 val
|= SMMU_CACHE_CONFIG_STATS_ENABLE
;
1013 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1014 smmu_write(smmu
, val
, offs
);
1017 val
|= SMMU_CACHE_CONFIG_STATS_TEST
;
1018 smmu_write(smmu
, val
, offs
);
1019 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1020 smmu_write(smmu
, val
, offs
);
1027 dev_dbg(smmu
->dev
, "%s() %08x, %08x @%08x\n", __func__
,
1028 val
, smmu_read(smmu
, offs
), offs
);
1033 static int smmu_debugfs_stats_show(struct seq_file
*s
, void *v
)
1035 struct smmu_debugfs_info
*info
= s
->private;
1036 struct smmu_device
*smmu
= info
->smmu
;
1038 const char * const stats
[] = { "hit", "miss", };
1041 for (i
= 0; i
< ARRAY_SIZE(stats
); i
++) {
1045 offs
= SMMU_STATS_CACHE_COUNT(info
->mc
, info
->cache
, i
);
1046 val
= smmu_read(smmu
, offs
);
1047 seq_printf(s
, "%s:%08x ", stats
[i
], val
);
1049 dev_dbg(smmu
->dev
, "%s() %s %08x @%08x\n", __func__
,
1050 stats
[i
], val
, offs
);
1052 seq_printf(s
, "\n");
1056 static int smmu_debugfs_stats_open(struct inode
*inode
, struct file
*file
)
1058 return single_open(file
, smmu_debugfs_stats_show
, inode
->i_private
);
1061 static const struct file_operations smmu_debugfs_stats_fops
= {
1062 .open
= smmu_debugfs_stats_open
,
1064 .llseek
= seq_lseek
,
1065 .release
= single_release
,
1066 .write
= smmu_debugfs_stats_write
,
1069 static void smmu_debugfs_delete(struct smmu_device
*smmu
)
1071 debugfs_remove_recursive(smmu
->debugfs_root
);
1072 kfree(smmu
->debugfs_info
);
1075 static void smmu_debugfs_create(struct smmu_device
*smmu
)
1079 struct dentry
*root
;
1081 bytes
= ARRAY_SIZE(smmu_debugfs_mc
) * ARRAY_SIZE(smmu_debugfs_cache
) *
1082 sizeof(*smmu
->debugfs_info
);
1083 smmu
->debugfs_info
= kmalloc(bytes
, GFP_KERNEL
);
1084 if (!smmu
->debugfs_info
)
1087 root
= debugfs_create_dir(dev_name(smmu
->dev
), NULL
);
1090 smmu
->debugfs_root
= root
;
1092 for (i
= 0; i
< ARRAY_SIZE(smmu_debugfs_mc
); i
++) {
1096 mc
= debugfs_create_dir(smmu_debugfs_mc
[i
], root
);
1100 for (j
= 0; j
< ARRAY_SIZE(smmu_debugfs_cache
); j
++) {
1101 struct dentry
*cache
;
1102 struct smmu_debugfs_info
*info
;
1104 info
= smmu
->debugfs_info
;
1105 info
+= i
* ARRAY_SIZE(smmu_debugfs_mc
) + j
;
1110 cache
= debugfs_create_file(smmu_debugfs_cache
[j
],
1111 S_IWUGO
| S_IRUGO
, mc
,
1113 &smmu_debugfs_stats_fops
);
1122 smmu_debugfs_delete(smmu
);
1125 static int tegra_smmu_suspend(struct device
*dev
)
1127 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1129 smmu
->translation_enable_0
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_0
);
1130 smmu
->translation_enable_1
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_1
);
1131 smmu
->translation_enable_2
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_2
);
1132 smmu
->asid_security
= smmu_read(smmu
, SMMU_ASID_SECURITY
);
1136 static int tegra_smmu_resume(struct device
*dev
)
1138 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1139 unsigned long flags
;
1142 spin_lock_irqsave(&smmu
->lock
, flags
);
1143 err
= smmu_setup_regs(smmu
);
1144 spin_unlock_irqrestore(&smmu
->lock
, flags
);
1148 static int tegra_smmu_probe(struct platform_device
*pdev
)
1150 struct smmu_device
*smmu
;
1151 struct device
*dev
= &pdev
->dev
;
1152 int i
, asids
, err
= 0;
1153 dma_addr_t
uninitialized_var(base
);
1154 size_t bytes
, uninitialized_var(size
);
1159 BUILD_BUG_ON(PAGE_SHIFT
!= SMMU_PAGE_SHIFT
);
1161 if (of_property_read_u32(dev
->of_node
, "nvidia,#asids", &asids
))
1164 bytes
= sizeof(*smmu
) + asids
* sizeof(*smmu
->as
);
1165 smmu
= devm_kzalloc(dev
, bytes
, GFP_KERNEL
);
1167 dev_err(dev
, "failed to allocate smmu_device\n");
1171 smmu
->nregs
= pdev
->num_resources
;
1172 smmu
->regs
= devm_kzalloc(dev
, 2 * smmu
->nregs
* sizeof(*smmu
->regs
),
1174 smmu
->rege
= smmu
->regs
+ smmu
->nregs
;
1177 for (i
= 0; i
< smmu
->nregs
; i
++) {
1178 struct resource
*res
;
1180 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
1181 smmu
->regs
[i
] = devm_ioremap_resource(&pdev
->dev
, res
);
1182 if (IS_ERR(smmu
->regs
[i
]))
1183 return PTR_ERR(smmu
->regs
[i
]);
1184 smmu
->rege
[i
] = smmu
->regs
[i
] + resource_size(res
) - 1;
1186 /* Same as "mc" 1st regiter block start address */
1187 smmu
->regbase
= (void __iomem
*)((u32
)smmu
->regs
[0] & PAGE_MASK
);
1189 err
= of_get_dma_window(dev
->of_node
, NULL
, 0, NULL
, &base
, &size
);
1193 if (size
& SMMU_PAGE_MASK
)
1196 size
>>= SMMU_PAGE_SHIFT
;
1200 smmu
->ahb
= of_parse_phandle(dev
->of_node
, "nvidia,ahb", 0);
1205 smmu
->num_as
= asids
;
1206 smmu
->iovmm_base
= base
;
1207 smmu
->page_count
= size
;
1209 smmu
->translation_enable_0
= ~0;
1210 smmu
->translation_enable_1
= ~0;
1211 smmu
->translation_enable_2
= ~0;
1212 smmu
->asid_security
= 0;
1214 for (i
= 0; i
< smmu
->num_as
; i
++) {
1215 struct smmu_as
*as
= &smmu
->as
[i
];
1219 as
->pdir_attr
= _PDIR_ATTR
;
1220 as
->pde_attr
= _PDE_ATTR
;
1221 as
->pte_attr
= _PTE_ATTR
;
1223 spin_lock_init(&as
->lock
);
1224 spin_lock_init(&as
->client_lock
);
1225 INIT_LIST_HEAD(&as
->client
);
1227 spin_lock_init(&smmu
->lock
);
1228 err
= smmu_setup_regs(smmu
);
1231 platform_set_drvdata(pdev
, smmu
);
1233 smmu
->avp_vector_page
= alloc_page(GFP_KERNEL
);
1234 if (!smmu
->avp_vector_page
)
1237 smmu_debugfs_create(smmu
);
1239 bus_set_iommu(&platform_bus_type
, &smmu_iommu_ops
);
1243 static int tegra_smmu_remove(struct platform_device
*pdev
)
1245 struct smmu_device
*smmu
= platform_get_drvdata(pdev
);
1248 smmu_debugfs_delete(smmu
);
1250 smmu_write(smmu
, SMMU_CONFIG_DISABLE
, SMMU_CONFIG
);
1251 for (i
= 0; i
< smmu
->num_as
; i
++)
1252 free_pdir(&smmu
->as
[i
]);
1253 __free_page(smmu
->avp_vector_page
);
1258 static const struct dev_pm_ops tegra_smmu_pm_ops
= {
1259 .suspend
= tegra_smmu_suspend
,
1260 .resume
= tegra_smmu_resume
,
1263 static struct of_device_id tegra_smmu_of_match
[] = {
1264 { .compatible
= "nvidia,tegra30-smmu", },
1267 MODULE_DEVICE_TABLE(of
, tegra_smmu_of_match
);
1269 static struct platform_driver tegra_smmu_driver
= {
1270 .probe
= tegra_smmu_probe
,
1271 .remove
= tegra_smmu_remove
,
1273 .owner
= THIS_MODULE
,
1274 .name
= "tegra-smmu",
1275 .pm
= &tegra_smmu_pm_ops
,
1276 .of_match_table
= tegra_smmu_of_match
,
1280 static int tegra_smmu_init(void)
1282 return platform_driver_register(&tegra_smmu_driver
);
1285 static void __exit
tegra_smmu_exit(void)
1287 platform_driver_unregister(&tegra_smmu_driver
);
1290 subsys_initcall(tegra_smmu_init
);
1291 module_exit(tegra_smmu_exit
);
1293 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1294 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1295 MODULE_ALIAS("platform:tegra-smmu");
1296 MODULE_LICENSE("GPL v2");