2 * IOMMU API for SMMU in Tegra30
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #define pr_fmt(fmt) "%s(): " fmt, __func__
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
34 #include <linux/of_iommu.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/tegra-ahb.h>
40 #include <asm/cacheflush.h>
65 #define HWG_AFI (1 << HWGRP_AFI)
66 #define HWG_AVPC (1 << HWGRP_AVPC)
67 #define HWG_DC (1 << HWGRP_DC)
68 #define HWG_DCB (1 << HWGRP_DCB)
69 #define HWG_EPP (1 << HWGRP_EPP)
70 #define HWG_G2 (1 << HWGRP_G2)
71 #define HWG_HC (1 << HWGRP_HC)
72 #define HWG_HDA (1 << HWGRP_HDA)
73 #define HWG_ISP (1 << HWGRP_ISP)
74 #define HWG_MPE (1 << HWGRP_MPE)
75 #define HWG_NV (1 << HWGRP_NV)
76 #define HWG_NV2 (1 << HWGRP_NV2)
77 #define HWG_PPCS (1 << HWGRP_PPCS)
78 #define HWG_SATA (1 << HWGRP_SATA)
79 #define HWG_VDE (1 << HWGRP_VDE)
80 #define HWG_VI (1 << HWGRP_VI)
82 /* bitmap of the page sizes currently supported */
83 #define SMMU_IOMMU_PGSIZES (SZ_4K)
85 #define SMMU_CONFIG 0x10
86 #define SMMU_CONFIG_DISABLE 0
87 #define SMMU_CONFIG_ENABLE 1
89 /* REVISIT: To support multiple MCs */
99 #define SMMU_CACHE_CONFIG_BASE 0x14
100 #define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
101 #define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
103 #define SMMU_CACHE_CONFIG_STATS_SHIFT 31
104 #define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
105 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30
106 #define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
108 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
109 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
110 #define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
112 #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
113 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
114 #define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
116 #define SMMU_PTB_ASID 0x1c
117 #define SMMU_PTB_ASID_CURRENT_SHIFT 0
119 #define SMMU_PTB_DATA 0x20
120 #define SMMU_PTB_DATA_RESET_VAL 0
121 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
122 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
123 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
125 #define SMMU_TLB_FLUSH 0x30
126 #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
127 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
128 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
129 #define SMMU_TLB_FLUSH_ASID_SHIFT 29
130 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
131 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
132 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
134 #define SMMU_PTC_FLUSH 0x34
135 #define SMMU_PTC_FLUSH_TYPE_ALL 0
136 #define SMMU_PTC_FLUSH_TYPE_ADR 1
137 #define SMMU_PTC_FLUSH_ADR_SHIFT 4
139 #define SMMU_ASID_SECURITY 0x38
141 #define SMMU_STATS_CACHE_COUNT_BASE 0x1f0
143 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
144 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
146 #define SMMU_TRANSLATION_ENABLE_0 0x228
147 #define SMMU_TRANSLATION_ENABLE_1 0x22c
148 #define SMMU_TRANSLATION_ENABLE_2 0x230
150 #define SMMU_AFI_ASID 0x238 /* PCIE */
151 #define SMMU_AVPC_ASID 0x23c /* AVP */
152 #define SMMU_DC_ASID 0x240 /* Display controller */
153 #define SMMU_DCB_ASID 0x244 /* Display controller B */
154 #define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
155 #define SMMU_G2_ASID 0x24c /* 2D engine */
156 #define SMMU_HC_ASID 0x250 /* Host1x */
157 #define SMMU_HDA_ASID 0x254 /* High-def audio */
158 #define SMMU_ISP_ASID 0x258 /* Image signal processor */
159 #define SMMU_MPE_ASID 0x264 /* MPEG encoder */
160 #define SMMU_NV_ASID 0x268 /* (3D) */
161 #define SMMU_NV2_ASID 0x26c /* (3D) */
162 #define SMMU_PPCS_ASID 0x270 /* AHB */
163 #define SMMU_SATA_ASID 0x278 /* SATA */
164 #define SMMU_VDE_ASID 0x27c /* Video decoder */
165 #define SMMU_VI_ASID 0x280 /* Video input */
167 #define SMMU_PDE_NEXT_SHIFT 28
169 #define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
170 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
171 #define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
172 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
173 #define SMMU_TLB_FLUSH_VA(iova, which) \
174 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
175 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
176 SMMU_TLB_FLUSH_VA_MATCH_##which)
177 #define SMMU_PTB_ASID_CUR(n) \
178 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
179 #define SMMU_TLB_FLUSH_ASID_MATCH_disable \
180 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
181 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
182 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
183 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
184 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
186 #define SMMU_PAGE_SHIFT 12
187 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
188 #define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
190 #define SMMU_PDIR_COUNT 1024
191 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
192 #define SMMU_PTBL_COUNT 1024
193 #define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
194 #define SMMU_PDIR_SHIFT 12
195 #define SMMU_PDE_SHIFT 12
196 #define SMMU_PTE_SHIFT 12
197 #define SMMU_PFN_MASK 0x000fffff
199 #define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
200 #define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
201 #define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22)
203 #define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
204 #define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
205 #define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
206 #define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
207 #define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
209 #define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
211 #define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
212 #define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
213 #define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
215 #define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
216 #define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
218 #define SMMU_MK_PDIR(page, attr) \
219 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
220 #define SMMU_MK_PDE(page, attr) \
221 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
222 #define SMMU_EX_PTBL_PAGE(pde) \
223 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
224 #define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
226 #define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
227 #define SMMU_ASID_DISABLE 0
228 #define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
230 #define NUM_SMMU_REG_BANKS 3
232 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
233 #define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
234 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
235 #define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
237 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
239 static const u32 smmu_hwgrp_asid_reg
[] = {
257 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
260 * Per client for address space
264 struct list_head list
;
273 struct smmu_device
*smmu
; /* back pointer to container */
275 spinlock_t lock
; /* for pagetable */
276 struct page
*pdir_page
;
277 unsigned long pdir_attr
;
278 unsigned long pde_attr
;
279 unsigned long pte_attr
;
280 unsigned int *pte_count
;
282 struct list_head client
;
283 spinlock_t client_lock
; /* for client list */
286 struct smmu_debugfs_info
{
287 struct smmu_device
*smmu
;
293 * Per SMMU device - IOMMU device
296 void __iomem
*regs
[NUM_SMMU_REG_BANKS
];
297 unsigned long iovmm_base
; /* remappable base address */
298 unsigned long page_count
; /* total remappable size */
302 struct page
*avp_vector_page
; /* dummy page shared by all AS's */
305 * Register image savers for suspend/resume
307 unsigned long translation_enable_0
;
308 unsigned long translation_enable_1
;
309 unsigned long translation_enable_2
;
310 unsigned long asid_security
;
312 struct dentry
*debugfs_root
;
313 struct smmu_debugfs_info
*debugfs_info
;
315 struct device_node
*ahb
;
318 struct smmu_as as
[0]; /* Run-time allocated array */
321 static struct smmu_device
*smmu_handle
; /* unique for a system */
324 * SMMU register accessors
326 static inline u32
smmu_read(struct smmu_device
*smmu
, size_t offs
)
330 return readl(smmu
->regs
[0] + offs
- 0x10);
331 BUG_ON(offs
< 0x1f0);
333 return readl(smmu
->regs
[1] + offs
- 0x1f0);
334 BUG_ON(offs
< 0x228);
336 return readl(smmu
->regs
[2] + offs
- 0x228);
340 static inline void smmu_write(struct smmu_device
*smmu
, u32 val
, size_t offs
)
344 writel(val
, smmu
->regs
[0] + offs
- 0x10);
347 BUG_ON(offs
< 0x1f0);
349 writel(val
, smmu
->regs
[1] + offs
- 0x1f0);
352 BUG_ON(offs
< 0x228);
354 writel(val
, smmu
->regs
[2] + offs
- 0x228);
360 #define VA_PAGE_TO_PA(va, page) \
361 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
363 #define FLUSH_CPU_DCACHE(va, page, size) \
365 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
366 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
367 outer_flush_range(_pa_, _pa_+(size_t)(size)); \
371 * Any interaction between any block on PPSB and a block on APB or AHB
372 * must have these read-back barriers to ensure the APB/AHB bus
373 * transaction is complete before initiating activity on the PPSB
376 #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
378 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
380 static int __smmu_client_set_hwgrp(struct smmu_client
*c
,
381 unsigned long map
, int on
)
384 struct smmu_as
*as
= c
->as
;
385 u32 val
, offs
, mask
= SMMU_ASID_ENABLE(as
->asid
);
386 struct smmu_device
*smmu
= as
->smmu
;
392 map
= smmu_client_hwgrp(c
);
394 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
395 offs
= HWGRP_ASID_REG(i
);
396 val
= smmu_read(smmu
, offs
);
398 if (WARN_ON(val
& mask
))
402 WARN_ON((val
& mask
) == mask
);
405 smmu_write(smmu
, val
, offs
);
407 FLUSH_SMMU_REGS(smmu
);
412 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
413 offs
= HWGRP_ASID_REG(i
);
414 val
= smmu_read(smmu
, offs
);
416 smmu_write(smmu
, val
, offs
);
421 static int smmu_client_set_hwgrp(struct smmu_client
*c
, u32 map
, int on
)
425 struct smmu_as
*as
= c
->as
;
426 struct smmu_device
*smmu
= as
->smmu
;
428 spin_lock_irqsave(&smmu
->lock
, flags
);
429 val
= __smmu_client_set_hwgrp(c
, map
, on
);
430 spin_unlock_irqrestore(&smmu
->lock
, flags
);
435 * Flush all TLB entries and all PTC entries
436 * Caller must lock smmu
438 static void smmu_flush_regs(struct smmu_device
*smmu
, int enable
)
442 smmu_write(smmu
, SMMU_PTC_FLUSH_TYPE_ALL
, SMMU_PTC_FLUSH
);
443 FLUSH_SMMU_REGS(smmu
);
444 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
445 SMMU_TLB_FLUSH_ASID_MATCH_disable
;
446 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
449 smmu_write(smmu
, SMMU_CONFIG_ENABLE
, SMMU_CONFIG
);
450 FLUSH_SMMU_REGS(smmu
);
453 static int smmu_setup_regs(struct smmu_device
*smmu
)
458 for (i
= 0; i
< smmu
->num_as
; i
++) {
459 struct smmu_as
*as
= &smmu
->as
[i
];
460 struct smmu_client
*c
;
462 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
463 val
= as
->pdir_page
?
464 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
) :
465 SMMU_PTB_DATA_RESET_VAL
;
466 smmu_write(smmu
, val
, SMMU_PTB_DATA
);
468 list_for_each_entry(c
, &as
->client
, list
)
469 __smmu_client_set_hwgrp(c
, c
->hwgrp
, 1);
472 smmu_write(smmu
, smmu
->translation_enable_0
, SMMU_TRANSLATION_ENABLE_0
);
473 smmu_write(smmu
, smmu
->translation_enable_1
, SMMU_TRANSLATION_ENABLE_1
);
474 smmu_write(smmu
, smmu
->translation_enable_2
, SMMU_TRANSLATION_ENABLE_2
);
475 smmu_write(smmu
, smmu
->asid_security
, SMMU_ASID_SECURITY
);
476 smmu_write(smmu
, SMMU_TLB_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_TLB
));
477 smmu_write(smmu
, SMMU_PTC_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_PTC
));
479 smmu_flush_regs(smmu
, 1);
481 return tegra_ahb_enable_smmu(smmu
->ahb
);
484 static void flush_ptc_and_tlb(struct smmu_device
*smmu
,
485 struct smmu_as
*as
, dma_addr_t iova
,
486 unsigned long *pte
, struct page
*page
, int is_pde
)
489 unsigned long tlb_flush_va
= is_pde
490 ? SMMU_TLB_FLUSH_VA(iova
, SECTION
)
491 : SMMU_TLB_FLUSH_VA(iova
, GROUP
);
493 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pte
, page
);
494 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
495 FLUSH_SMMU_REGS(smmu
);
497 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
498 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
499 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
500 FLUSH_SMMU_REGS(smmu
);
503 static void free_ptbl(struct smmu_as
*as
, dma_addr_t iova
)
505 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
506 unsigned long *pdir
= (unsigned long *)page_address(as
->pdir_page
);
508 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
509 dev_dbg(as
->smmu
->dev
, "pdn: %lx\n", pdn
);
511 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
512 __free_page(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
513 pdir
[pdn
] = _PDE_VACANT(pdn
);
514 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
515 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
520 static void free_pdir(struct smmu_as
*as
)
524 struct device
*dev
= as
->smmu
->dev
;
529 addr
= as
->smmu
->iovmm_base
;
530 count
= as
->smmu
->page_count
;
531 while (count
-- > 0) {
533 addr
+= SMMU_PAGE_SIZE
* SMMU_PTBL_COUNT
;
535 ClearPageReserved(as
->pdir_page
);
536 __free_page(as
->pdir_page
);
537 as
->pdir_page
= NULL
;
538 devm_kfree(dev
, as
->pte_count
);
539 as
->pte_count
= NULL
;
543 * Maps PTBL for given iova and returns the PTE address
544 * Caller must unmap the mapped PTBL returned in *ptbl_page_p
546 static unsigned long *locate_pte(struct smmu_as
*as
,
547 dma_addr_t iova
, bool allocate
,
548 struct page
**ptbl_page_p
,
549 unsigned int **count
)
551 unsigned long ptn
= SMMU_ADDR_TO_PFN(iova
);
552 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
553 unsigned long *pdir
= page_address(as
->pdir_page
);
556 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
557 /* Mapped entry table already exists */
558 *ptbl_page_p
= SMMU_EX_PTBL_PAGE(pdir
[pdn
]);
559 ptbl
= page_address(*ptbl_page_p
);
560 } else if (!allocate
) {
564 unsigned long addr
= SMMU_PDN_TO_ADDR(pdn
);
566 /* Vacant - allocate a new page table */
567 dev_dbg(as
->smmu
->dev
, "New PTBL pdn: %lx\n", pdn
);
569 *ptbl_page_p
= alloc_page(GFP_ATOMIC
);
571 dev_err(as
->smmu
->dev
,
572 "failed to allocate smmu_device page table\n");
575 SetPageReserved(*ptbl_page_p
);
576 ptbl
= (unsigned long *)page_address(*ptbl_page_p
);
577 for (pn
= 0; pn
< SMMU_PTBL_COUNT
;
578 pn
++, addr
+= SMMU_PAGE_SIZE
) {
579 ptbl
[pn
] = _PTE_VACANT(addr
);
581 FLUSH_CPU_DCACHE(ptbl
, *ptbl_page_p
, SMMU_PTBL_SIZE
);
582 pdir
[pdn
] = SMMU_MK_PDE(*ptbl_page_p
,
583 as
->pde_attr
| _PDE_NEXT
);
584 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
585 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
588 *count
= &as
->pte_count
[pdn
];
590 return &ptbl
[ptn
% SMMU_PTBL_COUNT
];
593 #ifdef CONFIG_SMMU_SIG_DEBUG
594 static void put_signature(struct smmu_as
*as
,
595 dma_addr_t iova
, unsigned long pfn
)
598 unsigned long *vaddr
;
600 page
= pfn_to_page(pfn
);
601 vaddr
= page_address(page
);
606 vaddr
[1] = pfn
<< PAGE_SHIFT
;
607 FLUSH_CPU_DCACHE(vaddr
, page
, sizeof(vaddr
[0]) * 2);
610 static inline void put_signature(struct smmu_as
*as
,
611 unsigned long addr
, unsigned long pfn
)
617 * Caller must not hold as->lock
619 static int alloc_pdir(struct smmu_as
*as
)
621 unsigned long *pdir
, flags
;
624 struct smmu_device
*smmu
= as
->smmu
;
629 * do the allocation, then grab as->lock
631 cnt
= devm_kzalloc(smmu
->dev
,
632 sizeof(cnt
[0]) * SMMU_PDIR_COUNT
,
634 page
= alloc_page(GFP_KERNEL
| __GFP_DMA
);
636 spin_lock_irqsave(&as
->lock
, flags
);
639 /* We raced, free the redundant */
645 dev_err(smmu
->dev
, "failed to allocate at %s\n", __func__
);
650 as
->pdir_page
= page
;
653 SetPageReserved(as
->pdir_page
);
654 pdir
= page_address(as
->pdir_page
);
656 for (pdn
= 0; pdn
< SMMU_PDIR_COUNT
; pdn
++)
657 pdir
[pdn
] = _PDE_VACANT(pdn
);
658 FLUSH_CPU_DCACHE(pdir
, as
->pdir_page
, SMMU_PDIR_SIZE
);
659 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pdir
, as
->pdir_page
);
660 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
661 FLUSH_SMMU_REGS(as
->smmu
);
662 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
663 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
664 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
665 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
666 FLUSH_SMMU_REGS(as
->smmu
);
668 spin_unlock_irqrestore(&as
->lock
, flags
);
673 spin_unlock_irqrestore(&as
->lock
, flags
);
675 devm_kfree(smmu
->dev
, cnt
);
681 static void __smmu_iommu_unmap(struct smmu_as
*as
, dma_addr_t iova
)
687 pte
= locate_pte(as
, iova
, false, &page
, &count
);
691 if (WARN_ON(*pte
== _PTE_VACANT(iova
)))
694 *pte
= _PTE_VACANT(iova
);
695 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
696 flush_ptc_and_tlb(as
->smmu
, as
, iova
, pte
, page
, 0);
701 static void __smmu_iommu_map_pfn(struct smmu_as
*as
, dma_addr_t iova
,
704 struct smmu_device
*smmu
= as
->smmu
;
709 pte
= locate_pte(as
, iova
, true, &page
, &count
);
713 if (*pte
== _PTE_VACANT(iova
))
715 *pte
= SMMU_PFN_TO_PTE(pfn
, as
->pte_attr
);
716 if (unlikely((*pte
== _PTE_VACANT(iova
))))
718 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
719 flush_ptc_and_tlb(smmu
, as
, iova
, pte
, page
, 0);
720 put_signature(as
, iova
, pfn
);
723 static int smmu_iommu_map(struct iommu_domain
*domain
, unsigned long iova
,
724 phys_addr_t pa
, size_t bytes
, int prot
)
726 struct smmu_as
*as
= domain
->priv
;
727 unsigned long pfn
= __phys_to_pfn(pa
);
730 dev_dbg(as
->smmu
->dev
, "[%d] %08lx:%08x\n", as
->asid
, iova
, pa
);
735 spin_lock_irqsave(&as
->lock
, flags
);
736 __smmu_iommu_map_pfn(as
, iova
, pfn
);
737 spin_unlock_irqrestore(&as
->lock
, flags
);
741 static size_t smmu_iommu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
744 struct smmu_as
*as
= domain
->priv
;
747 dev_dbg(as
->smmu
->dev
, "[%d] %08lx\n", as
->asid
, iova
);
749 spin_lock_irqsave(&as
->lock
, flags
);
750 __smmu_iommu_unmap(as
, iova
);
751 spin_unlock_irqrestore(&as
->lock
, flags
);
752 return SMMU_PAGE_SIZE
;
755 static phys_addr_t
smmu_iommu_iova_to_phys(struct iommu_domain
*domain
,
758 struct smmu_as
*as
= domain
->priv
;
765 spin_lock_irqsave(&as
->lock
, flags
);
767 pte
= locate_pte(as
, iova
, true, &page
, &count
);
768 pfn
= *pte
& SMMU_PFN_MASK
;
769 WARN_ON(!pfn_valid(pfn
));
770 dev_dbg(as
->smmu
->dev
,
771 "iova:%08lx pfn:%08lx asid:%d\n", iova
, pfn
, as
->asid
);
773 spin_unlock_irqrestore(&as
->lock
, flags
);
774 return PFN_PHYS(pfn
);
777 static int smmu_iommu_domain_has_cap(struct iommu_domain
*domain
,
783 static int smmu_iommu_attach_dev(struct iommu_domain
*domain
,
786 struct smmu_as
*as
= domain
->priv
;
787 struct smmu_device
*smmu
= as
->smmu
;
788 struct smmu_client
*client
, *c
;
792 client
= devm_kzalloc(smmu
->dev
, sizeof(*c
), GFP_KERNEL
);
797 map
= (unsigned long)dev
->platform_data
;
801 err
= smmu_client_enable_hwgrp(client
, map
);
805 spin_lock(&as
->client_lock
);
806 list_for_each_entry(c
, &as
->client
, list
) {
809 "%s is already attached\n", dev_name(c
->dev
));
814 list_add(&client
->list
, &as
->client
);
815 spin_unlock(&as
->client_lock
);
818 * Reserve "page zero" for AVP vectors using a common dummy
821 if (map
& HWG_AVPC
) {
824 page
= as
->smmu
->avp_vector_page
;
825 __smmu_iommu_map_pfn(as
, 0, page_to_pfn(page
));
827 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
830 dev_dbg(smmu
->dev
, "%s is attached\n", dev_name(dev
));
834 smmu_client_disable_hwgrp(client
);
835 spin_unlock(&as
->client_lock
);
837 devm_kfree(smmu
->dev
, client
);
841 static void smmu_iommu_detach_dev(struct iommu_domain
*domain
,
844 struct smmu_as
*as
= domain
->priv
;
845 struct smmu_device
*smmu
= as
->smmu
;
846 struct smmu_client
*c
;
848 spin_lock(&as
->client_lock
);
850 list_for_each_entry(c
, &as
->client
, list
) {
852 smmu_client_disable_hwgrp(c
);
854 devm_kfree(smmu
->dev
, c
);
857 "%s is detached\n", dev_name(c
->dev
));
861 dev_err(smmu
->dev
, "Couldn't find %s\n", dev_name(dev
));
863 spin_unlock(&as
->client_lock
);
866 static int smmu_iommu_domain_init(struct iommu_domain
*domain
)
868 int i
, err
= -EAGAIN
;
871 struct smmu_device
*smmu
= smmu_handle
;
873 /* Look for a free AS with lock held */
874 for (i
= 0; i
< smmu
->num_as
; i
++) {
880 err
= alloc_pdir(as
);
887 if (i
== smmu
->num_as
)
888 dev_err(smmu
->dev
, "no free AS\n");
892 spin_lock_irqsave(&smmu
->lock
, flags
);
894 /* Update PDIR register */
895 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
897 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
), SMMU_PTB_DATA
);
898 FLUSH_SMMU_REGS(smmu
);
900 spin_unlock_irqrestore(&smmu
->lock
, flags
);
904 domain
->geometry
.aperture_start
= smmu
->iovmm_base
;
905 domain
->geometry
.aperture_end
= smmu
->iovmm_base
+
906 smmu
->page_count
* SMMU_PAGE_SIZE
- 1;
907 domain
->geometry
.force_aperture
= true;
909 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
914 static void smmu_iommu_domain_destroy(struct iommu_domain
*domain
)
916 struct smmu_as
*as
= domain
->priv
;
917 struct smmu_device
*smmu
= as
->smmu
;
920 spin_lock_irqsave(&as
->lock
, flags
);
923 spin_lock(&smmu
->lock
);
924 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
925 smmu_write(smmu
, SMMU_PTB_DATA_RESET_VAL
, SMMU_PTB_DATA
);
926 FLUSH_SMMU_REGS(smmu
);
927 spin_unlock(&smmu
->lock
);
932 if (!list_empty(&as
->client
)) {
933 struct smmu_client
*c
;
935 list_for_each_entry(c
, &as
->client
, list
)
936 smmu_iommu_detach_dev(domain
, c
->dev
);
939 spin_unlock_irqrestore(&as
->lock
, flags
);
942 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
945 static struct iommu_ops smmu_iommu_ops
= {
946 .domain_init
= smmu_iommu_domain_init
,
947 .domain_destroy
= smmu_iommu_domain_destroy
,
948 .attach_dev
= smmu_iommu_attach_dev
,
949 .detach_dev
= smmu_iommu_detach_dev
,
950 .map
= smmu_iommu_map
,
951 .unmap
= smmu_iommu_unmap
,
952 .iova_to_phys
= smmu_iommu_iova_to_phys
,
953 .domain_has_cap
= smmu_iommu_domain_has_cap
,
954 .pgsize_bitmap
= SMMU_IOMMU_PGSIZES
,
957 /* Should be in the order of enum */
958 static const char * const smmu_debugfs_mc
[] = { "mc", };
959 static const char * const smmu_debugfs_cache
[] = { "tlb", "ptc", };
961 static ssize_t
smmu_debugfs_stats_write(struct file
*file
,
962 const char __user
*buffer
,
963 size_t count
, loff_t
*pos
)
965 struct smmu_debugfs_info
*info
;
966 struct smmu_device
*smmu
;
974 const char * const command
[] = {
979 char str
[] = "reset";
983 count
= min_t(size_t, count
, sizeof(str
));
984 if (copy_from_user(str
, buffer
, count
))
987 for (i
= 0; i
< ARRAY_SIZE(command
); i
++)
988 if (strncmp(str
, command
[i
],
989 strlen(command
[i
])) == 0)
992 if (i
== ARRAY_SIZE(command
))
995 dent
= file
->f_dentry
;
996 info
= dent
->d_inode
->i_private
;
999 offs
= SMMU_CACHE_CONFIG(info
->cache
);
1000 val
= smmu_read(smmu
, offs
);
1003 val
&= ~SMMU_CACHE_CONFIG_STATS_ENABLE
;
1004 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1005 smmu_write(smmu
, val
, offs
);
1008 val
|= SMMU_CACHE_CONFIG_STATS_ENABLE
;
1009 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1010 smmu_write(smmu
, val
, offs
);
1013 val
|= SMMU_CACHE_CONFIG_STATS_TEST
;
1014 smmu_write(smmu
, val
, offs
);
1015 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1016 smmu_write(smmu
, val
, offs
);
1023 dev_dbg(smmu
->dev
, "%s() %08x, %08x @%08x\n", __func__
,
1024 val
, smmu_read(smmu
, offs
), offs
);
1029 static int smmu_debugfs_stats_show(struct seq_file
*s
, void *v
)
1031 struct smmu_debugfs_info
*info
;
1032 struct smmu_device
*smmu
;
1033 struct dentry
*dent
;
1035 const char * const stats
[] = { "hit", "miss", };
1037 dent
= d_find_alias(s
->private);
1038 info
= dent
->d_inode
->i_private
;
1041 for (i
= 0; i
< ARRAY_SIZE(stats
); i
++) {
1045 offs
= SMMU_STATS_CACHE_COUNT(info
->mc
, info
->cache
, i
);
1046 val
= smmu_read(smmu
, offs
);
1047 seq_printf(s
, "%s:%08x ", stats
[i
], val
);
1049 dev_dbg(smmu
->dev
, "%s() %s %08x @%08x\n", __func__
,
1050 stats
[i
], val
, offs
);
1052 seq_printf(s
, "\n");
1058 static int smmu_debugfs_stats_open(struct inode
*inode
, struct file
*file
)
1060 return single_open(file
, smmu_debugfs_stats_show
, inode
);
1063 static const struct file_operations smmu_debugfs_stats_fops
= {
1064 .open
= smmu_debugfs_stats_open
,
1066 .llseek
= seq_lseek
,
1067 .release
= single_release
,
1068 .write
= smmu_debugfs_stats_write
,
1071 static void smmu_debugfs_delete(struct smmu_device
*smmu
)
1073 debugfs_remove_recursive(smmu
->debugfs_root
);
1074 kfree(smmu
->debugfs_info
);
1077 static void smmu_debugfs_create(struct smmu_device
*smmu
)
1081 struct dentry
*root
;
1083 bytes
= ARRAY_SIZE(smmu_debugfs_mc
) * ARRAY_SIZE(smmu_debugfs_cache
) *
1084 sizeof(*smmu
->debugfs_info
);
1085 smmu
->debugfs_info
= kmalloc(bytes
, GFP_KERNEL
);
1086 if (!smmu
->debugfs_info
)
1089 root
= debugfs_create_dir(dev_name(smmu
->dev
), NULL
);
1092 smmu
->debugfs_root
= root
;
1094 for (i
= 0; i
< ARRAY_SIZE(smmu_debugfs_mc
); i
++) {
1098 mc
= debugfs_create_dir(smmu_debugfs_mc
[i
], root
);
1102 for (j
= 0; j
< ARRAY_SIZE(smmu_debugfs_cache
); j
++) {
1103 struct dentry
*cache
;
1104 struct smmu_debugfs_info
*info
;
1106 info
= smmu
->debugfs_info
;
1107 info
+= i
* ARRAY_SIZE(smmu_debugfs_mc
) + j
;
1112 cache
= debugfs_create_file(smmu_debugfs_cache
[j
],
1113 S_IWUGO
| S_IRUGO
, mc
,
1115 &smmu_debugfs_stats_fops
);
1124 smmu_debugfs_delete(smmu
);
1127 static int tegra_smmu_suspend(struct device
*dev
)
1129 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1131 smmu
->translation_enable_0
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_0
);
1132 smmu
->translation_enable_1
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_1
);
1133 smmu
->translation_enable_2
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_2
);
1134 smmu
->asid_security
= smmu_read(smmu
, SMMU_ASID_SECURITY
);
1138 static int tegra_smmu_resume(struct device
*dev
)
1140 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1141 unsigned long flags
;
1144 spin_lock_irqsave(&smmu
->lock
, flags
);
1145 err
= smmu_setup_regs(smmu
);
1146 spin_unlock_irqrestore(&smmu
->lock
, flags
);
1150 static int tegra_smmu_probe(struct platform_device
*pdev
)
1152 struct smmu_device
*smmu
;
1153 struct device
*dev
= &pdev
->dev
;
1154 int i
, asids
, err
= 0;
1155 dma_addr_t
uninitialized_var(base
);
1156 size_t bytes
, uninitialized_var(size
);
1161 BUILD_BUG_ON(PAGE_SHIFT
!= SMMU_PAGE_SHIFT
);
1163 if (of_property_read_u32(dev
->of_node
, "nvidia,#asids", &asids
))
1166 bytes
= sizeof(*smmu
) + asids
* sizeof(*smmu
->as
);
1167 smmu
= devm_kzalloc(dev
, bytes
, GFP_KERNEL
);
1169 dev_err(dev
, "failed to allocate smmu_device\n");
1173 for (i
= 0; i
< ARRAY_SIZE(smmu
->regs
); i
++) {
1174 struct resource
*res
;
1176 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
1179 smmu
->regs
[i
] = devm_request_and_ioremap(&pdev
->dev
, res
);
1184 err
= of_get_dma_window(dev
->of_node
, NULL
, 0, NULL
, &base
, &size
);
1188 if (size
& SMMU_PAGE_MASK
)
1191 size
>>= SMMU_PAGE_SHIFT
;
1195 smmu
->ahb
= of_parse_phandle(dev
->of_node
, "nvidia,ahb", 0);
1200 smmu
->num_as
= asids
;
1201 smmu
->iovmm_base
= base
;
1202 smmu
->page_count
= size
;
1204 smmu
->translation_enable_0
= ~0;
1205 smmu
->translation_enable_1
= ~0;
1206 smmu
->translation_enable_2
= ~0;
1207 smmu
->asid_security
= 0;
1209 for (i
= 0; i
< smmu
->num_as
; i
++) {
1210 struct smmu_as
*as
= &smmu
->as
[i
];
1214 as
->pdir_attr
= _PDIR_ATTR
;
1215 as
->pde_attr
= _PDE_ATTR
;
1216 as
->pte_attr
= _PTE_ATTR
;
1218 spin_lock_init(&as
->lock
);
1219 INIT_LIST_HEAD(&as
->client
);
1221 spin_lock_init(&smmu
->lock
);
1222 err
= smmu_setup_regs(smmu
);
1225 platform_set_drvdata(pdev
, smmu
);
1227 smmu
->avp_vector_page
= alloc_page(GFP_KERNEL
);
1228 if (!smmu
->avp_vector_page
)
1231 smmu_debugfs_create(smmu
);
1233 bus_set_iommu(&platform_bus_type
, &smmu_iommu_ops
);
1237 static int tegra_smmu_remove(struct platform_device
*pdev
)
1239 struct smmu_device
*smmu
= platform_get_drvdata(pdev
);
1242 smmu_debugfs_delete(smmu
);
1244 smmu_write(smmu
, SMMU_CONFIG_DISABLE
, SMMU_CONFIG
);
1245 for (i
= 0; i
< smmu
->num_as
; i
++)
1246 free_pdir(&smmu
->as
[i
]);
1247 __free_page(smmu
->avp_vector_page
);
1252 const struct dev_pm_ops tegra_smmu_pm_ops
= {
1253 .suspend
= tegra_smmu_suspend
,
1254 .resume
= tegra_smmu_resume
,
1258 static struct of_device_id tegra_smmu_of_match
[] __devinitdata
= {
1259 { .compatible
= "nvidia,tegra30-smmu", },
1262 MODULE_DEVICE_TABLE(of
, tegra_smmu_of_match
);
1265 static struct platform_driver tegra_smmu_driver
= {
1266 .probe
= tegra_smmu_probe
,
1267 .remove
= tegra_smmu_remove
,
1269 .owner
= THIS_MODULE
,
1270 .name
= "tegra-smmu",
1271 .pm
= &tegra_smmu_pm_ops
,
1272 .of_match_table
= of_match_ptr(tegra_smmu_of_match
),
1276 static int __devinit
tegra_smmu_init(void)
1278 return platform_driver_register(&tegra_smmu_driver
);
1281 static void __exit
tegra_smmu_exit(void)
1283 platform_driver_unregister(&tegra_smmu_driver
);
1286 subsys_initcall(tegra_smmu_init
);
1287 module_exit(tegra_smmu_exit
);
1289 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1290 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1291 MODULE_ALIAS("platform:tegra-smmu");
1292 MODULE_LICENSE("GPL v2");