drivers/irqchip/Kconfig

   1 menu "IRQ chip support"
   2
   3 config IRQCHIP
   4         def_bool y
   5         depends on OF_IRQ
   6
   7 config ARM_GIC
   8         bool
   9         select IRQ_DOMAIN
  10         select IRQ_DOMAIN_HIERARCHY
  11         select GENERIC_IRQ_MULTI_HANDLER
  12         select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  13
  14 config ARM_GIC_PM
  15         bool
  16         depends on PM
  17         select ARM_GIC
  18         select PM_CLK
  19
  20 config ARM_GIC_MAX_NR
  21         int
  22         default 2 if ARCH_REALVIEW
  23         default 1
  24
  25 config ARM_GIC_V2M
  26         bool
  27         depends on PCI
  28         select ARM_GIC
  29         select PCI_MSI
  30
  31 config GIC_NON_BANKED
  32         bool
  33
  34 config ARM_GIC_V3
  35         bool
  36         select IRQ_DOMAIN
  37         select GENERIC_IRQ_MULTI_HANDLER
  38         select IRQ_DOMAIN_HIERARCHY
  39         select PARTITION_PERCPU
  40         select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  41
  42 config ARM_GIC_V3_ITS
  43         bool
  44         select GENERIC_MSI_IRQ_DOMAIN
  45         default ARM_GIC_V3
  46
  47 config ARM_GIC_V3_ITS_PCI
  48         bool
  49         depends on ARM_GIC_V3_ITS
  50         depends on PCI
  51         depends on PCI_MSI
  52         default ARM_GIC_V3_ITS
  53
  54 config ARM_GIC_V3_ITS_FSL_MC
  55         bool
  56         depends on ARM_GIC_V3_ITS
  57         depends on FSL_MC_BUS
  58         default ARM_GIC_V3_ITS
  59
  60 config ARM_NVIC
  61         bool
  62         select IRQ_DOMAIN
  63         select IRQ_DOMAIN_HIERARCHY
  64         select GENERIC_IRQ_CHIP
  65
  66 config ARM_VIC
  67         bool
  68         select IRQ_DOMAIN
  69         select GENERIC_IRQ_MULTI_HANDLER
  70
  71 config ARM_VIC_NR
  72         int
  73         default 4 if ARCH_S5PV210
  74         default 2
  75         depends on ARM_VIC
  76         help
  77           The maximum number of VICs available in the system, for
  78           power management.
  79
  80 config ARMADA_370_XP_IRQ
  81         bool
  82         select GENERIC_IRQ_CHIP
  83         select PCI_MSI if PCI
  84         select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  85
  86 config ALPINE_MSI
  87         bool
  88         depends on PCI
  89         select PCI_MSI
  90         select GENERIC_IRQ_CHIP
  91
  92 config ATMEL_AIC_IRQ
  93         bool
  94         select GENERIC_IRQ_CHIP
  95         select IRQ_DOMAIN
  96         select GENERIC_IRQ_MULTI_HANDLER
  97         select SPARSE_IRQ
  98
  99 config ATMEL_AIC5_IRQ
 100         bool
 101         select GENERIC_IRQ_CHIP
 102         select IRQ_DOMAIN
 103         select GENERIC_IRQ_MULTI_HANDLER
 104         select SPARSE_IRQ
 105
 106 config I8259
 107         bool
 108         select IRQ_DOMAIN
 109
 110 config BCM6345_L1_IRQ
 111         bool
 112         select GENERIC_IRQ_CHIP
 113         select IRQ_DOMAIN
 114         select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 115
 116 config BCM7038_L1_IRQ
 117         bool
 118         select GENERIC_IRQ_CHIP
 119         select IRQ_DOMAIN
 120         select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 121
 122 config BCM7120_L2_IRQ
 123         bool
 124         select GENERIC_IRQ_CHIP
 125         select IRQ_DOMAIN
 126
 127 config BRCMSTB_L2_IRQ
 128         bool
 129         select GENERIC_IRQ_CHIP
 130         select IRQ_DOMAIN
 131
 132 config DAVINCI_AINTC
 133         bool
 134         select GENERIC_IRQ_CHIP
 135         select IRQ_DOMAIN
 136
 137 config DAVINCI_CP_INTC
 138         bool
 139         select GENERIC_IRQ_CHIP
 140         select IRQ_DOMAIN
 141
 142 config DW_APB_ICTL
 143         bool
 144         select GENERIC_IRQ_CHIP
 145         select IRQ_DOMAIN
 146
 147 config FARADAY_FTINTC010
 148         bool
 149         select IRQ_DOMAIN
 150         select GENERIC_IRQ_MULTI_HANDLER
 151         select SPARSE_IRQ
 152
 153 config HISILICON_IRQ_MBIGEN
 154         bool
 155         select ARM_GIC_V3
 156         select ARM_GIC_V3_ITS
 157
 158 config IMGPDC_IRQ
 159         bool
 160         select GENERIC_IRQ_CHIP
 161         select IRQ_DOMAIN
 162
 163 config IXP4XX_IRQ
 164         bool
 165         select IRQ_DOMAIN
 166         select GENERIC_IRQ_MULTI_HANDLER
 167         select SPARSE_IRQ
 168
 169 config MADERA_IRQ
 170         tristate
 171
 172 config IRQ_MIPS_CPU
 173         bool
 174         select GENERIC_IRQ_CHIP
 175         select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
 176         select IRQ_DOMAIN
 177         select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
 178         select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 179
 180 config CLPS711X_IRQCHIP
 181         bool
 182         depends on ARCH_CLPS711X
 183         select IRQ_DOMAIN
 184         select GENERIC_IRQ_MULTI_HANDLER
 185         select SPARSE_IRQ
 186         default y
 187
 188 config OMPIC
 189         bool
 190
 191 config OR1K_PIC
 192         bool
 193         select IRQ_DOMAIN
 194
 195 config OMAP_IRQCHIP
 196         bool
 197         select GENERIC_IRQ_CHIP
 198         select IRQ_DOMAIN
 199
 200 config ORION_IRQCHIP
 201         bool
 202         select IRQ_DOMAIN
 203         select GENERIC_IRQ_MULTI_HANDLER
 204
 205 config PIC32_EVIC
 206         bool
 207         select GENERIC_IRQ_CHIP
 208         select IRQ_DOMAIN
 209
 210 config JCORE_AIC
 211         bool "J-Core integrated AIC" if COMPILE_TEST
 212         depends on OF
 213         select IRQ_DOMAIN
 214         help
 215           Support for the J-Core integrated AIC.
 216
 217 config RDA_INTC
 218         bool
 219         select IRQ_DOMAIN
 220
 221 config RENESAS_INTC_IRQPIN
 222         bool
 223         select IRQ_DOMAIN
 224
 225 config RENESAS_IRQC
 226         bool
 227         select GENERIC_IRQ_CHIP
 228         select IRQ_DOMAIN
 229
 230 config ST_IRQCHIP
 231         bool
 232         select REGMAP
 233         select MFD_SYSCON
 234         help
 235           Enables SysCfg Controlled IRQs on STi based platforms.
 236
 237 config TANGO_IRQ
 238         bool
 239         select IRQ_DOMAIN
 240         select GENERIC_IRQ_CHIP
 241
 242 config TB10X_IRQC
 243         bool
 244         select IRQ_DOMAIN
 245         select GENERIC_IRQ_CHIP
 246
 247 config TS4800_IRQ
 248         tristate "TS-4800 IRQ controller"
 249         select IRQ_DOMAIN
 250         depends on HAS_IOMEM
 251         depends on SOC_IMX51 || COMPILE_TEST
 252         help
 253           Support for the TS-4800 FPGA IRQ controller
 254
 255 config VERSATILE_FPGA_IRQ
 256         bool
 257         select IRQ_DOMAIN
 258
 259 config VERSATILE_FPGA_IRQ_NR
 260        int
 261        default 4
 262        depends on VERSATILE_FPGA_IRQ
 263
 264 config XTENSA_MX
 265         bool
 266         select IRQ_DOMAIN
 267         select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 268
 269 config XILINX_INTC
 270         bool
 271         select IRQ_DOMAIN
 272
 273 config IRQ_CROSSBAR
 274         bool
 275         help
 276           Support for a CROSSBAR ip that precedes the main interrupt controller.
 277           The primary irqchip invokes the crossbar's callback which inturn allocates
 278           a free irq and configures the IP. Thus the peripheral interrupts are
 279           routed to one of the free irqchip interrupt lines.
 280
 281 config KEYSTONE_IRQ
 282         tristate "Keystone 2 IRQ controller IP"
 283         depends on ARCH_KEYSTONE
 284         help
 285                 Support for Texas Instruments Keystone 2 IRQ controller IP which
 286                 is part of the Keystone 2 IPC mechanism
 287
 288 config MIPS_GIC
 289         bool
 290         select GENERIC_IRQ_IPI
 291         select IRQ_DOMAIN_HIERARCHY
 292         select MIPS_CM
 293
 294 config INGENIC_IRQ
 295         bool
 296         depends on MACH_INGENIC
 297         default y
 298
 299 config RENESAS_H8300H_INTC
 300         bool
 301         select IRQ_DOMAIN
 302
 303 config RENESAS_H8S_INTC
 304         bool
 305         select IRQ_DOMAIN
 306
 307 config IMX_GPCV2
 308         bool
 309         select IRQ_DOMAIN
 310         help
 311           Enables the wakeup IRQs for IMX platforms with GPCv2 block
 312
 313 config IRQ_MXS
 314         def_bool y if MACH_ASM9260 || ARCH_MXS
 315         select IRQ_DOMAIN
 316         select STMP_DEVICE
 317
 318 config MSCC_OCELOT_IRQ
 319         bool
 320         select IRQ_DOMAIN
 321         select GENERIC_IRQ_CHIP
 322
 323 config MVEBU_GICP
 324         bool
 325
 326 config MVEBU_ICU
 327         bool
 328
 329 config MVEBU_ODMI
 330         bool
 331         select GENERIC_MSI_IRQ_DOMAIN
 332
 333 config MVEBU_PIC
 334         bool
 335
 336 config MVEBU_SEI
 337         bool
 338
 339 config LS_SCFG_MSI
 340         def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
 341         depends on PCI && PCI_MSI
 342
 343 config PARTITION_PERCPU
 344         bool
 345
 346 config EZNPS_GIC
 347         bool "NPS400 Global Interrupt Manager (GIM)"
 348         depends on ARC || (COMPILE_TEST && !64BIT)
 349         select IRQ_DOMAIN
 350         help
 351           Support the EZchip NPS400 global interrupt controller
 352
 353 config STM32_EXTI
 354         bool
 355         select IRQ_DOMAIN
 356         select GENERIC_IRQ_CHIP
 357
 358 config QCOM_IRQ_COMBINER
 359         bool "QCOM IRQ combiner support"
 360         depends on ARCH_QCOM && ACPI
 361         select IRQ_DOMAIN
 362         select IRQ_DOMAIN_HIERARCHY
 363         help
 364           Say yes here to add support for the IRQ combiner devices embedded
 365           in Qualcomm Technologies chips.
 366
 367 config IRQ_UNIPHIER_AIDET
 368         bool "UniPhier AIDET support" if COMPILE_TEST
 369         depends on ARCH_UNIPHIER || COMPILE_TEST
 370         default ARCH_UNIPHIER
 371         select IRQ_DOMAIN_HIERARCHY
 372         help
 373           Support for the UniPhier AIDET (ARM Interrupt Detector).
 374
 375 config MESON_IRQ_GPIO
 376        bool "Meson GPIO Interrupt Multiplexer"
 377        depends on ARCH_MESON
 378        select IRQ_DOMAIN
 379        select IRQ_DOMAIN_HIERARCHY
 380        help
 381          Support Meson SoC Family GPIO Interrupt Multiplexer
 382
 383 config GOLDFISH_PIC
 384        bool "Goldfish programmable interrupt controller"
 385        depends on MIPS && (GOLDFISH || COMPILE_TEST)
 386        select IRQ_DOMAIN
 387        help
 388          Say yes here to enable Goldfish interrupt controller driver used
 389          for Goldfish based virtual platforms.
 390
 391 config QCOM_PDC
 392         bool "QCOM PDC"
 393         depends on ARCH_QCOM
 394         select IRQ_DOMAIN
 395         select IRQ_DOMAIN_HIERARCHY
 396         help
 397           Power Domain Controller driver to manage and configure wakeup
 398           IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
 399
 400 config CSKY_MPINTC
 401         bool "C-SKY Multi Processor Interrupt Controller"
 402         depends on CSKY
 403         help
 404           Say yes here to enable C-SKY SMP interrupt controller driver used
 405           for C-SKY SMP system.
 406           In fact it's not mmio map in hw and it use ld/st to visit the
 407           controller's register inside CPU.
 408
 409 config CSKY_APB_INTC
 410         bool "C-SKY APB Interrupt Controller"
 411         depends on CSKY
 412         help
 413           Say yes here to enable C-SKY APB interrupt controller driver used
 414           by C-SKY single core SOC system. It use mmio map apb-bus to visit
 415           the controller's register.
 416
 417 config IMX_IRQSTEER
 418         bool "i.MX IRQSTEER support"
 419         depends on ARCH_MXC || COMPILE_TEST
 420         default ARCH_MXC
 421         select IRQ_DOMAIN
 422         help
 423           Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
 424
 425 config LS1X_IRQ
 426         bool "Loongson-1 Interrupt Controller"
 427         depends on MACH_LOONGSON32
 428         default y
 429         select IRQ_DOMAIN
 430         select GENERIC_IRQ_CHIP
 431         help
 432           Support for the Loongson-1 platform Interrupt Controller.
 433
 434 endmenu
 435
 436 config SIFIVE_PLIC
 437         bool "SiFive Platform-Level Interrupt Controller"
 438         depends on RISCV
 439         help
 440            This enables support for the PLIC chip found in SiFive (and
 441            potentially other) RISC-V systems.  The PLIC controls devices
 442            interrupts and connects them to each core's local interrupt
 443            controller.  Aside from timer and software interrupts, all other
 444            interrupt sources are subordinate to the PLIC.
 445
 446            If you don't know what to do here, say Y.