drivers/irqchip/irq-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370 and Armada XP SoC IRQ handling
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_pci.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/slab.h>
  27 #include <linux/msi.h>
  28 #include <asm/mach/arch.h>
  29 #include <asm/exception.h>
  30 #include <asm/smp_plat.h>
  31 #include <asm/mach/irq.h>
  32
  33 #include "irqchip.h"
  34
  35 /* Interrupt Controller Registers Map */
  36 #define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
  37 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
  38
  39 #define ARMADA_370_XP_INT_CONTROL               (0x00)
  40 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
  41 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
  42 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)       (0x100 + irq*4)
  43
  44 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
  45
  46 #define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
  47 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
  48 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
  49
  50 #define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
  51
  52 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ        (5)
  53
  54 #define IPI_DOORBELL_START                      (0)
  55 #define IPI_DOORBELL_END                        (8)
  56 #define IPI_DOORBELL_MASK                       0xFF
  57 #define PCI_MSI_DOORBELL_START                  (16)
  58 #define PCI_MSI_DOORBELL_NR                     (16)
  59 #define PCI_MSI_DOORBELL_END                    (32)
  60 #define PCI_MSI_DOORBELL_MASK                   0xFFFF0000
  61
  62 static void __iomem *per_cpu_int_base;
  63 static void __iomem *main_int_base;
  64 static struct irq_domain *armada_370_xp_mpic_domain;
  65 #ifdef CONFIG_PCI_MSI
  66 static struct irq_domain *armada_370_xp_msi_domain;
  67 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
  68 static DEFINE_MUTEX(msi_used_lock);
  69 static phys_addr_t msi_doorbell_addr;
  70 #endif
  71
  72 /*
  73  * In SMP mode:
  74  * For shared global interrupts, mask/unmask global enable bit
  75  * For CPU interrupts, mask/unmask the calling CPU's bit
  76  */
  77 static void armada_370_xp_irq_mask(struct irq_data *d)
  78 {
  79         irq_hw_number_t hwirq = irqd_to_hwirq(d);
  80
  81         if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
  82                 writel(hwirq, main_int_base +
  83                                 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
  84         else
  85                 writel(hwirq, per_cpu_int_base +
  86                                 ARMADA_370_XP_INT_SET_MASK_OFFS);
  87 }
  88
  89 static void armada_370_xp_irq_unmask(struct irq_data *d)
  90 {
  91         irq_hw_number_t hwirq = irqd_to_hwirq(d);
  92
  93         if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
  94                 writel(hwirq, main_int_base +
  95                                 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
  96         else
  97                 writel(hwirq, per_cpu_int_base +
  98                                 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
  99 }
 100
 101 #ifdef CONFIG_PCI_MSI
 102
 103 static int armada_370_xp_alloc_msi(void)
 104 {
 105         int hwirq;
 106
 107         mutex_lock(&msi_used_lock);
 108         hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
 109         if (hwirq >= PCI_MSI_DOORBELL_NR)
 110                 hwirq = -ENOSPC;
 111         else
 112                 set_bit(hwirq, msi_used);
 113         mutex_unlock(&msi_used_lock);
 114
 115         return hwirq;
 116 }
 117
 118 static void armada_370_xp_free_msi(int hwirq)
 119 {
 120         mutex_lock(&msi_used_lock);
 121         if (!test_bit(hwirq, msi_used))
 122                 pr_err("trying to free unused MSI#%d\n", hwirq);
 123         else
 124                 clear_bit(hwirq, msi_used);
 125         mutex_unlock(&msi_used_lock);
 126 }
 127
 128 static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
 129                                        struct pci_dev *pdev,
 130                                        struct msi_desc *desc)
 131 {
 132         struct msi_msg msg;
 133         irq_hw_number_t hwirq;
 134         int virq;
 135
 136         hwirq = armada_370_xp_alloc_msi();
 137         if (hwirq < 0)
 138                 return hwirq;
 139
 140         virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
 141         if (!virq) {
 142                 armada_370_xp_free_msi(hwirq);
 143                 return -EINVAL;
 144         }
 145
 146         irq_set_msi_desc(virq, desc);
 147
 148         msg.address_lo = msi_doorbell_addr;
 149         msg.address_hi = 0;
 150         msg.data = 0xf00 | (hwirq + 16);
 151
 152         write_msi_msg(virq, &msg);
 153         return 0;
 154 }
 155
 156 static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
 157                                            unsigned int irq)
 158 {
 159         struct irq_data *d = irq_get_irq_data(irq);
 160         irq_dispose_mapping(irq);
 161         armada_370_xp_free_msi(d->hwirq);
 162 }
 163
 164 static struct irq_chip armada_370_xp_msi_irq_chip = {
 165         .name = "armada_370_xp_msi_irq",
 166         .irq_enable = unmask_msi_irq,
 167         .irq_disable = mask_msi_irq,
 168         .irq_mask = mask_msi_irq,
 169         .irq_unmask = unmask_msi_irq,
 170 };
 171
 172 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
 173                                  irq_hw_number_t hw)
 174 {
 175         irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
 176                                  handle_simple_irq);
 177         set_irq_flags(virq, IRQF_VALID);
 178
 179         return 0;
 180 }
 181
 182 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
 183         .map = armada_370_xp_msi_map,
 184 };
 185
 186 static int armada_370_xp_msi_init(struct device_node *node,
 187                                   phys_addr_t main_int_phys_base)
 188 {
 189         struct msi_chip *msi_chip;
 190         u32 reg;
 191         int ret;
 192
 193         msi_doorbell_addr = main_int_phys_base +
 194                 ARMADA_370_XP_SW_TRIG_INT_OFFS;
 195
 196         msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
 197         if (!msi_chip)
 198                 return -ENOMEM;
 199
 200         msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
 201         msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
 202         msi_chip->of_node = node;
 203
 204         armada_370_xp_msi_domain =
 205                 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
 206                                       &armada_370_xp_msi_irq_ops,
 207                                       NULL);
 208         if (!armada_370_xp_msi_domain) {
 209                 kfree(msi_chip);
 210                 return -ENOMEM;
 211         }
 212
 213         ret = of_pci_msi_chip_add(msi_chip);
 214         if (ret < 0) {
 215                 irq_domain_remove(armada_370_xp_msi_domain);
 216                 kfree(msi_chip);
 217                 return ret;
 218         }
 219
 220         reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
 221                 | PCI_MSI_DOORBELL_MASK;
 222
 223         writel(reg, per_cpu_int_base +
 224                ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 225
 226         /* Unmask IPI interrupt */
 227         writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 228
 229         return 0;
 230 }
 231 #else
 232 static inline int armada_370_xp_msi_init(struct device_node *node,
 233                                          phys_addr_t main_int_phys_base)
 234 {
 235         return 0;
 236 }
 237 #endif
 238
 239 #ifdef CONFIG_SMP
 240 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 241
 242 static int armada_xp_set_affinity(struct irq_data *d,
 243                                   const struct cpumask *mask_val, bool force)
 244 {
 245         unsigned long reg;
 246         unsigned long new_mask = 0;
 247         unsigned long online_mask = 0;
 248         unsigned long count = 0;
 249         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 250         int cpu;
 251
 252         for_each_cpu(cpu, mask_val) {
 253                 new_mask |= 1 << cpu_logical_map(cpu);
 254                 count++;
 255         }
 256
 257         /*
 258          * Forbid mutlicore interrupt affinity
 259          * This is required since the MPIC HW doesn't limit
 260          * several CPUs from acknowledging the same interrupt.
 261          */
 262         if (count > 1)
 263                 return -EINVAL;
 264
 265         for_each_cpu(cpu, cpu_online_mask)
 266                 online_mask |= 1 << cpu_logical_map(cpu);
 267
 268         raw_spin_lock(&irq_controller_lock);
 269
 270         reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 271         reg = (reg & (~online_mask)) | new_mask;
 272         writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 273
 274         raw_spin_unlock(&irq_controller_lock);
 275
 276         return 0;
 277 }
 278 #endif
 279
 280 static struct irq_chip armada_370_xp_irq_chip = {
 281         .name           = "armada_370_xp_irq",
 282         .irq_mask       = armada_370_xp_irq_mask,
 283         .irq_mask_ack   = armada_370_xp_irq_mask,
 284         .irq_unmask     = armada_370_xp_irq_unmask,
 285 #ifdef CONFIG_SMP
 286         .irq_set_affinity = armada_xp_set_affinity,
 287 #endif
 288 };
 289
 290 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 291                                       unsigned int virq, irq_hw_number_t hw)
 292 {
 293         armada_370_xp_irq_mask(irq_get_irq_data(virq));
 294         if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
 295                 writel(hw, per_cpu_int_base +
 296                         ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 297         else
 298                 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 299         irq_set_status_flags(virq, IRQ_LEVEL);
 300
 301         if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
 302                 irq_set_percpu_devid(virq);
 303                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 304                                         handle_percpu_devid_irq);
 305
 306         } else {
 307                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 308                                         handle_level_irq);
 309         }
 310         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
 311
 312         return 0;
 313 }
 314
 315 #ifdef CONFIG_SMP
 316 void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
 317 {
 318         int cpu;
 319         unsigned long map = 0;
 320
 321         /* Convert our logical CPU mask into a physical one. */
 322         for_each_cpu(cpu, mask)
 323                 map |= 1 << cpu_logical_map(cpu);
 324
 325         /*
 326          * Ensure that stores to Normal memory are visible to the
 327          * other CPUs before issuing the IPI.
 328          */
 329         dsb();
 330
 331         /* submit softirq */
 332         writel((map << 8) | irq, main_int_base +
 333                 ARMADA_370_XP_SW_TRIG_INT_OFFS);
 334 }
 335
 336 void armada_xp_mpic_smp_cpu_init(void)
 337 {
 338         /* Clear pending IPIs */
 339         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 340
 341         /* Enable first 8 IPIs */
 342         writel(IPI_DOORBELL_MASK, per_cpu_int_base +
 343                 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 344
 345         /* Unmask IPI interrupt */
 346         writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 347 }
 348 #endif /* CONFIG_SMP */
 349
 350 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 351         .map = armada_370_xp_mpic_irq_map,
 352         .xlate = irq_domain_xlate_onecell,
 353 };
 354
 355 static asmlinkage void __exception_irq_entry
 356 armada_370_xp_handle_irq(struct pt_regs *regs)
 357 {
 358         u32 irqstat, irqnr;
 359
 360         do {
 361                 irqstat = readl_relaxed(per_cpu_int_base +
 362                                         ARMADA_370_XP_CPU_INTACK_OFFS);
 363                 irqnr = irqstat & 0x3FF;
 364
 365                 if (irqnr > 1022)
 366                         break;
 367
 368                 if (irqnr > 1) {
 369                         irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
 370                                         irqnr);
 371                         handle_IRQ(irqnr, regs);
 372                         continue;
 373                 }
 374
 375 #ifdef CONFIG_PCI_MSI
 376                 /* MSI handling */
 377                 if (irqnr == 1) {
 378                         u32 msimask, msinr;
 379
 380                         msimask = readl_relaxed(per_cpu_int_base +
 381                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 382                                 & PCI_MSI_DOORBELL_MASK;
 383
 384                         writel(~msimask, per_cpu_int_base +
 385                                ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 386
 387                         for (msinr = PCI_MSI_DOORBELL_START;
 388                              msinr < PCI_MSI_DOORBELL_END; msinr++) {
 389                                 int irq;
 390
 391                                 if (!(msimask & BIT(msinr)))
 392                                         continue;
 393
 394                                 irq = irq_find_mapping(armada_370_xp_msi_domain,
 395                                                        msinr - 16);
 396                                 handle_IRQ(irq, regs);
 397                         }
 398                 }
 399 #endif
 400
 401 #ifdef CONFIG_SMP
 402                 /* IPI Handling */
 403                 if (irqnr == 0) {
 404                         u32 ipimask, ipinr;
 405
 406                         ipimask = readl_relaxed(per_cpu_int_base +
 407                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 408                                 & IPI_DOORBELL_MASK;
 409
 410                         writel(~ipimask, per_cpu_int_base +
 411                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 412
 413                         /* Handle all pending doorbells */
 414                         for (ipinr = IPI_DOORBELL_START;
 415                              ipinr < IPI_DOORBELL_END; ipinr++) {
 416                                 if (ipimask & (0x1 << ipinr))
 417                                         handle_IPI(ipinr, regs);
 418                         }
 419                         continue;
 420                 }
 421 #endif
 422
 423         } while (1);
 424 }
 425
 426 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 427                                              struct device_node *parent)
 428 {
 429         struct resource main_int_res, per_cpu_int_res;
 430         u32 control;
 431
 432         BUG_ON(of_address_to_resource(node, 0, &main_int_res));
 433         BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
 434
 435         BUG_ON(!request_mem_region(main_int_res.start,
 436                                    resource_size(&main_int_res),
 437                                    node->full_name));
 438         BUG_ON(!request_mem_region(per_cpu_int_res.start,
 439                                    resource_size(&per_cpu_int_res),
 440                                    node->full_name));
 441
 442         main_int_base = ioremap(main_int_res.start,
 443                                 resource_size(&main_int_res));
 444         BUG_ON(!main_int_base);
 445
 446         per_cpu_int_base = ioremap(per_cpu_int_res.start,
 447                                    resource_size(&per_cpu_int_res));
 448         BUG_ON(!per_cpu_int_base);
 449
 450         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 451
 452         armada_370_xp_mpic_domain =
 453                 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
 454                                 &armada_370_xp_mpic_irq_ops, NULL);
 455
 456         BUG_ON(!armada_370_xp_mpic_domain);
 457
 458         irq_set_default_host(armada_370_xp_mpic_domain);
 459
 460 #ifdef CONFIG_SMP
 461         armada_xp_mpic_smp_cpu_init();
 462
 463         /*
 464          * Set the default affinity from all CPUs to the boot cpu.
 465          * This is required since the MPIC doesn't limit several CPUs
 466          * from acknowledging the same interrupt.
 467          */
 468         cpumask_clear(irq_default_affinity);
 469         cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
 470
 471 #endif
 472
 473         armada_370_xp_msi_init(node, main_int_res.start);
 474
 475         set_handle_irq(armada_370_xp_handle_irq);
 476
 477         return 0;
 478 }
 479
 480 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);