drivers/irqchip/irq-bcm2835.c

   1 /*
   2  * Copyright 2010 Broadcom
   3  * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
  16  *
  17  * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
  18  * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
  19  * to look in the bank 1 status register for more information.
  20  *
  21  * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
  22  * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
  23  * status register, but bank 0 bit 8 is _not_ set.
  24  *
  25  * Quirk 2: You can't mask the register 1/2 pending interrupts
  26  *
  27  * In a proper cascaded interrupt controller, the interrupt lines with
  28  * cascaded interrupt controllers on them are just normal interrupt lines.
  29  * You can mask the interrupts and get on with things. With this controller
  30  * you can't do that.
  31  *
  32  * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
  33  *
  34  * Those interrupts that have shortcuts can only be masked/unmasked in
  35  * their respective banks' enable/disable registers. Doing so in the bank 0
  36  * enable/disable registers has no effect.
  37  *
  38  * The FIQ control register:
  39  *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
  40  *  Bit    7: Enable FIQ generation
  41  *  Bits  8+: Unused
  42  *
  43  * An interrupt must be disabled before configuring it for FIQ generation
  44  * otherwise both handlers will fire at the same time!
  45  */
  46
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/of_address.h>
  50 #include <linux/of_irq.h>
  51 #include <linux/irqchip.h>
  52 #include <linux/irqdomain.h>
  53 #include <linux/mfd/syscon.h>
  54 #include <linux/regmap.h>
  55
  56 #include <asm/exception.h>
  57 #ifndef CONFIG_ARM64
  58 #include <asm/mach/irq.h>
  59 #endif
  60
  61 /* Put the bank and irq (32 bits) into the hwirq */
  62 #define MAKE_HWIRQ(b, n)        (((b) << 5) | (n))
  63 #define HWIRQ_BANK(i)           (i >> 5)
  64 #define HWIRQ_BIT(i)            BIT(i & 0x1f)
  65
  66 #define NR_IRQS_BANK0           8
  67 #define BANK0_HWIRQ_MASK        0xff
  68 /* Shortcuts can't be disabled so any unknown new ones need to be masked */
  69 #define SHORTCUT1_MASK          0x00007c00
  70 #define SHORTCUT2_MASK          0x001f8000
  71 #define SHORTCUT_SHIFT          10
  72 #define BANK1_HWIRQ             BIT(8)
  73 #define BANK2_HWIRQ             BIT(9)
  74 #define BANK0_VALID_MASK        (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
  75                                         | SHORTCUT1_MASK | SHORTCUT2_MASK)
  76
  77 #undef ARM_LOCAL_GPU_INT_ROUTING
  78 #define ARM_LOCAL_GPU_INT_ROUTING 0x0c
  79
  80 #define REG_FIQ_CONTROL         0x0c
  81 #define REG_FIQ_ENABLE          0x80
  82 #define REG_FIQ_DISABLE         0
  83
  84 #define NR_BANKS                3
  85 #define IRQS_PER_BANK           32
  86 #define NUMBER_IRQS             MAKE_HWIRQ(NR_BANKS, 0)
  87 #undef FIQ_START
  88 #define FIQ_START               (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))
  89
  90 static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
  91 static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
  92 static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
  93 static const int bank_irqs[] __initconst = { 8, 32, 32 };
  94
  95 static const int shortcuts[] = {
  96         7, 9, 10, 18, 19,               /* Bank 1 */
  97         21, 22, 23, 24, 25, 30          /* Bank 2 */
  98 };
  99
 100 struct armctrl_ic {
 101         void __iomem *base;
 102         void __iomem *pending[NR_BANKS];
 103         void __iomem *enable[NR_BANKS];
 104         void __iomem *disable[NR_BANKS];
 105         struct irq_domain *domain;
 106         struct regmap *local_regmap;
 107 };
 108
 109 static struct armctrl_ic intc __read_mostly;
 110 static void __exception_irq_entry bcm2835_handle_irq(
 111         struct pt_regs *regs);
 112 static void bcm2836_chained_handle_irq(struct irq_desc *desc);
 113
 114 static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
 115 {
 116         hwirq -= NUMBER_IRQS;
 117         /*
 118          * The hwirq numbering used in this driver is:
 119          *   BASE (0-7) GPU1 (32-63) GPU2 (64-95).
 120          * This differ from the one used in the FIQ register:
 121          *   GPU1 (0-31) GPU2 (32-63) BASE (64-71)
 122          */
 123         if (hwirq >= 32)
 124                 return hwirq - 32;
 125
 126         return hwirq + 64;
 127 }
 128
 129 static void armctrl_mask_irq(struct irq_data *d)
 130 {
 131         if (d->hwirq >= NUMBER_IRQS)
 132                 writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
 133         else
 134                 writel_relaxed(HWIRQ_BIT(d->hwirq),
 135                                intc.disable[HWIRQ_BANK(d->hwirq)]);
 136 }
 137
 138 static void armctrl_unmask_irq(struct irq_data *d)
 139 {
 140         if (d->hwirq >= NUMBER_IRQS) {
 141                 if (num_online_cpus() > 1) {
 142                         unsigned int data;
 143                         int ret;
 144
 145                         if (!intc.local_regmap) {
 146                                 pr_err("FIQ is disabled due to missing regmap\n");
 147                                 return;
 148                         }
 149
 150                         ret = regmap_read(intc.local_regmap,
 151                                           ARM_LOCAL_GPU_INT_ROUTING, &data);
 152                         if (ret) {
 153                                 pr_err("Failed to read int routing %d\n", ret);
 154                                 return;
 155                         }
 156
 157                         data &= ~0xc;
 158                         data |= (1 << 2);
 159                         regmap_write(intc.local_regmap,
 160                                      ARM_LOCAL_GPU_INT_ROUTING, data);
 161                 }
 162
 163                 writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
 164                                intc.base + REG_FIQ_CONTROL);
 165         } else {
 166                 writel_relaxed(HWIRQ_BIT(d->hwirq),
 167                                intc.enable[HWIRQ_BANK(d->hwirq)]);
 168         }
 169 }
 170
 171 static struct irq_chip armctrl_chip = {
 172         .name = "ARMCTRL-level",
 173         .irq_mask = armctrl_mask_irq,
 174         .irq_unmask = armctrl_unmask_irq
 175 };
 176
 177 static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
 178         const u32 *intspec, unsigned int intsize,
 179         unsigned long *out_hwirq, unsigned int *out_type)
 180 {
 181         if (WARN_ON(intsize != 2))
 182                 return -EINVAL;
 183
 184         if (WARN_ON(intspec[0] >= NR_BANKS))
 185                 return -EINVAL;
 186
 187         if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
 188                 return -EINVAL;
 189
 190         if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
 191                 return -EINVAL;
 192
 193         *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
 194         *out_type = IRQ_TYPE_NONE;
 195         return 0;
 196 }
 197
 198 static const struct irq_domain_ops armctrl_ops = {
 199         .xlate = armctrl_xlate
 200 };
 201
 202 static int __init armctrl_of_init(struct device_node *node,
 203                                   struct device_node *parent,
 204                                   bool is_2836)
 205 {
 206         void __iomem *base;
 207         int irq, b, i;
 208
 209         base = of_iomap(node, 0);
 210         if (!base)
 211                 panic("%s: unable to map IC registers\n",
 212                         node->full_name);
 213
 214         intc.base = base;
 215         intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
 216                                             &armctrl_ops, NULL);
 217         if (!intc.domain)
 218                 panic("%s: unable to create IRQ domain\n", node->full_name);
 219
 220         for (b = 0; b < NR_BANKS; b++) {
 221                 intc.pending[b] = base + reg_pending[b];
 222                 intc.enable[b] = base + reg_enable[b];
 223                 intc.disable[b] = base + reg_disable[b];
 224
 225                 for (i = 0; i < bank_irqs[b]; i++) {
 226                         irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
 227                         BUG_ON(irq <= 0);
 228                         irq_set_chip_and_handler(irq, &armctrl_chip,
 229                                 handle_level_irq);
 230                         irq_set_probe(irq);
 231                 }
 232         }
 233
 234         if (is_2836) {
 235                 int parent_irq = irq_of_parse_and_map(node, 0);
 236
 237                 if (!parent_irq) {
 238                         panic("%s: unable to get parent interrupt.\n",
 239                               node->full_name);
 240                 }
 241                 irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
 242         } else {
 243                 set_handle_irq(bcm2835_handle_irq);
 244         }
 245
 246         if (is_2836) {
 247                 intc.local_regmap =
 248                         syscon_regmap_lookup_by_compatible("brcm,bcm2836-arm-local");
 249                 if (IS_ERR(intc.local_regmap)) {
 250                         pr_err("Failed to get local register map. FIQ is disabled for cpus > 1\n");
 251                         intc.local_regmap = NULL;
 252                 }
 253         }
 254
 255         /* Make a duplicate irq range which is used to enable FIQ */
 256         for (b = 0; b < NR_BANKS; b++) {
 257                 for (i = 0; i < bank_irqs[b]; i++) {
 258                         irq = irq_create_mapping(intc.domain,
 259                                         MAKE_HWIRQ(b, i) + NUMBER_IRQS);
 260                         BUG_ON(irq <= 0);
 261                         irq_set_chip(irq, &armctrl_chip);
 262                         irq_set_probe(irq);
 263                 }
 264         }
 265 #ifndef CONFIG_ARM64
 266         init_FIQ(FIQ_START);
 267 #endif
 268
 269         return 0;
 270 }
 271
 272 static int __init bcm2835_armctrl_of_init(struct device_node *node,
 273                                           struct device_node *parent)
 274 {
 275         return armctrl_of_init(node, parent, false);
 276 }
 277
 278 static int __init bcm2836_armctrl_of_init(struct device_node *node,
 279                                           struct device_node *parent)
 280 {
 281         return armctrl_of_init(node, parent, true);
 282 }
 283
 284
 285 /*
 286  * Handle each interrupt across the entire interrupt controller.  This reads the
 287  * status register before handling each interrupt, which is necessary given that
 288  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 289  */
 290
 291 static u32 armctrl_translate_bank(int bank)
 292 {
 293         u32 stat = readl_relaxed(intc.pending[bank]);
 294
 295         return MAKE_HWIRQ(bank, ffs(stat) - 1);
 296 }
 297
 298 static u32 armctrl_translate_shortcut(int bank, u32 stat)
 299 {
 300         return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
 301 }
 302
 303 static u32 get_next_armctrl_hwirq(void)
 304 {
 305         u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
 306
 307         if (stat == 0)
 308                 return ~0;
 309         else if (stat & BANK0_HWIRQ_MASK)
 310                 return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
 311         else if (stat & SHORTCUT1_MASK)
 312                 return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
 313         else if (stat & SHORTCUT2_MASK)
 314                 return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
 315         else if (stat & BANK1_HWIRQ)
 316                 return armctrl_translate_bank(1);
 317         else if (stat & BANK2_HWIRQ)
 318                 return armctrl_translate_bank(2);
 319         else
 320                 BUG();
 321 }
 322
 323 static void __exception_irq_entry bcm2835_handle_irq(
 324         struct pt_regs *regs)
 325 {
 326         u32 hwirq;
 327
 328         while ((hwirq = get_next_armctrl_hwirq()) != ~0)
 329                 handle_domain_irq(intc.domain, hwirq, regs);
 330 }
 331
 332 static void bcm2836_chained_handle_irq(struct irq_desc *desc)
 333 {
 334         u32 hwirq;
 335
 336         while ((hwirq = get_next_armctrl_hwirq()) != ~0)
 337                 generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
 338 }
 339
 340 IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
 341                 bcm2835_armctrl_of_init);
 342 IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
 343                 bcm2836_armctrl_of_init);