2 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
4 * Copyright 2015 Broadcom
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/cpu.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/irqchip.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irqchip/irq-bcm2836.h>
24 #include <asm/exception.h>
26 struct bcm2836_arm_irqchip_intc
{
27 struct irq_domain
*domain
;
31 static struct bcm2836_arm_irqchip_intc intc __read_mostly
;
33 static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset
,
37 void __iomem
*reg
= intc
.base
+ reg_offset
+ 4 * cpu
;
39 writel(readl(reg
) & ~BIT(bit
), reg
);
42 static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset
,
46 void __iomem
*reg
= intc
.base
+ reg_offset
+ 4 * cpu
;
48 writel(readl(reg
) | BIT(bit
), reg
);
51 static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data
*d
)
53 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0
,
54 d
->hwirq
- LOCAL_IRQ_CNTPSIRQ
,
58 static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data
*d
)
60 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0
,
61 d
->hwirq
- LOCAL_IRQ_CNTPSIRQ
,
65 static struct irq_chip bcm2836_arm_irqchip_timer
= {
66 .name
= "bcm2836-timer",
67 .irq_mask
= bcm2836_arm_irqchip_mask_timer_irq
,
68 .irq_unmask
= bcm2836_arm_irqchip_unmask_timer_irq
,
71 static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data
*d
)
73 writel(1 << smp_processor_id(), intc
.base
+ LOCAL_PM_ROUTING_CLR
);
76 static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data
*d
)
78 writel(1 << smp_processor_id(), intc
.base
+ LOCAL_PM_ROUTING_SET
);
81 static struct irq_chip bcm2836_arm_irqchip_pmu
= {
82 .name
= "bcm2836-pmu",
83 .irq_mask
= bcm2836_arm_irqchip_mask_pmu_irq
,
84 .irq_unmask
= bcm2836_arm_irqchip_unmask_pmu_irq
,
87 static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data
*d
)
91 static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data
*d
)
95 static struct irq_chip bcm2836_arm_irqchip_gpu
= {
96 .name
= "bcm2836-gpu",
97 .irq_mask
= bcm2836_arm_irqchip_mask_gpu_irq
,
98 .irq_unmask
= bcm2836_arm_irqchip_unmask_gpu_irq
,
101 static void bcm2836_arm_irqchip_register_irq(int hwirq
, struct irq_chip
*chip
)
103 int irq
= irq_create_mapping(intc
.domain
, hwirq
);
105 irq_set_percpu_devid(irq
);
106 irq_set_chip_and_handler(irq
, chip
, handle_percpu_devid_irq
);
107 irq_set_status_flags(irq
, IRQ_NOAUTOEN
);
111 __exception_irq_entry
bcm2836_arm_irqchip_handle_irq(struct pt_regs
*regs
)
113 int cpu
= smp_processor_id();
116 stat
= readl_relaxed(intc
.base
+ LOCAL_IRQ_PENDING0
+ 4 * cpu
);
117 if (stat
& BIT(LOCAL_IRQ_MAILBOX0
)) {
119 void __iomem
*mailbox0
= (intc
.base
+
120 LOCAL_MAILBOX0_CLR0
+ 16 * cpu
);
121 u32 mbox_val
= readl(mailbox0
);
122 u32 ipi
= ffs(mbox_val
) - 1;
124 writel(1 << ipi
, mailbox0
);
125 handle_IPI(ipi
, regs
);
128 u32 hwirq
= ffs(stat
) - 1;
130 handle_domain_irq(intc
.domain
, hwirq
, regs
);
135 static void bcm2836_arm_irqchip_send_ipi(const struct cpumask
*mask
,
139 void __iomem
*mailbox0_base
= intc
.base
+ LOCAL_MAILBOX0_SET0
;
142 * Ensure that stores to normal memory are visible to the
143 * other CPUs before issuing the IPI.
147 for_each_cpu(cpu
, mask
) {
148 writel(1 << ipi
, mailbox0_base
+ 16 * cpu
);
152 static int bcm2836_cpu_starting(unsigned int cpu
)
154 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0
, 0,
159 static int bcm2836_cpu_dying(unsigned int cpu
)
161 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0
, 0,
167 static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops
= {
168 .xlate
= irq_domain_xlate_onecell
172 bcm2836_arm_irqchip_smp_init(void)
175 /* Unmask IPIs to the boot CPU. */
176 cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING
,
177 "irqchip/bcm2836:starting", bcm2836_cpu_starting
,
180 set_smp_cross_call(bcm2836_arm_irqchip_send_ipi
);
185 * The LOCAL_IRQ_CNT* timer firings are based off of the external
186 * oscillator with some scaling. The firmware sets up CNTFRQ to
187 * report 19.2Mhz, but doesn't set up the scaling registers.
189 static void bcm2835_init_local_timer_frequency(void)
192 * Set the timer to source from the 19.2Mhz crystal clock (bit
193 * 8 unset), and only increment by 1 instead of 2 (bit 9
196 writel(0, intc
.base
+ LOCAL_CONTROL
);
199 * Set the timer prescaler to 1:1 (timer freq = input freq *
202 writel(0x80000000, intc
.base
+ LOCAL_PRESCALER
);
205 static int __init
bcm2836_arm_irqchip_l1_intc_of_init(struct device_node
*node
,
206 struct device_node
*parent
)
208 intc
.base
= of_iomap(node
, 0);
210 panic("%pOF: unable to map local interrupt registers\n", node
);
213 bcm2835_init_local_timer_frequency();
215 intc
.domain
= irq_domain_add_linear(node
, LAST_IRQ
+ 1,
216 &bcm2836_arm_irqchip_intc_ops
,
219 panic("%pOF: unable to create IRQ domain\n", node
);
221 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ
,
222 &bcm2836_arm_irqchip_timer
);
223 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ
,
224 &bcm2836_arm_irqchip_timer
);
225 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ
,
226 &bcm2836_arm_irqchip_timer
);
227 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ
,
228 &bcm2836_arm_irqchip_timer
);
229 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST
,
230 &bcm2836_arm_irqchip_gpu
);
231 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST
,
232 &bcm2836_arm_irqchip_pmu
);
234 bcm2836_arm_irqchip_smp_init();
236 set_handle_irq(bcm2836_arm_irqchip_handle_irq
);
240 IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc
, "brcm,bcm2836-l1-intc",
241 bcm2836_arm_irqchip_l1_intc_of_init
);