2 * drivers/irqchip/irq-crossbar.c
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sricharan R <r.sricharan@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
22 #define IRQ_RESERVED -2
24 #define GIC_IRQ_START 32
27 * struct crossbar_device - crossbar device description
28 * @lock: spinlock serializing access to @irq_map
29 * @int_max: maximum number of supported interrupts
30 * @safe_map: safe default value to initialize the crossbar
31 * @max_crossbar_sources: Maximum number of crossbar sources
32 * @irq_map: array of interrupts to crossbar number mapping
33 * @crossbar_base: crossbar base address
34 * @register_offsets: offsets for each irq number
35 * @write: register write function pointer
37 struct crossbar_device
{
41 uint max_crossbar_sources
;
43 void __iomem
*crossbar_base
;
44 int *register_offsets
;
45 void (*write
)(int, int);
48 static struct crossbar_device
*cb
;
50 static void crossbar_writel(int irq_no
, int cb_no
)
52 writel(cb_no
, cb
->crossbar_base
+ cb
->register_offsets
[irq_no
]);
55 static void crossbar_writew(int irq_no
, int cb_no
)
57 writew(cb_no
, cb
->crossbar_base
+ cb
->register_offsets
[irq_no
]);
60 static void crossbar_writeb(int irq_no
, int cb_no
)
62 writeb(cb_no
, cb
->crossbar_base
+ cb
->register_offsets
[irq_no
]);
65 static struct irq_chip crossbar_chip
= {
67 .irq_eoi
= irq_chip_eoi_parent
,
68 .irq_mask
= irq_chip_mask_parent
,
69 .irq_unmask
= irq_chip_unmask_parent
,
70 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
71 .irq_set_type
= irq_chip_set_type_parent
,
72 .flags
= IRQCHIP_MASK_ON_SUSPEND
|
73 IRQCHIP_SKIP_SET_WAKE
,
75 .irq_set_affinity
= irq_chip_set_affinity_parent
,
79 static int allocate_gic_irq(struct irq_domain
*domain
, unsigned virq
,
80 irq_hw_number_t hwirq
)
82 struct of_phandle_args args
;
86 raw_spin_lock(&cb
->lock
);
87 for (i
= cb
->int_max
- 1; i
>= 0; i
--) {
88 if (cb
->irq_map
[i
] == IRQ_FREE
) {
89 cb
->irq_map
[i
] = hwirq
;
93 raw_spin_unlock(&cb
->lock
);
98 args
.np
= domain
->parent
->of_node
;
100 args
.args
[0] = 0; /* SPI */
102 args
.args
[2] = IRQ_TYPE_LEVEL_HIGH
;
104 err
= irq_domain_alloc_irqs_parent(domain
, virq
, 1, &args
);
106 cb
->irq_map
[i
] = IRQ_FREE
;
113 static int crossbar_domain_alloc(struct irq_domain
*d
, unsigned int virq
,
114 unsigned int nr_irqs
, void *data
)
116 struct of_phandle_args
*args
= data
;
117 irq_hw_number_t hwirq
;
120 if (args
->args_count
!= 3)
121 return -EINVAL
; /* Not GIC compliant */
122 if (args
->args
[0] != 0)
123 return -EINVAL
; /* No PPI should point to this domain */
125 hwirq
= args
->args
[1];
126 if ((hwirq
+ nr_irqs
) > cb
->max_crossbar_sources
)
127 return -EINVAL
; /* Can't deal with this */
129 for (i
= 0; i
< nr_irqs
; i
++) {
130 int err
= allocate_gic_irq(d
, virq
+ i
, hwirq
+ i
);
135 irq_domain_set_hwirq_and_chip(d
, virq
+ i
, hwirq
+ i
,
136 &crossbar_chip
, NULL
);
143 * crossbar_domain_free - unmap/free a crossbar<->irq connection
144 * @domain: domain of irq to unmap
146 * @nr_irqs: number of irqs to free
148 * We do not maintain a use count of total number of map/unmap
149 * calls for a particular irq to find out if a irq can be really
150 * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
151 * after which irq is anyways unusable. So an explicit map has to be called
154 static void crossbar_domain_free(struct irq_domain
*domain
, unsigned int virq
,
155 unsigned int nr_irqs
)
159 raw_spin_lock(&cb
->lock
);
160 for (i
= 0; i
< nr_irqs
; i
++) {
161 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
+ i
);
163 irq_domain_reset_irq_data(d
);
164 cb
->irq_map
[d
->hwirq
] = IRQ_FREE
;
165 cb
->write(d
->hwirq
, cb
->safe_map
);
167 raw_spin_unlock(&cb
->lock
);
170 static int crossbar_domain_xlate(struct irq_domain
*d
,
171 struct device_node
*controller
,
172 const u32
*intspec
, unsigned int intsize
,
173 unsigned long *out_hwirq
,
174 unsigned int *out_type
)
176 if (d
->of_node
!= controller
)
177 return -EINVAL
; /* Shouldn't happen, really... */
179 return -EINVAL
; /* Not GIC compliant */
181 return -EINVAL
; /* No PPI should point to this domain */
183 *out_hwirq
= intspec
[1];
184 *out_type
= intspec
[2];
188 static const struct irq_domain_ops crossbar_domain_ops
= {
189 .alloc
= crossbar_domain_alloc
,
190 .free
= crossbar_domain_free
,
191 .xlate
= crossbar_domain_xlate
,
194 static int __init
crossbar_of_init(struct device_node
*node
)
196 int i
, size
, max
= 0, reserved
= 0, entry
;
200 cb
= kzalloc(sizeof(*cb
), GFP_KERNEL
);
205 cb
->crossbar_base
= of_iomap(node
, 0);
206 if (!cb
->crossbar_base
)
209 of_property_read_u32(node
, "ti,max-crossbar-sources",
210 &cb
->max_crossbar_sources
);
211 if (!cb
->max_crossbar_sources
) {
212 pr_err("missing 'ti,max-crossbar-sources' property\n");
217 of_property_read_u32(node
, "ti,max-irqs", &max
);
219 pr_err("missing 'ti,max-irqs' property\n");
223 cb
->irq_map
= kcalloc(max
, sizeof(int), GFP_KERNEL
);
229 for (i
= 0; i
< max
; i
++)
230 cb
->irq_map
[i
] = IRQ_FREE
;
232 /* Get and mark reserved irqs */
233 irqsr
= of_get_property(node
, "ti,irqs-reserved", &size
);
235 size
/= sizeof(__be32
);
237 for (i
= 0; i
< size
; i
++) {
238 of_property_read_u32_index(node
,
242 pr_err("Invalid reserved entry\n");
246 cb
->irq_map
[entry
] = IRQ_RESERVED
;
250 /* Skip irqs hardwired to bypass the crossbar */
251 irqsr
= of_get_property(node
, "ti,irqs-skip", &size
);
253 size
/= sizeof(__be32
);
255 for (i
= 0; i
< size
; i
++) {
256 of_property_read_u32_index(node
,
260 pr_err("Invalid skip entry\n");
264 cb
->irq_map
[entry
] = IRQ_SKIP
;
269 cb
->register_offsets
= kcalloc(max
, sizeof(int), GFP_KERNEL
);
270 if (!cb
->register_offsets
)
273 of_property_read_u32(node
, "ti,reg-size", &size
);
277 cb
->write
= crossbar_writeb
;
280 cb
->write
= crossbar_writew
;
283 cb
->write
= crossbar_writel
;
286 pr_err("Invalid reg-size property\n");
293 * Register offsets are not linear because of the
294 * reserved irqs. so find and store the offsets once.
296 for (i
= 0; i
< max
; i
++) {
297 if (cb
->irq_map
[i
] == IRQ_RESERVED
)
300 cb
->register_offsets
[i
] = reserved
;
304 of_property_read_u32(node
, "ti,irqs-safe-map", &cb
->safe_map
);
305 /* Initialize the crossbar with safe map to start with */
306 for (i
= 0; i
< max
; i
++) {
307 if (cb
->irq_map
[i
] == IRQ_RESERVED
||
308 cb
->irq_map
[i
] == IRQ_SKIP
)
311 cb
->write(i
, cb
->safe_map
);
314 raw_spin_lock_init(&cb
->lock
);
319 kfree(cb
->register_offsets
);
323 iounmap(cb
->crossbar_base
);
331 static int __init
irqcrossbar_init(struct device_node
*node
,
332 struct device_node
*parent
)
334 struct irq_domain
*parent_domain
, *domain
;
338 pr_err("%s: no parent, giving up\n", node
->full_name
);
342 parent_domain
= irq_find_host(parent
);
343 if (!parent_domain
) {
344 pr_err("%s: unable to obtain parent domain\n", node
->full_name
);
348 err
= crossbar_of_init(node
);
352 domain
= irq_domain_add_hierarchy(parent_domain
, 0,
353 cb
->max_crossbar_sources
,
354 node
, &crossbar_domain_ops
,
357 pr_err("%s: failed to allocated domain\n", node
->full_name
);
364 IRQCHIP_DECLARE(ti_irqcrossbar
, "ti,irq-crossbar", irqcrossbar_init
);