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2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqchip/arm-gic.h>
22 #include "irq-gic-common.h"
24 void gic_configure_irq(unsigned int irq
, unsigned int type
,
25 void __iomem
*base
, void (*sync_access
)(void))
27 u32 enablemask
= 1 << (irq
% 32);
28 u32 enableoff
= (irq
/ 32) * 4;
29 u32 confmask
= 0x2 << ((irq
% 16) * 2);
30 u32 confoff
= (irq
/ 16) * 4;
35 * Read current configuration register, and insert the config
36 * for "irq", depending on "type".
38 val
= readl_relaxed(base
+ GIC_DIST_CONFIG
+ confoff
);
39 if (type
== IRQ_TYPE_LEVEL_HIGH
)
41 else if (type
== IRQ_TYPE_EDGE_RISING
)
45 * As recommended by the spec, disable the interrupt before changing
48 if (readl_relaxed(base
+ GIC_DIST_ENABLE_SET
+ enableoff
) & enablemask
) {
49 writel_relaxed(enablemask
, base
+ GIC_DIST_ENABLE_CLEAR
+ enableoff
);
56 * Write back the new configuration, and possibly re-enable
59 writel_relaxed(val
, base
+ GIC_DIST_CONFIG
+ confoff
);
62 writel_relaxed(enablemask
, base
+ GIC_DIST_ENABLE_SET
+ enableoff
);
68 void __init
gic_dist_config(void __iomem
*base
, int gic_irqs
,
69 void (*sync_access
)(void))
74 * Set all global interrupts to be level triggered, active low.
76 for (i
= 32; i
< gic_irqs
; i
+= 16)
77 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG
,
78 base
+ GIC_DIST_CONFIG
+ i
/ 4);
81 * Set priority on all global interrupts.
83 for (i
= 32; i
< gic_irqs
; i
+= 4)
84 writel_relaxed(GICD_INT_DEF_PRI_X4
, base
+ GIC_DIST_PRI
+ i
);
87 * Disable all interrupts. Leave the PPI and SGIs alone
88 * as they are enabled by redistributor registers.
90 for (i
= 32; i
< gic_irqs
; i
+= 32)
91 writel_relaxed(GICD_INT_EN_CLR_X32
,
92 base
+ GIC_DIST_ENABLE_CLEAR
+ i
/ 8);
98 void gic_cpu_config(void __iomem
*base
, void (*sync_access
)(void))
103 * Deal with the banked PPI and SGI interrupts - disable all
104 * PPI interrupts, ensure all SGI interrupts are enabled.
106 writel_relaxed(GICD_INT_EN_CLR_PPI
, base
+ GIC_DIST_ENABLE_CLEAR
);
107 writel_relaxed(GICD_INT_EN_SET_SGI
, base
+ GIC_DIST_ENABLE_SET
);
110 * Set priority on PPI and SGI interrupts
112 for (i
= 0; i
< 32; i
+= 4)
113 writel_relaxed(GICD_INT_DEF_PRI_X4
,
114 base
+ GIC_DIST_PRI
+ i
* 4 / 4);