drivers/irqchip/irq-gic-v2m.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARM GIC v2m MSI(-X) support
   4  * Support for Message Signaled Interrupts for systems that
   5  * implement ARM Generic Interrupt Controller: GICv2m.
   6  *
   7  * Copyright (C) 2014 Advanced Micro Devices, Inc.
   8  * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
   9  *          Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
  10  *          Brandon Anderson <brandon.anderson@amd.com>
  11  */
  12
  13 #define pr_fmt(fmt) "GICv2m: " fmt
  14
  15 #include <linux/acpi.h>
  16 #include <linux/dma-iommu.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/kernel.h>
  20 #include <linux/pci.h>
  21 #include <linux/msi.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/irqchip/arm-gic.h>
  27
  28 /*
  29 * MSI_TYPER:
  30 *     [31:26] Reserved
  31 *     [25:16] lowest SPI assigned to MSI
  32 *     [15:10] Reserved
  33 *     [9:0]   Numer of SPIs assigned to MSI
  34 */
  35 #define V2M_MSI_TYPER                  0x008
  36 #define V2M_MSI_TYPER_BASE_SHIFT       16
  37 #define V2M_MSI_TYPER_BASE_MASK        0x3FF
  38 #define V2M_MSI_TYPER_NUM_MASK         0x3FF
  39 #define V2M_MSI_SETSPI_NS              0x040
  40 #define V2M_MIN_SPI                    32
  41 #define V2M_MAX_SPI                    1019
  42 #define V2M_MSI_IIDR                   0xFCC
  43
  44 #define V2M_MSI_TYPER_BASE_SPI(x)      \
  45                (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
  46
  47 #define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)
  48
  49 /* APM X-Gene with GICv2m MSI_IIDR register value */
  50 #define XGENE_GICV2M_MSI_IIDR           0x06000170
  51
  52 /* Broadcom NS2 GICv2m MSI_IIDR register value */
  53 #define BCM_NS2_GICV2M_MSI_IIDR         0x0000013f
  54
  55 /* List of flags for specific v2m implementation */
  56 #define GICV2M_NEEDS_SPI_OFFSET         0x00000001
  57 #define GICV2M_GRAVITON_ADDRESS_ONLY    0x00000002
  58
  59 static LIST_HEAD(v2m_nodes);
  60 static DEFINE_SPINLOCK(v2m_lock);
  61
  62 struct v2m_data {
  63         struct list_head entry;
  64         struct fwnode_handle *fwnode;
  65         struct resource res;    /* GICv2m resource */
  66         void __iomem *base;     /* GICv2m virt address */
  67         u32 spi_start;          /* The SPI number that MSIs start */
  68         u32 nr_spis;            /* The number of SPIs for MSIs */
  69         u32 spi_offset;         /* offset to be subtracted from SPI number */
  70         unsigned long *bm;      /* MSI vector bitmap */
  71         u32 flags;              /* v2m flags for specific implementation */
  72 };
  73
  74 static void gicv2m_mask_msi_irq(struct irq_data *d)
  75 {
  76         pci_msi_mask_irq(d);
  77         irq_chip_mask_parent(d);
  78 }
  79
  80 static void gicv2m_unmask_msi_irq(struct irq_data *d)
  81 {
  82         pci_msi_unmask_irq(d);
  83         irq_chip_unmask_parent(d);
  84 }
  85
  86 static struct irq_chip gicv2m_msi_irq_chip = {
  87         .name                   = "MSI",
  88         .irq_mask               = gicv2m_mask_msi_irq,
  89         .irq_unmask             = gicv2m_unmask_msi_irq,
  90         .irq_eoi                = irq_chip_eoi_parent,
  91         .irq_write_msi_msg      = pci_msi_domain_write_msg,
  92 };
  93
  94 static struct msi_domain_info gicv2m_msi_domain_info = {
  95         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  96                    MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
  97         .chip   = &gicv2m_msi_irq_chip,
  98 };
  99
 100 static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq)
 101 {
 102         if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
 103                 return v2m->res.start | ((hwirq - 32) << 3);
 104         else
 105                 return v2m->res.start + V2M_MSI_SETSPI_NS;
 106 }
 107
 108 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 109 {
 110         struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
 111         phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq);
 112
 113         msg->address_hi = upper_32_bits(addr);
 114         msg->address_lo = lower_32_bits(addr);
 115
 116         if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
 117                 msg->data = 0;
 118         else
 119                 msg->data = data->hwirq;
 120         if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
 121                 msg->data -= v2m->spi_offset;
 122
 123         iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
 124 }
 125
 126 static struct irq_chip gicv2m_irq_chip = {
 127         .name                   = "GICv2m",
 128         .irq_mask               = irq_chip_mask_parent,
 129         .irq_unmask             = irq_chip_unmask_parent,
 130         .irq_eoi                = irq_chip_eoi_parent,
 131         .irq_set_affinity       = irq_chip_set_affinity_parent,
 132         .irq_compose_msi_msg    = gicv2m_compose_msi_msg,
 133 };
 134
 135 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
 136                                        unsigned int virq,
 137                                        irq_hw_number_t hwirq)
 138 {
 139         struct irq_fwspec fwspec;
 140         struct irq_data *d;
 141         int err;
 142
 143         if (is_of_node(domain->parent->fwnode)) {
 144                 fwspec.fwnode = domain->parent->fwnode;
 145                 fwspec.param_count = 3;
 146                 fwspec.param[0] = 0;
 147                 fwspec.param[1] = hwirq - 32;
 148                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
 149         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
 150                 fwspec.fwnode = domain->parent->fwnode;
 151                 fwspec.param_count = 2;
 152                 fwspec.param[0] = hwirq;
 153                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
 154         } else {
 155                 return -EINVAL;
 156         }
 157
 158         err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
 159         if (err)
 160                 return err;
 161
 162         /* Configure the interrupt line to be edge */
 163         d = irq_domain_get_irq_data(domain->parent, virq);
 164         d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
 165         return 0;
 166 }
 167
 168 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
 169                                int nr_irqs)
 170 {
 171         spin_lock(&v2m_lock);
 172         bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
 173                               get_count_order(nr_irqs));
 174         spin_unlock(&v2m_lock);
 175 }
 176
 177 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 178                                    unsigned int nr_irqs, void *args)
 179 {
 180         msi_alloc_info_t *info = args;
 181         struct v2m_data *v2m = NULL, *tmp;
 182         int hwirq, offset, i, err = 0;
 183
 184         spin_lock(&v2m_lock);
 185         list_for_each_entry(tmp, &v2m_nodes, entry) {
 186                 offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
 187                                                  get_count_order(nr_irqs));
 188                 if (offset >= 0) {
 189                         v2m = tmp;
 190                         break;
 191                 }
 192         }
 193         spin_unlock(&v2m_lock);
 194
 195         if (!v2m)
 196                 return -ENOSPC;
 197
 198         hwirq = v2m->spi_start + offset;
 199
 200         err = iommu_dma_prepare_msi(info->desc,
 201                                     gicv2m_get_msi_addr(v2m, hwirq));
 202         if (err)
 203                 return err;
 204
 205         for (i = 0; i < nr_irqs; i++) {
 206                 err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
 207                 if (err)
 208                         goto fail;
 209
 210                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 211                                               &gicv2m_irq_chip, v2m);
 212         }
 213
 214         return 0;
 215
 216 fail:
 217         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 218         gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
 219         return err;
 220 }
 221
 222 static void gicv2m_irq_domain_free(struct irq_domain *domain,
 223                                    unsigned int virq, unsigned int nr_irqs)
 224 {
 225         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 226         struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
 227
 228         gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
 229         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 230 }
 231
 232 static const struct irq_domain_ops gicv2m_domain_ops = {
 233         .alloc                  = gicv2m_irq_domain_alloc,
 234         .free                   = gicv2m_irq_domain_free,
 235 };
 236
 237 static bool is_msi_spi_valid(u32 base, u32 num)
 238 {
 239         if (base < V2M_MIN_SPI) {
 240                 pr_err("Invalid MSI base SPI (base:%u)\n", base);
 241                 return false;
 242         }
 243
 244         if ((num == 0) || (base + num > V2M_MAX_SPI)) {
 245                 pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
 246                        num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
 247                 return false;
 248         }
 249
 250         return true;
 251 }
 252
 253 static struct irq_chip gicv2m_pmsi_irq_chip = {
 254         .name                   = "pMSI",
 255 };
 256
 257 static struct msi_domain_ops gicv2m_pmsi_ops = {
 258 };
 259
 260 static struct msi_domain_info gicv2m_pmsi_domain_info = {
 261         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
 262         .ops    = &gicv2m_pmsi_ops,
 263         .chip   = &gicv2m_pmsi_irq_chip,
 264 };
 265
 266 static void gicv2m_teardown(void)
 267 {
 268         struct v2m_data *v2m, *tmp;
 269
 270         list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
 271                 list_del(&v2m->entry);
 272                 bitmap_free(v2m->bm);
 273                 iounmap(v2m->base);
 274                 of_node_put(to_of_node(v2m->fwnode));
 275                 if (is_fwnode_irqchip(v2m->fwnode))
 276                         irq_domain_free_fwnode(v2m->fwnode);
 277                 kfree(v2m);
 278         }
 279 }
 280
 281 static int gicv2m_allocate_domains(struct irq_domain *parent)
 282 {
 283         struct irq_domain *inner_domain, *pci_domain, *plat_domain;
 284         struct v2m_data *v2m;
 285
 286         v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
 287         if (!v2m)
 288                 return 0;
 289
 290         inner_domain = irq_domain_create_tree(v2m->fwnode,
 291                                               &gicv2m_domain_ops, v2m);
 292         if (!inner_domain) {
 293                 pr_err("Failed to create GICv2m domain\n");
 294                 return -ENOMEM;
 295         }
 296
 297         irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
 298         inner_domain->parent = parent;
 299         pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
 300                                                &gicv2m_msi_domain_info,
 301                                                inner_domain);
 302         plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
 303                                                      &gicv2m_pmsi_domain_info,
 304                                                      inner_domain);
 305         if (!pci_domain || !plat_domain) {
 306                 pr_err("Failed to create MSI domains\n");
 307                 if (plat_domain)
 308                         irq_domain_remove(plat_domain);
 309                 if (pci_domain)
 310                         irq_domain_remove(pci_domain);
 311                 irq_domain_remove(inner_domain);
 312                 return -ENOMEM;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
 319                                   u32 spi_start, u32 nr_spis,
 320                                   struct resource *res, u32 flags)
 321 {
 322         int ret;
 323         struct v2m_data *v2m;
 324
 325         v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
 326         if (!v2m)
 327                 return -ENOMEM;
 328
 329         INIT_LIST_HEAD(&v2m->entry);
 330         v2m->fwnode = fwnode;
 331         v2m->flags = flags;
 332
 333         memcpy(&v2m->res, res, sizeof(struct resource));
 334
 335         v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
 336         if (!v2m->base) {
 337                 pr_err("Failed to map GICv2m resource\n");
 338                 ret = -ENOMEM;
 339                 goto err_free_v2m;
 340         }
 341
 342         if (spi_start && nr_spis) {
 343                 v2m->spi_start = spi_start;
 344                 v2m->nr_spis = nr_spis;
 345         } else {
 346                 u32 typer;
 347
 348                 /* Graviton should always have explicit spi_start/nr_spis */
 349                 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) {
 350                         ret = -EINVAL;
 351                         goto err_iounmap;
 352                 }
 353                 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
 354
 355                 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
 356                 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
 357         }
 358
 359         if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
 360                 ret = -EINVAL;
 361                 goto err_iounmap;
 362         }
 363
 364         /*
 365          * APM X-Gene GICv2m implementation has an erratum where
 366          * the MSI data needs to be the offset from the spi_start
 367          * in order to trigger the correct MSI interrupt. This is
 368          * different from the standard GICv2m implementation where
 369          * the MSI data is the absolute value within the range from
 370          * spi_start to (spi_start + num_spis).
 371          *
 372          * Broadcom NS2 GICv2m implementation has an erratum where the MSI data
 373          * is 'spi_number - 32'
 374          *
 375          * Reading that register fails on the Graviton implementation
 376          */
 377         if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) {
 378                 switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
 379                 case XGENE_GICV2M_MSI_IIDR:
 380                         v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
 381                         v2m->spi_offset = v2m->spi_start;
 382                         break;
 383                 case BCM_NS2_GICV2M_MSI_IIDR:
 384                         v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
 385                         v2m->spi_offset = 32;
 386                         break;
 387                 }
 388         }
 389         v2m->bm = bitmap_zalloc(v2m->nr_spis, GFP_KERNEL);
 390         if (!v2m->bm) {
 391                 ret = -ENOMEM;
 392                 goto err_iounmap;
 393         }
 394
 395         list_add_tail(&v2m->entry, &v2m_nodes);
 396
 397         pr_info("range%pR, SPI[%d:%d]\n", res,
 398                 v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
 399         return 0;
 400
 401 err_iounmap:
 402         iounmap(v2m->base);
 403 err_free_v2m:
 404         kfree(v2m);
 405         return ret;
 406 }
 407
 408 static struct of_device_id gicv2m_device_id[] = {
 409         {       .compatible     = "arm,gic-v2m-frame",  },
 410         {},
 411 };
 412
 413 static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
 414                                  struct irq_domain *parent)
 415 {
 416         int ret = 0;
 417         struct device_node *node = to_of_node(parent_handle);
 418         struct device_node *child;
 419
 420         for (child = of_find_matching_node(node, gicv2m_device_id); child;
 421              child = of_find_matching_node(child, gicv2m_device_id)) {
 422                 u32 spi_start = 0, nr_spis = 0;
 423                 struct resource res;
 424
 425                 if (!of_find_property(child, "msi-controller", NULL))
 426                         continue;
 427
 428                 ret = of_address_to_resource(child, 0, &res);
 429                 if (ret) {
 430                         pr_err("Failed to allocate v2m resource.\n");
 431                         break;
 432                 }
 433
 434                 if (!of_property_read_u32(child, "arm,msi-base-spi",
 435                                           &spi_start) &&
 436                     !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
 437                         pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
 438                                 spi_start, nr_spis);
 439
 440                 ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,
 441                                       &res, 0);
 442                 if (ret) {
 443                         of_node_put(child);
 444                         break;
 445                 }
 446         }
 447
 448         if (!ret)
 449                 ret = gicv2m_allocate_domains(parent);
 450         if (ret)
 451                 gicv2m_teardown();
 452         return ret;
 453 }
 454
 455 #ifdef CONFIG_ACPI
 456 static int acpi_num_msi;
 457
 458 static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
 459 {
 460         struct v2m_data *data;
 461
 462         if (WARN_ON(acpi_num_msi <= 0))
 463                 return NULL;
 464
 465         /* We only return the fwnode of the first MSI frame. */
 466         data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
 467         if (!data)
 468                 return NULL;
 469
 470         return data->fwnode;
 471 }
 472
 473 static bool acpi_check_amazon_graviton_quirks(void)
 474 {
 475         static struct acpi_table_madt *madt;
 476         acpi_status status;
 477         bool rc = false;
 478
 479 #define ACPI_AMZN_OEM_ID                "AMAZON"
 480
 481         status = acpi_get_table(ACPI_SIG_MADT, 0,
 482                                 (struct acpi_table_header **)&madt);
 483
 484         if (ACPI_FAILURE(status) || !madt)
 485                 return rc;
 486         rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE);
 487         acpi_put_table((struct acpi_table_header *)madt);
 488
 489         return rc;
 490 }
 491
 492 static int __init
 493 acpi_parse_madt_msi(union acpi_subtable_headers *header,
 494                     const unsigned long end)
 495 {
 496         int ret;
 497         struct resource res;
 498         u32 spi_start = 0, nr_spis = 0;
 499         struct acpi_madt_generic_msi_frame *m;
 500         struct fwnode_handle *fwnode;
 501         u32 flags = 0;
 502
 503         m = (struct acpi_madt_generic_msi_frame *)header;
 504         if (BAD_MADT_ENTRY(m, end))
 505                 return -EINVAL;
 506
 507         res.start = m->base_address;
 508         res.end = m->base_address + SZ_4K - 1;
 509         res.flags = IORESOURCE_MEM;
 510
 511         if (acpi_check_amazon_graviton_quirks()) {
 512                 pr_info("applying Amazon Graviton quirk\n");
 513                 res.end = res.start + SZ_8K - 1;
 514                 flags |= GICV2M_GRAVITON_ADDRESS_ONLY;
 515                 gicv2m_msi_domain_info.flags &= ~MSI_FLAG_MULTI_PCI_MSI;
 516         }
 517
 518         if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
 519                 spi_start = m->spi_base;
 520                 nr_spis = m->spi_count;
 521
 522                 pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
 523                         spi_start, nr_spis);
 524         }
 525
 526         fwnode = irq_domain_alloc_fwnode(&res.start);
 527         if (!fwnode) {
 528                 pr_err("Unable to allocate GICv2m domain token\n");
 529                 return -EINVAL;
 530         }
 531
 532         ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res, flags);
 533         if (ret)
 534                 irq_domain_free_fwnode(fwnode);
 535
 536         return ret;
 537 }
 538
 539 static int __init gicv2m_acpi_init(struct irq_domain *parent)
 540 {
 541         int ret;
 542
 543         if (acpi_num_msi > 0)
 544                 return 0;
 545
 546         acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
 547                                       acpi_parse_madt_msi, 0);
 548
 549         if (acpi_num_msi <= 0)
 550                 goto err_out;
 551
 552         ret = gicv2m_allocate_domains(parent);
 553         if (ret)
 554                 goto err_out;
 555
 556         pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
 557
 558         return 0;
 559
 560 err_out:
 561         gicv2m_teardown();
 562         return -EINVAL;
 563 }
 564 #else /* CONFIG_ACPI */
 565 static int __init gicv2m_acpi_init(struct irq_domain *parent)
 566 {
 567         return -EINVAL;
 568 }
 569 #endif /* CONFIG_ACPI */
 570
 571 int __init gicv2m_init(struct fwnode_handle *parent_handle,
 572                        struct irq_domain *parent)
 573 {
 574         if (is_of_node(parent_handle))
 575                 return gicv2m_of_init(parent_handle, parent);
 576
 577         return gicv2m_acpi_init(parent);
 578 }