drivers/irqchip/irq-gic-v2m.c

   1 /*
   2  * ARM GIC v2m MSI(-X) support
   3  * Support for Message Signaled Interrupts for systems that
   4  * implement ARM Generic Interrupt Controller: GICv2m.
   5  *
   6  * Copyright (C) 2014 Advanced Micro Devices, Inc.
   7  * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
   8  *          Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
   9  *          Brandon Anderson <brandon.anderson@amd.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published
  13  * by the Free Software Foundation.
  14  */
  15
  16 #define pr_fmt(fmt) "GICv2m: " fmt
  17
  18 #include <linux/acpi.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/kernel.h>
  22 #include <linux/msi.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27
  28 /*
  29 * MSI_TYPER:
  30 *     [31:26] Reserved
  31 *     [25:16] lowest SPI assigned to MSI
  32 *     [15:10] Reserved
  33 *     [9:0]   Numer of SPIs assigned to MSI
  34 */
  35 #define V2M_MSI_TYPER                  0x008
  36 #define V2M_MSI_TYPER_BASE_SHIFT       16
  37 #define V2M_MSI_TYPER_BASE_MASK        0x3FF
  38 #define V2M_MSI_TYPER_NUM_MASK         0x3FF
  39 #define V2M_MSI_SETSPI_NS              0x040
  40 #define V2M_MIN_SPI                    32
  41 #define V2M_MAX_SPI                    1019
  42 #define V2M_MSI_IIDR                   0xFCC
  43
  44 #define V2M_MSI_TYPER_BASE_SPI(x)      \
  45                (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
  46
  47 #define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)
  48
  49 /* APM X-Gene with GICv2m MSI_IIDR register value */
  50 #define XGENE_GICV2M_MSI_IIDR           0x06000170
  51
  52 /* List of flags for specific v2m implementation */
  53 #define GICV2M_NEEDS_SPI_OFFSET         0x00000001
  54
  55 static LIST_HEAD(v2m_nodes);
  56 static DEFINE_SPINLOCK(v2m_lock);
  57
  58 struct v2m_data {
  59         struct list_head entry;
  60         struct fwnode_handle *fwnode;
  61         struct resource res;    /* GICv2m resource */
  62         void __iomem *base;     /* GICv2m virt address */
  63         u32 spi_start;          /* The SPI number that MSIs start */
  64         u32 nr_spis;            /* The number of SPIs for MSIs */
  65         unsigned long *bm;      /* MSI vector bitmap */
  66         u32 flags;              /* v2m flags for specific implementation */
  67 };
  68
  69 static void gicv2m_mask_msi_irq(struct irq_data *d)
  70 {
  71         pci_msi_mask_irq(d);
  72         irq_chip_mask_parent(d);
  73 }
  74
  75 static void gicv2m_unmask_msi_irq(struct irq_data *d)
  76 {
  77         pci_msi_unmask_irq(d);
  78         irq_chip_unmask_parent(d);
  79 }
  80
  81 static struct irq_chip gicv2m_msi_irq_chip = {
  82         .name                   = "MSI",
  83         .irq_mask               = gicv2m_mask_msi_irq,
  84         .irq_unmask             = gicv2m_unmask_msi_irq,
  85         .irq_eoi                = irq_chip_eoi_parent,
  86         .irq_write_msi_msg      = pci_msi_domain_write_msg,
  87 };
  88
  89 static struct msi_domain_info gicv2m_msi_domain_info = {
  90         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  91                    MSI_FLAG_PCI_MSIX),
  92         .chip   = &gicv2m_msi_irq_chip,
  93 };
  94
  95 static int gicv2m_set_affinity(struct irq_data *irq_data,
  96                                const struct cpumask *mask, bool force)
  97 {
  98         int ret;
  99
 100         ret = irq_chip_set_affinity_parent(irq_data, mask, force);
 101         if (ret == IRQ_SET_MASK_OK)
 102                 ret = IRQ_SET_MASK_OK_DONE;
 103
 104         return ret;
 105 }
 106
 107 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 108 {
 109         struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
 110         phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
 111
 112         msg->address_hi = upper_32_bits(addr);
 113         msg->address_lo = lower_32_bits(addr);
 114         msg->data = data->hwirq;
 115
 116         if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
 117                 msg->data -= v2m->spi_start;
 118 }
 119
 120 static struct irq_chip gicv2m_irq_chip = {
 121         .name                   = "GICv2m",
 122         .irq_mask               = irq_chip_mask_parent,
 123         .irq_unmask             = irq_chip_unmask_parent,
 124         .irq_eoi                = irq_chip_eoi_parent,
 125         .irq_set_affinity       = gicv2m_set_affinity,
 126         .irq_compose_msi_msg    = gicv2m_compose_msi_msg,
 127 };
 128
 129 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
 130                                        unsigned int virq,
 131                                        irq_hw_number_t hwirq)
 132 {
 133         struct irq_fwspec fwspec;
 134         struct irq_data *d;
 135         int err;
 136
 137         if (is_of_node(domain->parent->fwnode)) {
 138                 fwspec.fwnode = domain->parent->fwnode;
 139                 fwspec.param_count = 3;
 140                 fwspec.param[0] = 0;
 141                 fwspec.param[1] = hwirq - 32;
 142                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
 143         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
 144                 fwspec.fwnode = domain->parent->fwnode;
 145                 fwspec.param_count = 2;
 146                 fwspec.param[0] = hwirq;
 147                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
 148         } else {
 149                 return -EINVAL;
 150         }
 151
 152         err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
 153         if (err)
 154                 return err;
 155
 156         /* Configure the interrupt line to be edge */
 157         d = irq_domain_get_irq_data(domain->parent, virq);
 158         d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
 159         return 0;
 160 }
 161
 162 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
 163 {
 164         int pos;
 165
 166         pos = hwirq - v2m->spi_start;
 167         if (pos < 0 || pos >= v2m->nr_spis) {
 168                 pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
 169                 return;
 170         }
 171
 172         spin_lock(&v2m_lock);
 173         __clear_bit(pos, v2m->bm);
 174         spin_unlock(&v2m_lock);
 175 }
 176
 177 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 178                                    unsigned int nr_irqs, void *args)
 179 {
 180         struct v2m_data *v2m = NULL, *tmp;
 181         int hwirq, offset, err = 0;
 182
 183         spin_lock(&v2m_lock);
 184         list_for_each_entry(tmp, &v2m_nodes, entry) {
 185                 offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
 186                 if (offset < tmp->nr_spis) {
 187                         __set_bit(offset, tmp->bm);
 188                         v2m = tmp;
 189                         break;
 190                 }
 191         }
 192         spin_unlock(&v2m_lock);
 193
 194         if (!v2m)
 195                 return -ENOSPC;
 196
 197         hwirq = v2m->spi_start + offset;
 198
 199         err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
 200         if (err) {
 201                 gicv2m_unalloc_msi(v2m, hwirq);
 202                 return err;
 203         }
 204
 205         irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 206                                       &gicv2m_irq_chip, v2m);
 207
 208         return 0;
 209 }
 210
 211 static void gicv2m_irq_domain_free(struct irq_domain *domain,
 212                                    unsigned int virq, unsigned int nr_irqs)
 213 {
 214         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 215         struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
 216
 217         BUG_ON(nr_irqs != 1);
 218         gicv2m_unalloc_msi(v2m, d->hwirq);
 219         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 220 }
 221
 222 static const struct irq_domain_ops gicv2m_domain_ops = {
 223         .alloc                  = gicv2m_irq_domain_alloc,
 224         .free                   = gicv2m_irq_domain_free,
 225 };
 226
 227 static bool is_msi_spi_valid(u32 base, u32 num)
 228 {
 229         if (base < V2M_MIN_SPI) {
 230                 pr_err("Invalid MSI base SPI (base:%u)\n", base);
 231                 return false;
 232         }
 233
 234         if ((num == 0) || (base + num > V2M_MAX_SPI)) {
 235                 pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
 236                        num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
 237                 return false;
 238         }
 239
 240         return true;
 241 }
 242
 243 static struct irq_chip gicv2m_pmsi_irq_chip = {
 244         .name                   = "pMSI",
 245 };
 246
 247 static struct msi_domain_ops gicv2m_pmsi_ops = {
 248 };
 249
 250 static struct msi_domain_info gicv2m_pmsi_domain_info = {
 251         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
 252         .ops    = &gicv2m_pmsi_ops,
 253         .chip   = &gicv2m_pmsi_irq_chip,
 254 };
 255
 256 static void gicv2m_teardown(void)
 257 {
 258         struct v2m_data *v2m, *tmp;
 259
 260         list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
 261                 list_del(&v2m->entry);
 262                 kfree(v2m->bm);
 263                 iounmap(v2m->base);
 264                 of_node_put(to_of_node(v2m->fwnode));
 265                 if (is_fwnode_irqchip(v2m->fwnode))
 266                         irq_domain_free_fwnode(v2m->fwnode);
 267                 kfree(v2m);
 268         }
 269 }
 270
 271 static int gicv2m_allocate_domains(struct irq_domain *parent)
 272 {
 273         struct irq_domain *inner_domain, *pci_domain, *plat_domain;
 274         struct v2m_data *v2m;
 275
 276         v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
 277         if (!v2m)
 278                 return 0;
 279
 280         inner_domain = irq_domain_create_tree(v2m->fwnode,
 281                                               &gicv2m_domain_ops, v2m);
 282         if (!inner_domain) {
 283                 pr_err("Failed to create GICv2m domain\n");
 284                 return -ENOMEM;
 285         }
 286
 287         inner_domain->bus_token = DOMAIN_BUS_NEXUS;
 288         inner_domain->parent = parent;
 289         pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
 290                                                &gicv2m_msi_domain_info,
 291                                                inner_domain);
 292         plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
 293                                                      &gicv2m_pmsi_domain_info,
 294                                                      inner_domain);
 295         if (!pci_domain || !plat_domain) {
 296                 pr_err("Failed to create MSI domains\n");
 297                 if (plat_domain)
 298                         irq_domain_remove(plat_domain);
 299                 if (pci_domain)
 300                         irq_domain_remove(pci_domain);
 301                 irq_domain_remove(inner_domain);
 302                 return -ENOMEM;
 303         }
 304
 305         return 0;
 306 }
 307
 308 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
 309                                   u32 spi_start, u32 nr_spis,
 310                                   struct resource *res)
 311 {
 312         int ret;
 313         struct v2m_data *v2m;
 314
 315         v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
 316         if (!v2m) {
 317                 pr_err("Failed to allocate struct v2m_data.\n");
 318                 return -ENOMEM;
 319         }
 320
 321         INIT_LIST_HEAD(&v2m->entry);
 322         v2m->fwnode = fwnode;
 323
 324         memcpy(&v2m->res, res, sizeof(struct resource));
 325
 326         v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
 327         if (!v2m->base) {
 328                 pr_err("Failed to map GICv2m resource\n");
 329                 ret = -ENOMEM;
 330                 goto err_free_v2m;
 331         }
 332
 333         if (spi_start && nr_spis) {
 334                 v2m->spi_start = spi_start;
 335                 v2m->nr_spis = nr_spis;
 336         } else {
 337                 u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
 338
 339                 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
 340                 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
 341         }
 342
 343         if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
 344                 ret = -EINVAL;
 345                 goto err_iounmap;
 346         }
 347
 348         /*
 349          * APM X-Gene GICv2m implementation has an erratum where
 350          * the MSI data needs to be the offset from the spi_start
 351          * in order to trigger the correct MSI interrupt. This is
 352          * different from the standard GICv2m implementation where
 353          * the MSI data is the absolute value within the range from
 354          * spi_start to (spi_start + num_spis).
 355          */
 356         if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR)
 357                 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
 358
 359         v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
 360                           GFP_KERNEL);
 361         if (!v2m->bm) {
 362                 ret = -ENOMEM;
 363                 goto err_iounmap;
 364         }
 365
 366         list_add_tail(&v2m->entry, &v2m_nodes);
 367
 368         pr_info("range%pR, SPI[%d:%d]\n", res,
 369                 v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
 370         return 0;
 371
 372 err_iounmap:
 373         iounmap(v2m->base);
 374 err_free_v2m:
 375         kfree(v2m);
 376         return ret;
 377 }
 378
 379 static struct of_device_id gicv2m_device_id[] = {
 380         {       .compatible     = "arm,gic-v2m-frame",  },
 381         {},
 382 };
 383
 384 static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
 385                                  struct irq_domain *parent)
 386 {
 387         int ret = 0;
 388         struct device_node *node = to_of_node(parent_handle);
 389         struct device_node *child;
 390
 391         for (child = of_find_matching_node(node, gicv2m_device_id); child;
 392              child = of_find_matching_node(child, gicv2m_device_id)) {
 393                 u32 spi_start = 0, nr_spis = 0;
 394                 struct resource res;
 395
 396                 if (!of_find_property(child, "msi-controller", NULL))
 397                         continue;
 398
 399                 ret = of_address_to_resource(child, 0, &res);
 400                 if (ret) {
 401                         pr_err("Failed to allocate v2m resource.\n");
 402                         break;
 403                 }
 404
 405                 if (!of_property_read_u32(child, "arm,msi-base-spi",
 406                                           &spi_start) &&
 407                     !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
 408                         pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
 409                                 spi_start, nr_spis);
 410
 411                 ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
 412                 if (ret) {
 413                         of_node_put(child);
 414                         break;
 415                 }
 416         }
 417
 418         if (!ret)
 419                 ret = gicv2m_allocate_domains(parent);
 420         if (ret)
 421                 gicv2m_teardown();
 422         return ret;
 423 }
 424
 425 #ifdef CONFIG_ACPI
 426 static int acpi_num_msi;
 427
 428 static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
 429 {
 430         struct v2m_data *data;
 431
 432         if (WARN_ON(acpi_num_msi <= 0))
 433                 return NULL;
 434
 435         /* We only return the fwnode of the first MSI frame. */
 436         data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
 437         if (!data)
 438                 return NULL;
 439
 440         return data->fwnode;
 441 }
 442
 443 static int __init
 444 acpi_parse_madt_msi(struct acpi_subtable_header *header,
 445                     const unsigned long end)
 446 {
 447         int ret;
 448         struct resource res;
 449         u32 spi_start = 0, nr_spis = 0;
 450         struct acpi_madt_generic_msi_frame *m;
 451         struct fwnode_handle *fwnode;
 452
 453         m = (struct acpi_madt_generic_msi_frame *)header;
 454         if (BAD_MADT_ENTRY(m, end))
 455                 return -EINVAL;
 456
 457         res.start = m->base_address;
 458         res.end = m->base_address + SZ_4K - 1;
 459         res.flags = IORESOURCE_MEM;
 460
 461         if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
 462                 spi_start = m->spi_base;
 463                 nr_spis = m->spi_count;
 464
 465                 pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
 466                         spi_start, nr_spis);
 467         }
 468
 469         fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
 470         if (!fwnode) {
 471                 pr_err("Unable to allocate GICv2m domain token\n");
 472                 return -EINVAL;
 473         }
 474
 475         ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
 476         if (ret)
 477                 irq_domain_free_fwnode(fwnode);
 478
 479         return ret;
 480 }
 481
 482 static int __init gicv2m_acpi_init(struct irq_domain *parent)
 483 {
 484         int ret;
 485
 486         if (acpi_num_msi > 0)
 487                 return 0;
 488
 489         acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
 490                                       acpi_parse_madt_msi, 0);
 491
 492         if (acpi_num_msi <= 0)
 493                 goto err_out;
 494
 495         ret = gicv2m_allocate_domains(parent);
 496         if (ret)
 497                 goto err_out;
 498
 499         pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
 500
 501         return 0;
 502
 503 err_out:
 504         gicv2m_teardown();
 505         return -EINVAL;
 506 }
 507 #else /* CONFIG_ACPI */
 508 static int __init gicv2m_acpi_init(struct irq_domain *parent)
 509 {
 510         return -EINVAL;
 511 }
 512 #endif /* CONFIG_ACPI */
 513
 514 int __init gicv2m_init(struct fwnode_handle *parent_handle,
 515                        struct irq_domain *parent)
 516 {
 517         if (is_of_node(parent_handle))
 518                 return gicv2m_of_init(parent_handle, parent);
 519
 520         return gicv2m_acpi_init(parent);
 521 }