2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/acpi.h>
19 #include <linux/bitmap.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/irqdomain.h>
24 #include <linux/acpi_iort.h>
25 #include <linux/log2.h>
27 #include <linux/msi.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_pci.h>
32 #include <linux/of_platform.h>
33 #include <linux/percpu.h>
34 #include <linux/slab.h>
36 #include <linux/irqchip.h>
37 #include <linux/irqchip/arm-gic-v3.h>
39 #include <asm/cacheflush.h>
40 #include <asm/cputype.h>
41 #include <asm/exception.h>
43 #include "irq-gic-common.h"
45 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
46 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
47 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
49 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
52 * Collection structure - just an ID, and a redistributor address to
53 * ping. We use one per CPU as a bag of interrupts assigned to this
56 struct its_collection
{
62 * The ITS_BASER structure - contains memory information, cached
63 * value of BASER register configuration and ITS page size.
73 * The ITS structure - contains most of the infrastructure, with the
74 * top-level MSI domain, the command queue, the collections, and the
75 * list of devices writing to it.
79 struct list_head entry
;
81 phys_addr_t phys_base
;
82 struct its_cmd_block
*cmd_base
;
83 struct its_cmd_block
*cmd_write
;
84 struct its_baser tables
[GITS_BASER_NR_REGS
];
85 struct its_collection
*collections
;
86 struct list_head its_device_list
;
93 #define ITS_ITT_ALIGN SZ_256
95 /* Convert page order to size in bytes */
96 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
98 struct event_lpi_map
{
99 unsigned long *lpi_map
;
101 irq_hw_number_t lpi_base
;
106 * The ITS view of a device - belongs to an ITS, a collection, owns an
107 * interrupt translation table, and a list of interrupts.
110 struct list_head entry
;
111 struct its_node
*its
;
112 struct event_lpi_map event_map
;
118 static LIST_HEAD(its_nodes
);
119 static DEFINE_SPINLOCK(its_lock
);
120 static struct rdists
*gic_rdists
;
121 static struct irq_domain
*its_parent
;
123 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
124 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
126 static struct its_collection
*dev_event_to_col(struct its_device
*its_dev
,
129 struct its_node
*its
= its_dev
->its
;
131 return its
->collections
+ its_dev
->event_map
.col_map
[event
];
135 * ITS command descriptors - parameters to be encoded in a command
138 struct its_cmd_desc
{
141 struct its_device
*dev
;
146 struct its_device
*dev
;
151 struct its_device
*dev
;
156 struct its_collection
*col
;
161 struct its_device
*dev
;
167 struct its_device
*dev
;
168 struct its_collection
*col
;
173 struct its_device
*dev
;
178 struct its_collection
*col
;
184 * The ITS command block, which is what the ITS actually parses.
186 struct its_cmd_block
{
190 #define ITS_CMD_QUEUE_SZ SZ_64K
191 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
193 typedef struct its_collection
*(*its_cmd_builder_t
)(struct its_cmd_block
*,
194 struct its_cmd_desc
*);
196 static void its_encode_cmd(struct its_cmd_block
*cmd
, u8 cmd_nr
)
198 cmd
->raw_cmd
[0] &= ~0xffUL
;
199 cmd
->raw_cmd
[0] |= cmd_nr
;
202 static void its_encode_devid(struct its_cmd_block
*cmd
, u32 devid
)
204 cmd
->raw_cmd
[0] &= BIT_ULL(32) - 1;
205 cmd
->raw_cmd
[0] |= ((u64
)devid
) << 32;
208 static void its_encode_event_id(struct its_cmd_block
*cmd
, u32 id
)
210 cmd
->raw_cmd
[1] &= ~0xffffffffUL
;
211 cmd
->raw_cmd
[1] |= id
;
214 static void its_encode_phys_id(struct its_cmd_block
*cmd
, u32 phys_id
)
216 cmd
->raw_cmd
[1] &= 0xffffffffUL
;
217 cmd
->raw_cmd
[1] |= ((u64
)phys_id
) << 32;
220 static void its_encode_size(struct its_cmd_block
*cmd
, u8 size
)
222 cmd
->raw_cmd
[1] &= ~0x1fUL
;
223 cmd
->raw_cmd
[1] |= size
& 0x1f;
226 static void its_encode_itt(struct its_cmd_block
*cmd
, u64 itt_addr
)
228 cmd
->raw_cmd
[2] &= ~0xffffffffffffUL
;
229 cmd
->raw_cmd
[2] |= itt_addr
& 0xffffffffff00UL
;
232 static void its_encode_valid(struct its_cmd_block
*cmd
, int valid
)
234 cmd
->raw_cmd
[2] &= ~(1UL << 63);
235 cmd
->raw_cmd
[2] |= ((u64
)!!valid
) << 63;
238 static void its_encode_target(struct its_cmd_block
*cmd
, u64 target_addr
)
240 cmd
->raw_cmd
[2] &= ~(0xffffffffUL
<< 16);
241 cmd
->raw_cmd
[2] |= (target_addr
& (0xffffffffUL
<< 16));
244 static void its_encode_collection(struct its_cmd_block
*cmd
, u16 col
)
246 cmd
->raw_cmd
[2] &= ~0xffffUL
;
247 cmd
->raw_cmd
[2] |= col
;
250 static inline void its_fixup_cmd(struct its_cmd_block
*cmd
)
252 /* Let's fixup BE commands */
253 cmd
->raw_cmd
[0] = cpu_to_le64(cmd
->raw_cmd
[0]);
254 cmd
->raw_cmd
[1] = cpu_to_le64(cmd
->raw_cmd
[1]);
255 cmd
->raw_cmd
[2] = cpu_to_le64(cmd
->raw_cmd
[2]);
256 cmd
->raw_cmd
[3] = cpu_to_le64(cmd
->raw_cmd
[3]);
259 static struct its_collection
*its_build_mapd_cmd(struct its_cmd_block
*cmd
,
260 struct its_cmd_desc
*desc
)
262 unsigned long itt_addr
;
263 u8 size
= ilog2(desc
->its_mapd_cmd
.dev
->nr_ites
);
265 itt_addr
= virt_to_phys(desc
->its_mapd_cmd
.dev
->itt
);
266 itt_addr
= ALIGN(itt_addr
, ITS_ITT_ALIGN
);
268 its_encode_cmd(cmd
, GITS_CMD_MAPD
);
269 its_encode_devid(cmd
, desc
->its_mapd_cmd
.dev
->device_id
);
270 its_encode_size(cmd
, size
- 1);
271 its_encode_itt(cmd
, itt_addr
);
272 its_encode_valid(cmd
, desc
->its_mapd_cmd
.valid
);
279 static struct its_collection
*its_build_mapc_cmd(struct its_cmd_block
*cmd
,
280 struct its_cmd_desc
*desc
)
282 its_encode_cmd(cmd
, GITS_CMD_MAPC
);
283 its_encode_collection(cmd
, desc
->its_mapc_cmd
.col
->col_id
);
284 its_encode_target(cmd
, desc
->its_mapc_cmd
.col
->target_address
);
285 its_encode_valid(cmd
, desc
->its_mapc_cmd
.valid
);
289 return desc
->its_mapc_cmd
.col
;
292 static struct its_collection
*its_build_mapvi_cmd(struct its_cmd_block
*cmd
,
293 struct its_cmd_desc
*desc
)
295 struct its_collection
*col
;
297 col
= dev_event_to_col(desc
->its_mapvi_cmd
.dev
,
298 desc
->its_mapvi_cmd
.event_id
);
300 its_encode_cmd(cmd
, GITS_CMD_MAPVI
);
301 its_encode_devid(cmd
, desc
->its_mapvi_cmd
.dev
->device_id
);
302 its_encode_event_id(cmd
, desc
->its_mapvi_cmd
.event_id
);
303 its_encode_phys_id(cmd
, desc
->its_mapvi_cmd
.phys_id
);
304 its_encode_collection(cmd
, col
->col_id
);
311 static struct its_collection
*its_build_movi_cmd(struct its_cmd_block
*cmd
,
312 struct its_cmd_desc
*desc
)
314 struct its_collection
*col
;
316 col
= dev_event_to_col(desc
->its_movi_cmd
.dev
,
317 desc
->its_movi_cmd
.event_id
);
319 its_encode_cmd(cmd
, GITS_CMD_MOVI
);
320 its_encode_devid(cmd
, desc
->its_movi_cmd
.dev
->device_id
);
321 its_encode_event_id(cmd
, desc
->its_movi_cmd
.event_id
);
322 its_encode_collection(cmd
, desc
->its_movi_cmd
.col
->col_id
);
329 static struct its_collection
*its_build_discard_cmd(struct its_cmd_block
*cmd
,
330 struct its_cmd_desc
*desc
)
332 struct its_collection
*col
;
334 col
= dev_event_to_col(desc
->its_discard_cmd
.dev
,
335 desc
->its_discard_cmd
.event_id
);
337 its_encode_cmd(cmd
, GITS_CMD_DISCARD
);
338 its_encode_devid(cmd
, desc
->its_discard_cmd
.dev
->device_id
);
339 its_encode_event_id(cmd
, desc
->its_discard_cmd
.event_id
);
346 static struct its_collection
*its_build_inv_cmd(struct its_cmd_block
*cmd
,
347 struct its_cmd_desc
*desc
)
349 struct its_collection
*col
;
351 col
= dev_event_to_col(desc
->its_inv_cmd
.dev
,
352 desc
->its_inv_cmd
.event_id
);
354 its_encode_cmd(cmd
, GITS_CMD_INV
);
355 its_encode_devid(cmd
, desc
->its_inv_cmd
.dev
->device_id
);
356 its_encode_event_id(cmd
, desc
->its_inv_cmd
.event_id
);
363 static struct its_collection
*its_build_invall_cmd(struct its_cmd_block
*cmd
,
364 struct its_cmd_desc
*desc
)
366 its_encode_cmd(cmd
, GITS_CMD_INVALL
);
367 its_encode_collection(cmd
, desc
->its_mapc_cmd
.col
->col_id
);
374 static u64
its_cmd_ptr_to_offset(struct its_node
*its
,
375 struct its_cmd_block
*ptr
)
377 return (ptr
- its
->cmd_base
) * sizeof(*ptr
);
380 static int its_queue_full(struct its_node
*its
)
385 widx
= its
->cmd_write
- its
->cmd_base
;
386 ridx
= readl_relaxed(its
->base
+ GITS_CREADR
) / sizeof(struct its_cmd_block
);
388 /* This is incredibly unlikely to happen, unless the ITS locks up. */
389 if (((widx
+ 1) % ITS_CMD_QUEUE_NR_ENTRIES
) == ridx
)
395 static struct its_cmd_block
*its_allocate_entry(struct its_node
*its
)
397 struct its_cmd_block
*cmd
;
398 u32 count
= 1000000; /* 1s! */
400 while (its_queue_full(its
)) {
403 pr_err_ratelimited("ITS queue not draining\n");
410 cmd
= its
->cmd_write
++;
412 /* Handle queue wrapping */
413 if (its
->cmd_write
== (its
->cmd_base
+ ITS_CMD_QUEUE_NR_ENTRIES
))
414 its
->cmd_write
= its
->cmd_base
;
419 static struct its_cmd_block
*its_post_commands(struct its_node
*its
)
421 u64 wr
= its_cmd_ptr_to_offset(its
, its
->cmd_write
);
423 writel_relaxed(wr
, its
->base
+ GITS_CWRITER
);
425 return its
->cmd_write
;
428 static void its_flush_cmd(struct its_node
*its
, struct its_cmd_block
*cmd
)
431 * Make sure the commands written to memory are observable by
434 if (its
->flags
& ITS_FLAGS_CMDQ_NEEDS_FLUSHING
)
435 __flush_dcache_area(cmd
, sizeof(*cmd
));
440 static void its_wait_for_range_completion(struct its_node
*its
,
441 struct its_cmd_block
*from
,
442 struct its_cmd_block
*to
)
444 u64 rd_idx
, from_idx
, to_idx
;
445 u32 count
= 1000000; /* 1s! */
447 from_idx
= its_cmd_ptr_to_offset(its
, from
);
448 to_idx
= its_cmd_ptr_to_offset(its
, to
);
451 rd_idx
= readl_relaxed(its
->base
+ GITS_CREADR
);
452 if (rd_idx
>= to_idx
|| rd_idx
< from_idx
)
457 pr_err_ratelimited("ITS queue timeout\n");
465 static void its_send_single_command(struct its_node
*its
,
466 its_cmd_builder_t builder
,
467 struct its_cmd_desc
*desc
)
469 struct its_cmd_block
*cmd
, *sync_cmd
, *next_cmd
;
470 struct its_collection
*sync_col
;
473 raw_spin_lock_irqsave(&its
->lock
, flags
);
475 cmd
= its_allocate_entry(its
);
476 if (!cmd
) { /* We're soooooo screewed... */
477 pr_err_ratelimited("ITS can't allocate, dropping command\n");
478 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
481 sync_col
= builder(cmd
, desc
);
482 its_flush_cmd(its
, cmd
);
485 sync_cmd
= its_allocate_entry(its
);
487 pr_err_ratelimited("ITS can't SYNC, skipping\n");
490 its_encode_cmd(sync_cmd
, GITS_CMD_SYNC
);
491 its_encode_target(sync_cmd
, sync_col
->target_address
);
492 its_fixup_cmd(sync_cmd
);
493 its_flush_cmd(its
, sync_cmd
);
497 next_cmd
= its_post_commands(its
);
498 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
500 its_wait_for_range_completion(its
, cmd
, next_cmd
);
503 static void its_send_inv(struct its_device
*dev
, u32 event_id
)
505 struct its_cmd_desc desc
;
507 desc
.its_inv_cmd
.dev
= dev
;
508 desc
.its_inv_cmd
.event_id
= event_id
;
510 its_send_single_command(dev
->its
, its_build_inv_cmd
, &desc
);
513 static void its_send_mapd(struct its_device
*dev
, int valid
)
515 struct its_cmd_desc desc
;
517 desc
.its_mapd_cmd
.dev
= dev
;
518 desc
.its_mapd_cmd
.valid
= !!valid
;
520 its_send_single_command(dev
->its
, its_build_mapd_cmd
, &desc
);
523 static void its_send_mapc(struct its_node
*its
, struct its_collection
*col
,
526 struct its_cmd_desc desc
;
528 desc
.its_mapc_cmd
.col
= col
;
529 desc
.its_mapc_cmd
.valid
= !!valid
;
531 its_send_single_command(its
, its_build_mapc_cmd
, &desc
);
534 static void its_send_mapvi(struct its_device
*dev
, u32 irq_id
, u32 id
)
536 struct its_cmd_desc desc
;
538 desc
.its_mapvi_cmd
.dev
= dev
;
539 desc
.its_mapvi_cmd
.phys_id
= irq_id
;
540 desc
.its_mapvi_cmd
.event_id
= id
;
542 its_send_single_command(dev
->its
, its_build_mapvi_cmd
, &desc
);
545 static void its_send_movi(struct its_device
*dev
,
546 struct its_collection
*col
, u32 id
)
548 struct its_cmd_desc desc
;
550 desc
.its_movi_cmd
.dev
= dev
;
551 desc
.its_movi_cmd
.col
= col
;
552 desc
.its_movi_cmd
.event_id
= id
;
554 its_send_single_command(dev
->its
, its_build_movi_cmd
, &desc
);
557 static void its_send_discard(struct its_device
*dev
, u32 id
)
559 struct its_cmd_desc desc
;
561 desc
.its_discard_cmd
.dev
= dev
;
562 desc
.its_discard_cmd
.event_id
= id
;
564 its_send_single_command(dev
->its
, its_build_discard_cmd
, &desc
);
567 static void its_send_invall(struct its_node
*its
, struct its_collection
*col
)
569 struct its_cmd_desc desc
;
571 desc
.its_invall_cmd
.col
= col
;
573 its_send_single_command(its
, its_build_invall_cmd
, &desc
);
577 * irqchip functions - assumes MSI, mostly.
580 static inline u32
its_get_event_id(struct irq_data
*d
)
582 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
583 return d
->hwirq
- its_dev
->event_map
.lpi_base
;
586 static void lpi_set_config(struct irq_data
*d
, bool enable
)
588 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
589 irq_hw_number_t hwirq
= d
->hwirq
;
590 u32 id
= its_get_event_id(d
);
591 u8
*cfg
= page_address(gic_rdists
->prop_page
) + hwirq
- 8192;
594 *cfg
|= LPI_PROP_ENABLED
;
596 *cfg
&= ~LPI_PROP_ENABLED
;
599 * Make the above write visible to the redistributors.
600 * And yes, we're flushing exactly: One. Single. Byte.
603 if (gic_rdists
->flags
& RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING
)
604 __flush_dcache_area(cfg
, sizeof(*cfg
));
607 its_send_inv(its_dev
, id
);
610 static void its_mask_irq(struct irq_data
*d
)
612 lpi_set_config(d
, false);
615 static void its_unmask_irq(struct irq_data
*d
)
617 lpi_set_config(d
, true);
620 static int its_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
624 const struct cpumask
*cpu_mask
= cpu_online_mask
;
625 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
626 struct its_collection
*target_col
;
627 u32 id
= its_get_event_id(d
);
629 /* lpi cannot be routed to a redistributor that is on a foreign node */
630 if (its_dev
->its
->flags
& ITS_FLAGS_WORKAROUND_CAVIUM_23144
) {
631 if (its_dev
->its
->numa_node
>= 0) {
632 cpu_mask
= cpumask_of_node(its_dev
->its
->numa_node
);
633 if (!cpumask_intersects(mask_val
, cpu_mask
))
638 cpu
= cpumask_any_and(mask_val
, cpu_mask
);
640 if (cpu
>= nr_cpu_ids
)
643 target_col
= &its_dev
->its
->collections
[cpu
];
644 its_send_movi(its_dev
, target_col
, id
);
645 its_dev
->event_map
.col_map
[id
] = cpu
;
647 return IRQ_SET_MASK_OK_DONE
;
650 static void its_irq_compose_msi_msg(struct irq_data
*d
, struct msi_msg
*msg
)
652 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
653 struct its_node
*its
;
657 addr
= its
->phys_base
+ GITS_TRANSLATER
;
659 msg
->address_lo
= addr
& ((1UL << 32) - 1);
660 msg
->address_hi
= addr
>> 32;
661 msg
->data
= its_get_event_id(d
);
664 static struct irq_chip its_irq_chip
= {
666 .irq_mask
= its_mask_irq
,
667 .irq_unmask
= its_unmask_irq
,
668 .irq_eoi
= irq_chip_eoi_parent
,
669 .irq_set_affinity
= its_set_affinity
,
670 .irq_compose_msi_msg
= its_irq_compose_msi_msg
,
674 * How we allocate LPIs:
676 * The GIC has id_bits bits for interrupt identifiers. From there, we
677 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
678 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
681 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
683 #define IRQS_PER_CHUNK_SHIFT 5
684 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
686 static unsigned long *lpi_bitmap
;
687 static u32 lpi_chunks
;
688 static DEFINE_SPINLOCK(lpi_lock
);
690 static int its_lpi_to_chunk(int lpi
)
692 return (lpi
- 8192) >> IRQS_PER_CHUNK_SHIFT
;
695 static int its_chunk_to_lpi(int chunk
)
697 return (chunk
<< IRQS_PER_CHUNK_SHIFT
) + 8192;
700 static int __init
its_lpi_init(u32 id_bits
)
702 lpi_chunks
= its_lpi_to_chunk(1UL << id_bits
);
704 lpi_bitmap
= kzalloc(BITS_TO_LONGS(lpi_chunks
) * sizeof(long),
711 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks
);
715 static unsigned long *its_lpi_alloc_chunks(int nr_irqs
, int *base
, int *nr_ids
)
717 unsigned long *bitmap
= NULL
;
722 nr_chunks
= DIV_ROUND_UP(nr_irqs
, IRQS_PER_CHUNK
);
724 spin_lock(&lpi_lock
);
727 chunk_id
= bitmap_find_next_zero_area(lpi_bitmap
, lpi_chunks
,
729 if (chunk_id
< lpi_chunks
)
733 } while (nr_chunks
> 0);
738 bitmap
= kzalloc(BITS_TO_LONGS(nr_chunks
* IRQS_PER_CHUNK
) * sizeof (long),
743 for (i
= 0; i
< nr_chunks
; i
++)
744 set_bit(chunk_id
+ i
, lpi_bitmap
);
746 *base
= its_chunk_to_lpi(chunk_id
);
747 *nr_ids
= nr_chunks
* IRQS_PER_CHUNK
;
750 spin_unlock(&lpi_lock
);
758 static void its_lpi_free(struct event_lpi_map
*map
)
760 int base
= map
->lpi_base
;
761 int nr_ids
= map
->nr_lpis
;
764 spin_lock(&lpi_lock
);
766 for (lpi
= base
; lpi
< (base
+ nr_ids
); lpi
+= IRQS_PER_CHUNK
) {
767 int chunk
= its_lpi_to_chunk(lpi
);
768 BUG_ON(chunk
> lpi_chunks
);
769 if (test_bit(chunk
, lpi_bitmap
)) {
770 clear_bit(chunk
, lpi_bitmap
);
772 pr_err("Bad LPI chunk %d\n", chunk
);
776 spin_unlock(&lpi_lock
);
783 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
784 * deal with (one configuration byte per interrupt). PENDBASE has to
785 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
787 #define LPI_PROPBASE_SZ SZ_64K
788 #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
791 * This is how many bits of ID we need, including the useless ones.
793 #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
795 #define LPI_PROP_DEFAULT_PRIO 0xa0
797 static int __init
its_alloc_lpi_tables(void)
801 gic_rdists
->prop_page
= alloc_pages(GFP_NOWAIT
,
802 get_order(LPI_PROPBASE_SZ
));
803 if (!gic_rdists
->prop_page
) {
804 pr_err("Failed to allocate PROPBASE\n");
808 paddr
= page_to_phys(gic_rdists
->prop_page
);
809 pr_info("GIC: using LPI property table @%pa\n", &paddr
);
811 /* Priority 0xa0, Group-1, disabled */
812 memset(page_address(gic_rdists
->prop_page
),
813 LPI_PROP_DEFAULT_PRIO
| LPI_PROP_GROUP1
,
816 /* Make sure the GIC will observe the written configuration */
817 __flush_dcache_area(page_address(gic_rdists
->prop_page
), LPI_PROPBASE_SZ
);
822 static const char *its_base_type_string
[] = {
823 [GITS_BASER_TYPE_DEVICE
] = "Devices",
824 [GITS_BASER_TYPE_VCPU
] = "Virtual CPUs",
825 [GITS_BASER_TYPE_CPU
] = "Physical CPUs",
826 [GITS_BASER_TYPE_COLLECTION
] = "Interrupt Collections",
827 [GITS_BASER_TYPE_RESERVED5
] = "Reserved (5)",
828 [GITS_BASER_TYPE_RESERVED6
] = "Reserved (6)",
829 [GITS_BASER_TYPE_RESERVED7
] = "Reserved (7)",
832 static u64
its_read_baser(struct its_node
*its
, struct its_baser
*baser
)
834 u32 idx
= baser
- its
->tables
;
836 return readq_relaxed(its
->base
+ GITS_BASER
+ (idx
<< 3));
839 static void its_write_baser(struct its_node
*its
, struct its_baser
*baser
,
842 u32 idx
= baser
- its
->tables
;
844 writeq_relaxed(val
, its
->base
+ GITS_BASER
+ (idx
<< 3));
845 baser
->val
= its_read_baser(its
, baser
);
848 static int its_setup_baser(struct its_node
*its
, struct its_baser
*baser
,
849 u64 cache
, u64 shr
, u32 psz
, u32 order
,
852 u64 val
= its_read_baser(its
, baser
);
853 u64 esz
= GITS_BASER_ENTRY_SIZE(val
);
854 u64 type
= GITS_BASER_TYPE(val
);
860 alloc_pages
= (PAGE_ORDER_TO_SIZE(order
) / psz
);
861 if (alloc_pages
> GITS_BASER_PAGES_MAX
) {
862 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
863 &its
->phys_base
, its_base_type_string
[type
],
864 alloc_pages
, GITS_BASER_PAGES_MAX
);
865 alloc_pages
= GITS_BASER_PAGES_MAX
;
866 order
= get_order(GITS_BASER_PAGES_MAX
* psz
);
869 base
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
, order
);
874 val
= (virt_to_phys(base
) |
875 (type
<< GITS_BASER_TYPE_SHIFT
) |
876 ((esz
- 1) << GITS_BASER_ENTRY_SIZE_SHIFT
) |
877 ((alloc_pages
- 1) << GITS_BASER_PAGES_SHIFT
) |
882 val
|= indirect
? GITS_BASER_INDIRECT
: 0x0;
886 val
|= GITS_BASER_PAGE_SIZE_4K
;
889 val
|= GITS_BASER_PAGE_SIZE_16K
;
892 val
|= GITS_BASER_PAGE_SIZE_64K
;
896 its_write_baser(its
, baser
, val
);
899 if ((val
^ tmp
) & GITS_BASER_SHAREABILITY_MASK
) {
901 * Shareability didn't stick. Just use
902 * whatever the read reported, which is likely
903 * to be the only thing this redistributor
904 * supports. If that's zero, make it
905 * non-cacheable as well.
907 shr
= tmp
& GITS_BASER_SHAREABILITY_MASK
;
909 cache
= GITS_BASER_nC
;
910 __flush_dcache_area(base
, PAGE_ORDER_TO_SIZE(order
));
915 if ((val
^ tmp
) & GITS_BASER_PAGE_SIZE_MASK
) {
917 * Page size didn't stick. Let's try a smaller
918 * size and retry. If we reach 4K, then
919 * something is horribly wrong...
921 free_pages((unsigned long)base
, order
);
927 goto retry_alloc_baser
;
930 goto retry_alloc_baser
;
935 pr_err("ITS@%pa: %s doesn't stick: %lx %lx\n",
936 &its
->phys_base
, its_base_type_string
[type
],
937 (unsigned long) val
, (unsigned long) tmp
);
938 free_pages((unsigned long)base
, order
);
942 baser
->order
= order
;
945 tmp
= indirect
? GITS_LVL1_ENTRY_SIZE
: esz
;
947 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
948 &its
->phys_base
, (int)(PAGE_ORDER_TO_SIZE(order
) / tmp
),
949 its_base_type_string
[type
],
950 (unsigned long)virt_to_phys(base
),
951 indirect
? "indirect" : "flat", (int)esz
,
952 psz
/ SZ_1K
, (int)shr
>> GITS_BASER_SHAREABILITY_SHIFT
);
957 static bool its_parse_baser_device(struct its_node
*its
, struct its_baser
*baser
,
960 u64 esz
= GITS_BASER_ENTRY_SIZE(its_read_baser(its
, baser
));
961 u64 val
= GITS_BASER_InnerShareable
| GITS_BASER_WaWb
;
962 u32 ids
= its
->device_ids
;
963 u32 new_order
= *order
;
964 bool indirect
= false;
966 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
967 if ((esz
<< ids
) > (psz
* 2)) {
969 * Find out whether hw supports a single or two-level table by
970 * table by reading bit at offset '62' after writing '1' to it.
972 its_write_baser(its
, baser
, val
| GITS_BASER_INDIRECT
);
973 indirect
= !!(baser
->val
& GITS_BASER_INDIRECT
);
977 * The size of the lvl2 table is equal to ITS page size
978 * which is 'psz'. For computing lvl1 table size,
979 * subtract ID bits that sparse lvl2 table from 'ids'
980 * which is reported by ITS hardware times lvl1 table
983 ids
-= ilog2(psz
/ esz
);
984 esz
= GITS_LVL1_ENTRY_SIZE
;
989 * Allocate as many entries as required to fit the
990 * range of device IDs that the ITS can grok... The ID
991 * space being incredibly sparse, this results in a
992 * massive waste of memory if two-level device table
993 * feature is not supported by hardware.
995 new_order
= max_t(u32
, get_order(esz
<< ids
), new_order
);
996 if (new_order
>= MAX_ORDER
) {
997 new_order
= MAX_ORDER
- 1;
998 ids
= ilog2(PAGE_ORDER_TO_SIZE(new_order
) / esz
);
999 pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n",
1000 &its
->phys_base
, its
->device_ids
, ids
);
1008 static void its_free_tables(struct its_node
*its
)
1012 for (i
= 0; i
< GITS_BASER_NR_REGS
; i
++) {
1013 if (its
->tables
[i
].base
) {
1014 free_pages((unsigned long)its
->tables
[i
].base
,
1015 its
->tables
[i
].order
);
1016 its
->tables
[i
].base
= NULL
;
1021 static int its_alloc_tables(struct its_node
*its
)
1023 u64 typer
= readq_relaxed(its
->base
+ GITS_TYPER
);
1024 u32 ids
= GITS_TYPER_DEVBITS(typer
);
1025 u64 shr
= GITS_BASER_InnerShareable
;
1026 u64 cache
= GITS_BASER_WaWb
;
1030 if (its
->flags
& ITS_FLAGS_WORKAROUND_CAVIUM_22375
) {
1032 * erratum 22375: only alloc 8MB table size
1033 * erratum 24313: ignore memory access type
1035 cache
= GITS_BASER_nCnB
;
1036 ids
= 0x14; /* 20 bits, 8MB */
1039 its
->device_ids
= ids
;
1041 for (i
= 0; i
< GITS_BASER_NR_REGS
; i
++) {
1042 struct its_baser
*baser
= its
->tables
+ i
;
1043 u64 val
= its_read_baser(its
, baser
);
1044 u64 type
= GITS_BASER_TYPE(val
);
1045 u32 order
= get_order(psz
);
1046 bool indirect
= false;
1048 if (type
== GITS_BASER_TYPE_NONE
)
1051 if (type
== GITS_BASER_TYPE_DEVICE
)
1052 indirect
= its_parse_baser_device(its
, baser
, psz
, &order
);
1054 err
= its_setup_baser(its
, baser
, cache
, shr
, psz
, order
, indirect
);
1056 its_free_tables(its
);
1060 /* Update settings which will be used for next BASERn */
1062 cache
= baser
->val
& GITS_BASER_CACHEABILITY_MASK
;
1063 shr
= baser
->val
& GITS_BASER_SHAREABILITY_MASK
;
1069 static int its_alloc_collections(struct its_node
*its
)
1071 its
->collections
= kzalloc(nr_cpu_ids
* sizeof(*its
->collections
),
1073 if (!its
->collections
)
1079 static void its_cpu_init_lpis(void)
1081 void __iomem
*rbase
= gic_data_rdist_rd_base();
1082 struct page
*pend_page
;
1085 /* If we didn't allocate the pending table yet, do it now */
1086 pend_page
= gic_data_rdist()->pend_page
;
1090 * The pending pages have to be at least 64kB aligned,
1091 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1093 pend_page
= alloc_pages(GFP_NOWAIT
| __GFP_ZERO
,
1094 get_order(max(LPI_PENDBASE_SZ
, SZ_64K
)));
1096 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1097 smp_processor_id());
1101 /* Make sure the GIC will observe the zero-ed page */
1102 __flush_dcache_area(page_address(pend_page
), LPI_PENDBASE_SZ
);
1104 paddr
= page_to_phys(pend_page
);
1105 pr_info("CPU%d: using LPI pending table @%pa\n",
1106 smp_processor_id(), &paddr
);
1107 gic_data_rdist()->pend_page
= pend_page
;
1111 val
= readl_relaxed(rbase
+ GICR_CTLR
);
1112 val
&= ~GICR_CTLR_ENABLE_LPIS
;
1113 writel_relaxed(val
, rbase
+ GICR_CTLR
);
1116 * Make sure any change to the table is observable by the GIC.
1121 val
= (page_to_phys(gic_rdists
->prop_page
) |
1122 GICR_PROPBASER_InnerShareable
|
1123 GICR_PROPBASER_WaWb
|
1124 ((LPI_NRBITS
- 1) & GICR_PROPBASER_IDBITS_MASK
));
1126 writeq_relaxed(val
, rbase
+ GICR_PROPBASER
);
1127 tmp
= readq_relaxed(rbase
+ GICR_PROPBASER
);
1129 if ((tmp
^ val
) & GICR_PROPBASER_SHAREABILITY_MASK
) {
1130 if (!(tmp
& GICR_PROPBASER_SHAREABILITY_MASK
)) {
1132 * The HW reports non-shareable, we must
1133 * remove the cacheability attributes as
1136 val
&= ~(GICR_PROPBASER_SHAREABILITY_MASK
|
1137 GICR_PROPBASER_CACHEABILITY_MASK
);
1138 val
|= GICR_PROPBASER_nC
;
1139 writeq_relaxed(val
, rbase
+ GICR_PROPBASER
);
1141 pr_info_once("GIC: using cache flushing for LPI property table\n");
1142 gic_rdists
->flags
|= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING
;
1146 val
= (page_to_phys(pend_page
) |
1147 GICR_PENDBASER_InnerShareable
|
1148 GICR_PENDBASER_WaWb
);
1150 writeq_relaxed(val
, rbase
+ GICR_PENDBASER
);
1151 tmp
= readq_relaxed(rbase
+ GICR_PENDBASER
);
1153 if (!(tmp
& GICR_PENDBASER_SHAREABILITY_MASK
)) {
1155 * The HW reports non-shareable, we must remove the
1156 * cacheability attributes as well.
1158 val
&= ~(GICR_PENDBASER_SHAREABILITY_MASK
|
1159 GICR_PENDBASER_CACHEABILITY_MASK
);
1160 val
|= GICR_PENDBASER_nC
;
1161 writeq_relaxed(val
, rbase
+ GICR_PENDBASER
);
1165 val
= readl_relaxed(rbase
+ GICR_CTLR
);
1166 val
|= GICR_CTLR_ENABLE_LPIS
;
1167 writel_relaxed(val
, rbase
+ GICR_CTLR
);
1169 /* Make sure the GIC has seen the above */
1173 static void its_cpu_init_collection(void)
1175 struct its_node
*its
;
1178 spin_lock(&its_lock
);
1179 cpu
= smp_processor_id();
1181 list_for_each_entry(its
, &its_nodes
, entry
) {
1184 /* avoid cross node collections and its mapping */
1185 if (its
->flags
& ITS_FLAGS_WORKAROUND_CAVIUM_23144
) {
1186 struct device_node
*cpu_node
;
1188 cpu_node
= of_get_cpu_node(cpu
, NULL
);
1189 if (its
->numa_node
!= NUMA_NO_NODE
&&
1190 its
->numa_node
!= of_node_to_nid(cpu_node
))
1195 * We now have to bind each collection to its target
1198 if (readq_relaxed(its
->base
+ GITS_TYPER
) & GITS_TYPER_PTA
) {
1200 * This ITS wants the physical address of the
1203 target
= gic_data_rdist()->phys_base
;
1206 * This ITS wants a linear CPU number.
1208 target
= readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER
);
1209 target
= GICR_TYPER_CPU_NUMBER(target
) << 16;
1212 /* Perform collection mapping */
1213 its
->collections
[cpu
].target_address
= target
;
1214 its
->collections
[cpu
].col_id
= cpu
;
1216 its_send_mapc(its
, &its
->collections
[cpu
], 1);
1217 its_send_invall(its
, &its
->collections
[cpu
]);
1220 spin_unlock(&its_lock
);
1223 static struct its_device
*its_find_device(struct its_node
*its
, u32 dev_id
)
1225 struct its_device
*its_dev
= NULL
, *tmp
;
1226 unsigned long flags
;
1228 raw_spin_lock_irqsave(&its
->lock
, flags
);
1230 list_for_each_entry(tmp
, &its
->its_device_list
, entry
) {
1231 if (tmp
->device_id
== dev_id
) {
1237 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
1242 static struct its_baser
*its_get_baser(struct its_node
*its
, u32 type
)
1246 for (i
= 0; i
< GITS_BASER_NR_REGS
; i
++) {
1247 if (GITS_BASER_TYPE(its
->tables
[i
].val
) == type
)
1248 return &its
->tables
[i
];
1254 static bool its_alloc_device_table(struct its_node
*its
, u32 dev_id
)
1256 struct its_baser
*baser
;
1261 baser
= its_get_baser(its
, GITS_BASER_TYPE_DEVICE
);
1263 /* Don't allow device id that exceeds ITS hardware limit */
1265 return (ilog2(dev_id
) < its
->device_ids
);
1267 /* Don't allow device id that exceeds single, flat table limit */
1268 esz
= GITS_BASER_ENTRY_SIZE(baser
->val
);
1269 if (!(baser
->val
& GITS_BASER_INDIRECT
))
1270 return (dev_id
< (PAGE_ORDER_TO_SIZE(baser
->order
) / esz
));
1272 /* Compute 1st level table index & check if that exceeds table limit */
1273 idx
= dev_id
>> ilog2(baser
->psz
/ esz
);
1274 if (idx
>= (PAGE_ORDER_TO_SIZE(baser
->order
) / GITS_LVL1_ENTRY_SIZE
))
1277 table
= baser
->base
;
1279 /* Allocate memory for 2nd level table */
1281 page
= alloc_pages(GFP_KERNEL
| __GFP_ZERO
, get_order(baser
->psz
));
1285 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
1286 if (!(baser
->val
& GITS_BASER_SHAREABILITY_MASK
))
1287 __flush_dcache_area(page_address(page
), baser
->psz
);
1289 table
[idx
] = cpu_to_le64(page_to_phys(page
) | GITS_BASER_VALID
);
1291 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
1292 if (!(baser
->val
& GITS_BASER_SHAREABILITY_MASK
))
1293 __flush_dcache_area(table
+ idx
, GITS_LVL1_ENTRY_SIZE
);
1295 /* Ensure updated table contents are visible to ITS hardware */
1302 static struct its_device
*its_create_device(struct its_node
*its
, u32 dev_id
,
1305 struct its_device
*dev
;
1306 unsigned long *lpi_map
;
1307 unsigned long flags
;
1308 u16
*col_map
= NULL
;
1315 if (!its_alloc_device_table(its
, dev_id
))
1318 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1320 * At least one bit of EventID is being used, hence a minimum
1321 * of two entries. No, the architecture doesn't let you
1322 * express an ITT with a single entry.
1324 nr_ites
= max(2UL, roundup_pow_of_two(nvecs
));
1325 sz
= nr_ites
* its
->ite_size
;
1326 sz
= max(sz
, ITS_ITT_ALIGN
) + ITS_ITT_ALIGN
- 1;
1327 itt
= kzalloc(sz
, GFP_KERNEL
);
1328 lpi_map
= its_lpi_alloc_chunks(nvecs
, &lpi_base
, &nr_lpis
);
1330 col_map
= kzalloc(sizeof(*col_map
) * nr_lpis
, GFP_KERNEL
);
1332 if (!dev
|| !itt
|| !lpi_map
|| !col_map
) {
1340 __flush_dcache_area(itt
, sz
);
1344 dev
->nr_ites
= nr_ites
;
1345 dev
->event_map
.lpi_map
= lpi_map
;
1346 dev
->event_map
.col_map
= col_map
;
1347 dev
->event_map
.lpi_base
= lpi_base
;
1348 dev
->event_map
.nr_lpis
= nr_lpis
;
1349 dev
->device_id
= dev_id
;
1350 INIT_LIST_HEAD(&dev
->entry
);
1352 raw_spin_lock_irqsave(&its
->lock
, flags
);
1353 list_add(&dev
->entry
, &its
->its_device_list
);
1354 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
1356 /* Map device to its ITT */
1357 its_send_mapd(dev
, 1);
1362 static void its_free_device(struct its_device
*its_dev
)
1364 unsigned long flags
;
1366 raw_spin_lock_irqsave(&its_dev
->its
->lock
, flags
);
1367 list_del(&its_dev
->entry
);
1368 raw_spin_unlock_irqrestore(&its_dev
->its
->lock
, flags
);
1369 kfree(its_dev
->itt
);
1373 static int its_alloc_device_irq(struct its_device
*dev
, irq_hw_number_t
*hwirq
)
1377 idx
= find_first_zero_bit(dev
->event_map
.lpi_map
,
1378 dev
->event_map
.nr_lpis
);
1379 if (idx
== dev
->event_map
.nr_lpis
)
1382 *hwirq
= dev
->event_map
.lpi_base
+ idx
;
1383 set_bit(idx
, dev
->event_map
.lpi_map
);
1388 static int its_msi_prepare(struct irq_domain
*domain
, struct device
*dev
,
1389 int nvec
, msi_alloc_info_t
*info
)
1391 struct its_node
*its
;
1392 struct its_device
*its_dev
;
1393 struct msi_domain_info
*msi_info
;
1397 * We ignore "dev" entierely, and rely on the dev_id that has
1398 * been passed via the scratchpad. This limits this domain's
1399 * usefulness to upper layers that definitely know that they
1400 * are built on top of the ITS.
1402 dev_id
= info
->scratchpad
[0].ul
;
1404 msi_info
= msi_get_domain_info(domain
);
1405 its
= msi_info
->data
;
1407 its_dev
= its_find_device(its
, dev_id
);
1410 * We already have seen this ID, probably through
1411 * another alias (PCI bridge of some sort). No need to
1412 * create the device.
1414 pr_debug("Reusing ITT for devID %x\n", dev_id
);
1418 its_dev
= its_create_device(its
, dev_id
, nvec
);
1422 pr_debug("ITT %d entries, %d bits\n", nvec
, ilog2(nvec
));
1424 info
->scratchpad
[0].ptr
= its_dev
;
1428 static struct msi_domain_ops its_msi_domain_ops
= {
1429 .msi_prepare
= its_msi_prepare
,
1432 static int its_irq_gic_domain_alloc(struct irq_domain
*domain
,
1434 irq_hw_number_t hwirq
)
1436 struct irq_fwspec fwspec
;
1438 if (irq_domain_get_of_node(domain
->parent
)) {
1439 fwspec
.fwnode
= domain
->parent
->fwnode
;
1440 fwspec
.param_count
= 3;
1441 fwspec
.param
[0] = GIC_IRQ_TYPE_LPI
;
1442 fwspec
.param
[1] = hwirq
;
1443 fwspec
.param
[2] = IRQ_TYPE_EDGE_RISING
;
1444 } else if (is_fwnode_irqchip(domain
->parent
->fwnode
)) {
1445 fwspec
.fwnode
= domain
->parent
->fwnode
;
1446 fwspec
.param_count
= 2;
1447 fwspec
.param
[0] = hwirq
;
1448 fwspec
.param
[1] = IRQ_TYPE_EDGE_RISING
;
1453 return irq_domain_alloc_irqs_parent(domain
, virq
, 1, &fwspec
);
1456 static int its_irq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
1457 unsigned int nr_irqs
, void *args
)
1459 msi_alloc_info_t
*info
= args
;
1460 struct its_device
*its_dev
= info
->scratchpad
[0].ptr
;
1461 irq_hw_number_t hwirq
;
1465 for (i
= 0; i
< nr_irqs
; i
++) {
1466 err
= its_alloc_device_irq(its_dev
, &hwirq
);
1470 err
= its_irq_gic_domain_alloc(domain
, virq
+ i
, hwirq
);
1474 irq_domain_set_hwirq_and_chip(domain
, virq
+ i
,
1475 hwirq
, &its_irq_chip
, its_dev
);
1476 pr_debug("ID:%d pID:%d vID:%d\n",
1477 (int)(hwirq
- its_dev
->event_map
.lpi_base
),
1478 (int) hwirq
, virq
+ i
);
1484 static void its_irq_domain_activate(struct irq_domain
*domain
,
1487 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1488 u32 event
= its_get_event_id(d
);
1489 const struct cpumask
*cpu_mask
= cpu_online_mask
;
1491 /* get the cpu_mask of local node */
1492 if (its_dev
->its
->numa_node
>= 0)
1493 cpu_mask
= cpumask_of_node(its_dev
->its
->numa_node
);
1495 /* Bind the LPI to the first possible CPU */
1496 its_dev
->event_map
.col_map
[event
] = cpumask_first(cpu_mask
);
1498 /* Map the GIC IRQ and event to the device */
1499 its_send_mapvi(its_dev
, d
->hwirq
, event
);
1502 static void its_irq_domain_deactivate(struct irq_domain
*domain
,
1505 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1506 u32 event
= its_get_event_id(d
);
1508 /* Stop the delivery of interrupts */
1509 its_send_discard(its_dev
, event
);
1512 static void its_irq_domain_free(struct irq_domain
*domain
, unsigned int virq
,
1513 unsigned int nr_irqs
)
1515 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
);
1516 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1519 for (i
= 0; i
< nr_irqs
; i
++) {
1520 struct irq_data
*data
= irq_domain_get_irq_data(domain
,
1522 u32 event
= its_get_event_id(data
);
1524 /* Mark interrupt index as unused */
1525 clear_bit(event
, its_dev
->event_map
.lpi_map
);
1527 /* Nuke the entry in the domain */
1528 irq_domain_reset_irq_data(data
);
1531 /* If all interrupts have been freed, start mopping the floor */
1532 if (bitmap_empty(its_dev
->event_map
.lpi_map
,
1533 its_dev
->event_map
.nr_lpis
)) {
1534 its_lpi_free(&its_dev
->event_map
);
1536 /* Unmap device/itt */
1537 its_send_mapd(its_dev
, 0);
1538 its_free_device(its_dev
);
1541 irq_domain_free_irqs_parent(domain
, virq
, nr_irqs
);
1544 static const struct irq_domain_ops its_domain_ops
= {
1545 .alloc
= its_irq_domain_alloc
,
1546 .free
= its_irq_domain_free
,
1547 .activate
= its_irq_domain_activate
,
1548 .deactivate
= its_irq_domain_deactivate
,
1551 static int its_force_quiescent(void __iomem
*base
)
1553 u32 count
= 1000000; /* 1s */
1556 val
= readl_relaxed(base
+ GITS_CTLR
);
1558 * GIC architecture specification requires the ITS to be both
1559 * disabled and quiescent for writes to GITS_BASER<n> or
1560 * GITS_CBASER to not have UNPREDICTABLE results.
1562 if ((val
& GITS_CTLR_QUIESCENT
) && !(val
& GITS_CTLR_ENABLE
))
1565 /* Disable the generation of all interrupts to this ITS */
1566 val
&= ~GITS_CTLR_ENABLE
;
1567 writel_relaxed(val
, base
+ GITS_CTLR
);
1569 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1571 val
= readl_relaxed(base
+ GITS_CTLR
);
1572 if (val
& GITS_CTLR_QUIESCENT
)
1584 static void __maybe_unused
its_enable_quirk_cavium_22375(void *data
)
1586 struct its_node
*its
= data
;
1588 its
->flags
|= ITS_FLAGS_WORKAROUND_CAVIUM_22375
;
1591 static void __maybe_unused
its_enable_quirk_cavium_23144(void *data
)
1593 struct its_node
*its
= data
;
1595 its
->flags
|= ITS_FLAGS_WORKAROUND_CAVIUM_23144
;
1598 static const struct gic_quirk its_quirks
[] = {
1599 #ifdef CONFIG_CAVIUM_ERRATUM_22375
1601 .desc
= "ITS: Cavium errata 22375, 24313",
1602 .iidr
= 0xa100034c, /* ThunderX pass 1.x */
1604 .init
= its_enable_quirk_cavium_22375
,
1607 #ifdef CONFIG_CAVIUM_ERRATUM_23144
1609 .desc
= "ITS: Cavium erratum 23144",
1610 .iidr
= 0xa100034c, /* ThunderX pass 1.x */
1612 .init
= its_enable_quirk_cavium_23144
,
1619 static void its_enable_quirks(struct its_node
*its
)
1621 u32 iidr
= readl_relaxed(its
->base
+ GITS_IIDR
);
1623 gic_enable_quirks(iidr
, its_quirks
, its
);
1626 static int its_init_domain(struct fwnode_handle
*handle
, struct its_node
*its
)
1628 struct irq_domain
*inner_domain
;
1629 struct msi_domain_info
*info
;
1631 info
= kzalloc(sizeof(*info
), GFP_KERNEL
);
1635 inner_domain
= irq_domain_create_tree(handle
, &its_domain_ops
, its
);
1636 if (!inner_domain
) {
1641 inner_domain
->parent
= its_parent
;
1642 inner_domain
->bus_token
= DOMAIN_BUS_NEXUS
;
1643 info
->ops
= &its_msi_domain_ops
;
1645 inner_domain
->host_data
= info
;
1650 static int __init
its_probe_one(struct resource
*res
,
1651 struct fwnode_handle
*handle
, int numa_node
)
1653 struct its_node
*its
;
1654 void __iomem
*its_base
;
1659 its_base
= ioremap(res
->start
, resource_size(res
));
1661 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res
->start
);
1665 val
= readl_relaxed(its_base
+ GITS_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
1666 if (val
!= 0x30 && val
!= 0x40) {
1667 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res
->start
);
1672 err
= its_force_quiescent(its_base
);
1674 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res
->start
);
1678 pr_info("ITS %pR\n", res
);
1680 its
= kzalloc(sizeof(*its
), GFP_KERNEL
);
1686 raw_spin_lock_init(&its
->lock
);
1687 INIT_LIST_HEAD(&its
->entry
);
1688 INIT_LIST_HEAD(&its
->its_device_list
);
1689 its
->base
= its_base
;
1690 its
->phys_base
= res
->start
;
1691 its
->ite_size
= ((readl_relaxed(its_base
+ GITS_TYPER
) >> 4) & 0xf) + 1;
1692 its
->numa_node
= numa_node
;
1694 its
->cmd_base
= kzalloc(ITS_CMD_QUEUE_SZ
, GFP_KERNEL
);
1695 if (!its
->cmd_base
) {
1699 its
->cmd_write
= its
->cmd_base
;
1701 its_enable_quirks(its
);
1703 err
= its_alloc_tables(its
);
1707 err
= its_alloc_collections(its
);
1709 goto out_free_tables
;
1711 baser
= (virt_to_phys(its
->cmd_base
) |
1713 GITS_CBASER_InnerShareable
|
1714 (ITS_CMD_QUEUE_SZ
/ SZ_4K
- 1) |
1717 writeq_relaxed(baser
, its
->base
+ GITS_CBASER
);
1718 tmp
= readq_relaxed(its
->base
+ GITS_CBASER
);
1720 if ((tmp
^ baser
) & GITS_CBASER_SHAREABILITY_MASK
) {
1721 if (!(tmp
& GITS_CBASER_SHAREABILITY_MASK
)) {
1723 * The HW reports non-shareable, we must
1724 * remove the cacheability attributes as
1727 baser
&= ~(GITS_CBASER_SHAREABILITY_MASK
|
1728 GITS_CBASER_CACHEABILITY_MASK
);
1729 baser
|= GITS_CBASER_nC
;
1730 writeq_relaxed(baser
, its
->base
+ GITS_CBASER
);
1732 pr_info("ITS: using cache flushing for cmd queue\n");
1733 its
->flags
|= ITS_FLAGS_CMDQ_NEEDS_FLUSHING
;
1736 writeq_relaxed(0, its
->base
+ GITS_CWRITER
);
1737 writel_relaxed(GITS_CTLR_ENABLE
, its
->base
+ GITS_CTLR
);
1739 err
= its_init_domain(handle
, its
);
1741 goto out_free_tables
;
1743 spin_lock(&its_lock
);
1744 list_add(&its
->entry
, &its_nodes
);
1745 spin_unlock(&its_lock
);
1750 its_free_tables(its
);
1752 kfree(its
->cmd_base
);
1757 pr_err("ITS@%pa: failed probing (%d)\n", &res
->start
, err
);
1761 static bool gic_rdists_supports_plpis(void)
1763 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER
) & GICR_TYPER_PLPIS
);
1766 int its_cpu_init(void)
1768 if (!list_empty(&its_nodes
)) {
1769 if (!gic_rdists_supports_plpis()) {
1770 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1773 its_cpu_init_lpis();
1774 its_cpu_init_collection();
1780 static struct of_device_id its_device_id
[] = {
1781 { .compatible
= "arm,gic-v3-its", },
1785 static int __init
its_of_probe(struct device_node
*node
)
1787 struct device_node
*np
;
1788 struct resource res
;
1790 for (np
= of_find_matching_node(node
, its_device_id
); np
;
1791 np
= of_find_matching_node(np
, its_device_id
)) {
1792 if (!of_property_read_bool(np
, "msi-controller")) {
1793 pr_warn("%s: no msi-controller property, ITS ignored\n",
1798 if (of_address_to_resource(np
, 0, &res
)) {
1799 pr_warn("%s: no regs?\n", np
->full_name
);
1803 its_probe_one(&res
, &np
->fwnode
, of_node_to_nid(np
));
1810 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
1812 static int __init
gic_acpi_parse_madt_its(struct acpi_subtable_header
*header
,
1813 const unsigned long end
)
1815 struct acpi_madt_generic_translator
*its_entry
;
1816 struct fwnode_handle
*dom_handle
;
1817 struct resource res
;
1820 its_entry
= (struct acpi_madt_generic_translator
*)header
;
1821 memset(&res
, 0, sizeof(res
));
1822 res
.start
= its_entry
->base_address
;
1823 res
.end
= its_entry
->base_address
+ ACPI_GICV3_ITS_MEM_SIZE
- 1;
1824 res
.flags
= IORESOURCE_MEM
;
1826 dom_handle
= irq_domain_alloc_fwnode((void *)its_entry
->base_address
);
1828 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
1833 err
= iort_register_domain_token(its_entry
->translation_id
, dom_handle
);
1835 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
1836 &res
.start
, its_entry
->translation_id
);
1840 err
= its_probe_one(&res
, dom_handle
, NUMA_NO_NODE
);
1844 iort_deregister_domain_token(its_entry
->translation_id
);
1846 irq_domain_free_fwnode(dom_handle
);
1850 static void __init
its_acpi_probe(void)
1852 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR
,
1853 gic_acpi_parse_madt_its
, 0);
1856 static void __init
its_acpi_probe(void) { }
1859 int __init
its_init(struct fwnode_handle
*handle
, struct rdists
*rdists
,
1860 struct irq_domain
*parent_domain
)
1862 struct device_node
*of_node
;
1864 its_parent
= parent_domain
;
1865 of_node
= to_of_node(handle
);
1867 its_of_probe(of_node
);
1871 if (list_empty(&its_nodes
)) {
1872 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1876 gic_rdists
= rdists
;
1877 its_alloc_lpi_tables();
1878 its_lpi_init(rdists
->id_bits
);