2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/bitmap.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/log2.h>
24 #include <linux/msi.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_pci.h>
29 #include <linux/of_platform.h>
30 #include <linux/percpu.h>
31 #include <linux/slab.h>
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-v3.h>
36 #include <asm/cacheflush.h>
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
40 #include "irq-gic-common.h"
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
48 * Collection structure - just an ID, and a redistributor address to
49 * ping. We use one per CPU as a bag of interrupts assigned to this
52 struct its_collection
{
58 * The ITS structure - contains most of the infrastructure, with the
59 * top-level MSI domain, the command queue, the collections, and the
60 * list of devices writing to it.
64 struct list_head entry
;
66 unsigned long phys_base
;
67 struct its_cmd_block
*cmd_base
;
68 struct its_cmd_block
*cmd_write
;
72 } tables
[GITS_BASER_NR_REGS
];
73 struct its_collection
*collections
;
74 struct list_head its_device_list
;
79 #define ITS_ITT_ALIGN SZ_256
81 struct event_lpi_map
{
82 unsigned long *lpi_map
;
84 irq_hw_number_t lpi_base
;
89 * The ITS view of a device - belongs to an ITS, a collection, owns an
90 * interrupt translation table, and a list of interrupts.
93 struct list_head entry
;
95 struct event_lpi_map event_map
;
101 static LIST_HEAD(its_nodes
);
102 static DEFINE_SPINLOCK(its_lock
);
103 static struct device_node
*gic_root_node
;
104 static struct rdists
*gic_rdists
;
106 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
107 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
109 static struct its_collection
*dev_event_to_col(struct its_device
*its_dev
,
112 struct its_node
*its
= its_dev
->its
;
114 return its
->collections
+ its_dev
->event_map
.col_map
[event
];
118 * ITS command descriptors - parameters to be encoded in a command
121 struct its_cmd_desc
{
124 struct its_device
*dev
;
129 struct its_device
*dev
;
134 struct its_device
*dev
;
139 struct its_collection
*col
;
144 struct its_device
*dev
;
150 struct its_device
*dev
;
151 struct its_collection
*col
;
156 struct its_device
*dev
;
161 struct its_collection
*col
;
167 * The ITS command block, which is what the ITS actually parses.
169 struct its_cmd_block
{
173 #define ITS_CMD_QUEUE_SZ SZ_64K
174 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
176 typedef struct its_collection
*(*its_cmd_builder_t
)(struct its_cmd_block
*,
177 struct its_cmd_desc
*);
179 static void its_encode_cmd(struct its_cmd_block
*cmd
, u8 cmd_nr
)
181 cmd
->raw_cmd
[0] &= ~0xffUL
;
182 cmd
->raw_cmd
[0] |= cmd_nr
;
185 static void its_encode_devid(struct its_cmd_block
*cmd
, u32 devid
)
187 cmd
->raw_cmd
[0] &= BIT_ULL(32) - 1;
188 cmd
->raw_cmd
[0] |= ((u64
)devid
) << 32;
191 static void its_encode_event_id(struct its_cmd_block
*cmd
, u32 id
)
193 cmd
->raw_cmd
[1] &= ~0xffffffffUL
;
194 cmd
->raw_cmd
[1] |= id
;
197 static void its_encode_phys_id(struct its_cmd_block
*cmd
, u32 phys_id
)
199 cmd
->raw_cmd
[1] &= 0xffffffffUL
;
200 cmd
->raw_cmd
[1] |= ((u64
)phys_id
) << 32;
203 static void its_encode_size(struct its_cmd_block
*cmd
, u8 size
)
205 cmd
->raw_cmd
[1] &= ~0x1fUL
;
206 cmd
->raw_cmd
[1] |= size
& 0x1f;
209 static void its_encode_itt(struct its_cmd_block
*cmd
, u64 itt_addr
)
211 cmd
->raw_cmd
[2] &= ~0xffffffffffffUL
;
212 cmd
->raw_cmd
[2] |= itt_addr
& 0xffffffffff00UL
;
215 static void its_encode_valid(struct its_cmd_block
*cmd
, int valid
)
217 cmd
->raw_cmd
[2] &= ~(1UL << 63);
218 cmd
->raw_cmd
[2] |= ((u64
)!!valid
) << 63;
221 static void its_encode_target(struct its_cmd_block
*cmd
, u64 target_addr
)
223 cmd
->raw_cmd
[2] &= ~(0xffffffffUL
<< 16);
224 cmd
->raw_cmd
[2] |= (target_addr
& (0xffffffffUL
<< 16));
227 static void its_encode_collection(struct its_cmd_block
*cmd
, u16 col
)
229 cmd
->raw_cmd
[2] &= ~0xffffUL
;
230 cmd
->raw_cmd
[2] |= col
;
233 static inline void its_fixup_cmd(struct its_cmd_block
*cmd
)
235 /* Let's fixup BE commands */
236 cmd
->raw_cmd
[0] = cpu_to_le64(cmd
->raw_cmd
[0]);
237 cmd
->raw_cmd
[1] = cpu_to_le64(cmd
->raw_cmd
[1]);
238 cmd
->raw_cmd
[2] = cpu_to_le64(cmd
->raw_cmd
[2]);
239 cmd
->raw_cmd
[3] = cpu_to_le64(cmd
->raw_cmd
[3]);
242 static struct its_collection
*its_build_mapd_cmd(struct its_cmd_block
*cmd
,
243 struct its_cmd_desc
*desc
)
245 unsigned long itt_addr
;
246 u8 size
= ilog2(desc
->its_mapd_cmd
.dev
->nr_ites
);
248 itt_addr
= virt_to_phys(desc
->its_mapd_cmd
.dev
->itt
);
249 itt_addr
= ALIGN(itt_addr
, ITS_ITT_ALIGN
);
251 its_encode_cmd(cmd
, GITS_CMD_MAPD
);
252 its_encode_devid(cmd
, desc
->its_mapd_cmd
.dev
->device_id
);
253 its_encode_size(cmd
, size
- 1);
254 its_encode_itt(cmd
, itt_addr
);
255 its_encode_valid(cmd
, desc
->its_mapd_cmd
.valid
);
262 static struct its_collection
*its_build_mapc_cmd(struct its_cmd_block
*cmd
,
263 struct its_cmd_desc
*desc
)
265 its_encode_cmd(cmd
, GITS_CMD_MAPC
);
266 its_encode_collection(cmd
, desc
->its_mapc_cmd
.col
->col_id
);
267 its_encode_target(cmd
, desc
->its_mapc_cmd
.col
->target_address
);
268 its_encode_valid(cmd
, desc
->its_mapc_cmd
.valid
);
272 return desc
->its_mapc_cmd
.col
;
275 static struct its_collection
*its_build_mapvi_cmd(struct its_cmd_block
*cmd
,
276 struct its_cmd_desc
*desc
)
278 struct its_collection
*col
;
280 col
= dev_event_to_col(desc
->its_mapvi_cmd
.dev
,
281 desc
->its_mapvi_cmd
.event_id
);
283 its_encode_cmd(cmd
, GITS_CMD_MAPVI
);
284 its_encode_devid(cmd
, desc
->its_mapvi_cmd
.dev
->device_id
);
285 its_encode_event_id(cmd
, desc
->its_mapvi_cmd
.event_id
);
286 its_encode_phys_id(cmd
, desc
->its_mapvi_cmd
.phys_id
);
287 its_encode_collection(cmd
, col
->col_id
);
294 static struct its_collection
*its_build_movi_cmd(struct its_cmd_block
*cmd
,
295 struct its_cmd_desc
*desc
)
297 struct its_collection
*col
;
299 col
= dev_event_to_col(desc
->its_movi_cmd
.dev
,
300 desc
->its_movi_cmd
.event_id
);
302 its_encode_cmd(cmd
, GITS_CMD_MOVI
);
303 its_encode_devid(cmd
, desc
->its_movi_cmd
.dev
->device_id
);
304 its_encode_event_id(cmd
, desc
->its_movi_cmd
.event_id
);
305 its_encode_collection(cmd
, desc
->its_movi_cmd
.col
->col_id
);
312 static struct its_collection
*its_build_discard_cmd(struct its_cmd_block
*cmd
,
313 struct its_cmd_desc
*desc
)
315 struct its_collection
*col
;
317 col
= dev_event_to_col(desc
->its_discard_cmd
.dev
,
318 desc
->its_discard_cmd
.event_id
);
320 its_encode_cmd(cmd
, GITS_CMD_DISCARD
);
321 its_encode_devid(cmd
, desc
->its_discard_cmd
.dev
->device_id
);
322 its_encode_event_id(cmd
, desc
->its_discard_cmd
.event_id
);
329 static struct its_collection
*its_build_inv_cmd(struct its_cmd_block
*cmd
,
330 struct its_cmd_desc
*desc
)
332 struct its_collection
*col
;
334 col
= dev_event_to_col(desc
->its_inv_cmd
.dev
,
335 desc
->its_inv_cmd
.event_id
);
337 its_encode_cmd(cmd
, GITS_CMD_INV
);
338 its_encode_devid(cmd
, desc
->its_inv_cmd
.dev
->device_id
);
339 its_encode_event_id(cmd
, desc
->its_inv_cmd
.event_id
);
346 static struct its_collection
*its_build_invall_cmd(struct its_cmd_block
*cmd
,
347 struct its_cmd_desc
*desc
)
349 its_encode_cmd(cmd
, GITS_CMD_INVALL
);
350 its_encode_collection(cmd
, desc
->its_mapc_cmd
.col
->col_id
);
357 static u64
its_cmd_ptr_to_offset(struct its_node
*its
,
358 struct its_cmd_block
*ptr
)
360 return (ptr
- its
->cmd_base
) * sizeof(*ptr
);
363 static int its_queue_full(struct its_node
*its
)
368 widx
= its
->cmd_write
- its
->cmd_base
;
369 ridx
= readl_relaxed(its
->base
+ GITS_CREADR
) / sizeof(struct its_cmd_block
);
371 /* This is incredibly unlikely to happen, unless the ITS locks up. */
372 if (((widx
+ 1) % ITS_CMD_QUEUE_NR_ENTRIES
) == ridx
)
378 static struct its_cmd_block
*its_allocate_entry(struct its_node
*its
)
380 struct its_cmd_block
*cmd
;
381 u32 count
= 1000000; /* 1s! */
383 while (its_queue_full(its
)) {
386 pr_err_ratelimited("ITS queue not draining\n");
393 cmd
= its
->cmd_write
++;
395 /* Handle queue wrapping */
396 if (its
->cmd_write
== (its
->cmd_base
+ ITS_CMD_QUEUE_NR_ENTRIES
))
397 its
->cmd_write
= its
->cmd_base
;
402 static struct its_cmd_block
*its_post_commands(struct its_node
*its
)
404 u64 wr
= its_cmd_ptr_to_offset(its
, its
->cmd_write
);
406 writel_relaxed(wr
, its
->base
+ GITS_CWRITER
);
408 return its
->cmd_write
;
411 static void its_flush_cmd(struct its_node
*its
, struct its_cmd_block
*cmd
)
414 * Make sure the commands written to memory are observable by
417 if (its
->flags
& ITS_FLAGS_CMDQ_NEEDS_FLUSHING
)
418 __flush_dcache_area(cmd
, sizeof(*cmd
));
423 static void its_wait_for_range_completion(struct its_node
*its
,
424 struct its_cmd_block
*from
,
425 struct its_cmd_block
*to
)
427 u64 rd_idx
, from_idx
, to_idx
;
428 u32 count
= 1000000; /* 1s! */
430 from_idx
= its_cmd_ptr_to_offset(its
, from
);
431 to_idx
= its_cmd_ptr_to_offset(its
, to
);
434 rd_idx
= readl_relaxed(its
->base
+ GITS_CREADR
);
435 if (rd_idx
>= to_idx
|| rd_idx
< from_idx
)
440 pr_err_ratelimited("ITS queue timeout\n");
448 static void its_send_single_command(struct its_node
*its
,
449 its_cmd_builder_t builder
,
450 struct its_cmd_desc
*desc
)
452 struct its_cmd_block
*cmd
, *sync_cmd
, *next_cmd
;
453 struct its_collection
*sync_col
;
456 raw_spin_lock_irqsave(&its
->lock
, flags
);
458 cmd
= its_allocate_entry(its
);
459 if (!cmd
) { /* We're soooooo screewed... */
460 pr_err_ratelimited("ITS can't allocate, dropping command\n");
461 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
464 sync_col
= builder(cmd
, desc
);
465 its_flush_cmd(its
, cmd
);
468 sync_cmd
= its_allocate_entry(its
);
470 pr_err_ratelimited("ITS can't SYNC, skipping\n");
473 its_encode_cmd(sync_cmd
, GITS_CMD_SYNC
);
474 its_encode_target(sync_cmd
, sync_col
->target_address
);
475 its_fixup_cmd(sync_cmd
);
476 its_flush_cmd(its
, sync_cmd
);
480 next_cmd
= its_post_commands(its
);
481 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
483 its_wait_for_range_completion(its
, cmd
, next_cmd
);
486 static void its_send_inv(struct its_device
*dev
, u32 event_id
)
488 struct its_cmd_desc desc
;
490 desc
.its_inv_cmd
.dev
= dev
;
491 desc
.its_inv_cmd
.event_id
= event_id
;
493 its_send_single_command(dev
->its
, its_build_inv_cmd
, &desc
);
496 static void its_send_mapd(struct its_device
*dev
, int valid
)
498 struct its_cmd_desc desc
;
500 desc
.its_mapd_cmd
.dev
= dev
;
501 desc
.its_mapd_cmd
.valid
= !!valid
;
503 its_send_single_command(dev
->its
, its_build_mapd_cmd
, &desc
);
506 static void its_send_mapc(struct its_node
*its
, struct its_collection
*col
,
509 struct its_cmd_desc desc
;
511 desc
.its_mapc_cmd
.col
= col
;
512 desc
.its_mapc_cmd
.valid
= !!valid
;
514 its_send_single_command(its
, its_build_mapc_cmd
, &desc
);
517 static void its_send_mapvi(struct its_device
*dev
, u32 irq_id
, u32 id
)
519 struct its_cmd_desc desc
;
521 desc
.its_mapvi_cmd
.dev
= dev
;
522 desc
.its_mapvi_cmd
.phys_id
= irq_id
;
523 desc
.its_mapvi_cmd
.event_id
= id
;
525 its_send_single_command(dev
->its
, its_build_mapvi_cmd
, &desc
);
528 static void its_send_movi(struct its_device
*dev
,
529 struct its_collection
*col
, u32 id
)
531 struct its_cmd_desc desc
;
533 desc
.its_movi_cmd
.dev
= dev
;
534 desc
.its_movi_cmd
.col
= col
;
535 desc
.its_movi_cmd
.event_id
= id
;
537 its_send_single_command(dev
->its
, its_build_movi_cmd
, &desc
);
540 static void its_send_discard(struct its_device
*dev
, u32 id
)
542 struct its_cmd_desc desc
;
544 desc
.its_discard_cmd
.dev
= dev
;
545 desc
.its_discard_cmd
.event_id
= id
;
547 its_send_single_command(dev
->its
, its_build_discard_cmd
, &desc
);
550 static void its_send_invall(struct its_node
*its
, struct its_collection
*col
)
552 struct its_cmd_desc desc
;
554 desc
.its_invall_cmd
.col
= col
;
556 its_send_single_command(its
, its_build_invall_cmd
, &desc
);
560 * irqchip functions - assumes MSI, mostly.
563 static inline u32
its_get_event_id(struct irq_data
*d
)
565 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
566 return d
->hwirq
- its_dev
->event_map
.lpi_base
;
569 static void lpi_set_config(struct irq_data
*d
, bool enable
)
571 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
572 irq_hw_number_t hwirq
= d
->hwirq
;
573 u32 id
= its_get_event_id(d
);
574 u8
*cfg
= page_address(gic_rdists
->prop_page
) + hwirq
- 8192;
577 *cfg
|= LPI_PROP_ENABLED
;
579 *cfg
&= ~LPI_PROP_ENABLED
;
582 * Make the above write visible to the redistributors.
583 * And yes, we're flushing exactly: One. Single. Byte.
586 if (gic_rdists
->flags
& RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING
)
587 __flush_dcache_area(cfg
, sizeof(*cfg
));
590 its_send_inv(its_dev
, id
);
593 static void its_mask_irq(struct irq_data
*d
)
595 lpi_set_config(d
, false);
598 static void its_unmask_irq(struct irq_data
*d
)
600 lpi_set_config(d
, true);
603 static void its_eoi_irq(struct irq_data
*d
)
605 gic_write_eoir(d
->hwirq
);
608 static int its_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
611 unsigned int cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
612 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
613 struct its_collection
*target_col
;
614 u32 id
= its_get_event_id(d
);
616 if (cpu
>= nr_cpu_ids
)
619 target_col
= &its_dev
->its
->collections
[cpu
];
620 its_send_movi(its_dev
, target_col
, id
);
621 its_dev
->event_map
.col_map
[id
] = cpu
;
623 return IRQ_SET_MASK_OK_DONE
;
626 static void its_irq_compose_msi_msg(struct irq_data
*d
, struct msi_msg
*msg
)
628 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
629 struct its_node
*its
;
633 addr
= its
->phys_base
+ GITS_TRANSLATER
;
635 msg
->address_lo
= addr
& ((1UL << 32) - 1);
636 msg
->address_hi
= addr
>> 32;
637 msg
->data
= its_get_event_id(d
);
640 static struct irq_chip its_irq_chip
= {
642 .irq_mask
= its_mask_irq
,
643 .irq_unmask
= its_unmask_irq
,
644 .irq_eoi
= its_eoi_irq
,
645 .irq_set_affinity
= its_set_affinity
,
646 .irq_compose_msi_msg
= its_irq_compose_msi_msg
,
650 * How we allocate LPIs:
652 * The GIC has id_bits bits for interrupt identifiers. From there, we
653 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
654 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
657 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
659 #define IRQS_PER_CHUNK_SHIFT 5
660 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
662 static unsigned long *lpi_bitmap
;
663 static u32 lpi_chunks
;
664 static DEFINE_SPINLOCK(lpi_lock
);
666 static int its_lpi_to_chunk(int lpi
)
668 return (lpi
- 8192) >> IRQS_PER_CHUNK_SHIFT
;
671 static int its_chunk_to_lpi(int chunk
)
673 return (chunk
<< IRQS_PER_CHUNK_SHIFT
) + 8192;
676 static int its_lpi_init(u32 id_bits
)
678 lpi_chunks
= its_lpi_to_chunk(1UL << id_bits
);
680 lpi_bitmap
= kzalloc(BITS_TO_LONGS(lpi_chunks
) * sizeof(long),
687 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks
);
691 static unsigned long *its_lpi_alloc_chunks(int nr_irqs
, int *base
, int *nr_ids
)
693 unsigned long *bitmap
= NULL
;
698 nr_chunks
= DIV_ROUND_UP(nr_irqs
, IRQS_PER_CHUNK
);
700 spin_lock(&lpi_lock
);
703 chunk_id
= bitmap_find_next_zero_area(lpi_bitmap
, lpi_chunks
,
705 if (chunk_id
< lpi_chunks
)
709 } while (nr_chunks
> 0);
714 bitmap
= kzalloc(BITS_TO_LONGS(nr_chunks
* IRQS_PER_CHUNK
) * sizeof (long),
719 for (i
= 0; i
< nr_chunks
; i
++)
720 set_bit(chunk_id
+ i
, lpi_bitmap
);
722 *base
= its_chunk_to_lpi(chunk_id
);
723 *nr_ids
= nr_chunks
* IRQS_PER_CHUNK
;
726 spin_unlock(&lpi_lock
);
734 static void its_lpi_free(struct event_lpi_map
*map
)
736 int base
= map
->lpi_base
;
737 int nr_ids
= map
->nr_lpis
;
740 spin_lock(&lpi_lock
);
742 for (lpi
= base
; lpi
< (base
+ nr_ids
); lpi
+= IRQS_PER_CHUNK
) {
743 int chunk
= its_lpi_to_chunk(lpi
);
744 BUG_ON(chunk
> lpi_chunks
);
745 if (test_bit(chunk
, lpi_bitmap
)) {
746 clear_bit(chunk
, lpi_bitmap
);
748 pr_err("Bad LPI chunk %d\n", chunk
);
752 spin_unlock(&lpi_lock
);
759 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
760 * deal with (one configuration byte per interrupt). PENDBASE has to
761 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
763 #define LPI_PROPBASE_SZ SZ_64K
764 #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
767 * This is how many bits of ID we need, including the useless ones.
769 #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
771 #define LPI_PROP_DEFAULT_PRIO 0xa0
773 static int __init
its_alloc_lpi_tables(void)
777 gic_rdists
->prop_page
= alloc_pages(GFP_NOWAIT
,
778 get_order(LPI_PROPBASE_SZ
));
779 if (!gic_rdists
->prop_page
) {
780 pr_err("Failed to allocate PROPBASE\n");
784 paddr
= page_to_phys(gic_rdists
->prop_page
);
785 pr_info("GIC: using LPI property table @%pa\n", &paddr
);
787 /* Priority 0xa0, Group-1, disabled */
788 memset(page_address(gic_rdists
->prop_page
),
789 LPI_PROP_DEFAULT_PRIO
| LPI_PROP_GROUP1
,
792 /* Make sure the GIC will observe the written configuration */
793 __flush_dcache_area(page_address(gic_rdists
->prop_page
), LPI_PROPBASE_SZ
);
798 static const char *its_base_type_string
[] = {
799 [GITS_BASER_TYPE_DEVICE
] = "Devices",
800 [GITS_BASER_TYPE_VCPU
] = "Virtual CPUs",
801 [GITS_BASER_TYPE_CPU
] = "Physical CPUs",
802 [GITS_BASER_TYPE_COLLECTION
] = "Interrupt Collections",
803 [GITS_BASER_TYPE_RESERVED5
] = "Reserved (5)",
804 [GITS_BASER_TYPE_RESERVED6
] = "Reserved (6)",
805 [GITS_BASER_TYPE_RESERVED7
] = "Reserved (7)",
808 static void its_free_tables(struct its_node
*its
)
812 for (i
= 0; i
< GITS_BASER_NR_REGS
; i
++) {
813 if (its
->tables
[i
].base
) {
814 free_pages((unsigned long)its
->tables
[i
].base
,
815 its
->tables
[i
].order
);
816 its
->tables
[i
].base
= NULL
;
821 static int its_alloc_tables(const char *node_name
, struct its_node
*its
)
826 u64 shr
= GITS_BASER_InnerShareable
;
831 if (its
->flags
& ITS_FLAGS_WORKAROUND_CAVIUM_22375
) {
833 * erratum 22375: only alloc 8MB table size
834 * erratum 24313: ignore memory access type
837 ids
= 0x14; /* 20 bits, 8MB */
839 cache
= GITS_BASER_WaWb
;
840 typer
= readq_relaxed(its
->base
+ GITS_TYPER
);
841 ids
= GITS_TYPER_DEVBITS(typer
);
844 for (i
= 0; i
< GITS_BASER_NR_REGS
; i
++) {
845 u64 val
= readq_relaxed(its
->base
+ GITS_BASER
+ i
* 8);
846 u64 type
= GITS_BASER_TYPE(val
);
847 u64 entry_size
= GITS_BASER_ENTRY_SIZE(val
);
848 int order
= get_order(psz
);
854 if (type
== GITS_BASER_TYPE_NONE
)
858 * Allocate as many entries as required to fit the
859 * range of device IDs that the ITS can grok... The ID
860 * space being incredibly sparse, this results in a
861 * massive waste of memory.
863 * For other tables, only allocate a single page.
865 if (type
== GITS_BASER_TYPE_DEVICE
) {
867 * 'order' was initialized earlier to the default page
868 * granule of the the ITS. We can't have an allocation
869 * smaller than that. If the requested allocation
870 * is smaller, round up to the default page granule.
872 order
= max(get_order((1UL << ids
) * entry_size
),
874 if (order
>= MAX_ORDER
) {
875 order
= MAX_ORDER
- 1;
876 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
881 alloc_size
= (1 << order
) * PAGE_SIZE
;
883 alloc_pages
= (alloc_size
/ psz
);
884 if (alloc_pages
> GITS_BASER_PAGES_MAX
) {
885 alloc_pages
= GITS_BASER_PAGES_MAX
;
886 order
= get_order(GITS_BASER_PAGES_MAX
* psz
);
887 pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
888 node_name
, order
, alloc_pages
);
891 base
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
, order
);
897 its
->tables
[i
].base
= base
;
898 its
->tables
[i
].order
= order
;
901 val
= (virt_to_phys(base
) |
902 (type
<< GITS_BASER_TYPE_SHIFT
) |
903 ((entry_size
- 1) << GITS_BASER_ENTRY_SIZE_SHIFT
) |
910 val
|= GITS_BASER_PAGE_SIZE_4K
;
913 val
|= GITS_BASER_PAGE_SIZE_16K
;
916 val
|= GITS_BASER_PAGE_SIZE_64K
;
920 val
|= alloc_pages
- 1;
922 writeq_relaxed(val
, its
->base
+ GITS_BASER
+ i
* 8);
923 tmp
= readq_relaxed(its
->base
+ GITS_BASER
+ i
* 8);
925 if ((val
^ tmp
) & GITS_BASER_SHAREABILITY_MASK
) {
927 * Shareability didn't stick. Just use
928 * whatever the read reported, which is likely
929 * to be the only thing this redistributor
930 * supports. If that's zero, make it
931 * non-cacheable as well.
933 shr
= tmp
& GITS_BASER_SHAREABILITY_MASK
;
935 cache
= GITS_BASER_nC
;
936 __flush_dcache_area(base
, alloc_size
);
941 if ((val
^ tmp
) & GITS_BASER_PAGE_SIZE_MASK
) {
943 * Page size didn't stick. Let's try a smaller
944 * size and retry. If we reach 4K, then
945 * something is horribly wrong...
947 free_pages((unsigned long)base
, order
);
948 its
->tables
[i
].base
= NULL
;
953 goto retry_alloc_baser
;
956 goto retry_alloc_baser
;
961 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
963 (unsigned long) val
, (unsigned long) tmp
);
968 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
969 (int)(alloc_size
/ entry_size
),
970 its_base_type_string
[type
],
971 (unsigned long)virt_to_phys(base
),
972 psz
/ SZ_1K
, (int)shr
>> GITS_BASER_SHAREABILITY_SHIFT
);
978 its_free_tables(its
);
983 static int its_alloc_collections(struct its_node
*its
)
985 its
->collections
= kzalloc(nr_cpu_ids
* sizeof(*its
->collections
),
987 if (!its
->collections
)
993 static void its_cpu_init_lpis(void)
995 void __iomem
*rbase
= gic_data_rdist_rd_base();
996 struct page
*pend_page
;
999 /* If we didn't allocate the pending table yet, do it now */
1000 pend_page
= gic_data_rdist()->pend_page
;
1004 * The pending pages have to be at least 64kB aligned,
1005 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1007 pend_page
= alloc_pages(GFP_NOWAIT
| __GFP_ZERO
,
1008 get_order(max(LPI_PENDBASE_SZ
, SZ_64K
)));
1010 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1011 smp_processor_id());
1015 /* Make sure the GIC will observe the zero-ed page */
1016 __flush_dcache_area(page_address(pend_page
), LPI_PENDBASE_SZ
);
1018 paddr
= page_to_phys(pend_page
);
1019 pr_info("CPU%d: using LPI pending table @%pa\n",
1020 smp_processor_id(), &paddr
);
1021 gic_data_rdist()->pend_page
= pend_page
;
1025 val
= readl_relaxed(rbase
+ GICR_CTLR
);
1026 val
&= ~GICR_CTLR_ENABLE_LPIS
;
1027 writel_relaxed(val
, rbase
+ GICR_CTLR
);
1030 * Make sure any change to the table is observable by the GIC.
1035 val
= (page_to_phys(gic_rdists
->prop_page
) |
1036 GICR_PROPBASER_InnerShareable
|
1037 GICR_PROPBASER_WaWb
|
1038 ((LPI_NRBITS
- 1) & GICR_PROPBASER_IDBITS_MASK
));
1040 writeq_relaxed(val
, rbase
+ GICR_PROPBASER
);
1041 tmp
= readq_relaxed(rbase
+ GICR_PROPBASER
);
1043 if ((tmp
^ val
) & GICR_PROPBASER_SHAREABILITY_MASK
) {
1044 if (!(tmp
& GICR_PROPBASER_SHAREABILITY_MASK
)) {
1046 * The HW reports non-shareable, we must
1047 * remove the cacheability attributes as
1050 val
&= ~(GICR_PROPBASER_SHAREABILITY_MASK
|
1051 GICR_PROPBASER_CACHEABILITY_MASK
);
1052 val
|= GICR_PROPBASER_nC
;
1053 writeq_relaxed(val
, rbase
+ GICR_PROPBASER
);
1055 pr_info_once("GIC: using cache flushing for LPI property table\n");
1056 gic_rdists
->flags
|= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING
;
1060 val
= (page_to_phys(pend_page
) |
1061 GICR_PENDBASER_InnerShareable
|
1062 GICR_PENDBASER_WaWb
);
1064 writeq_relaxed(val
, rbase
+ GICR_PENDBASER
);
1065 tmp
= readq_relaxed(rbase
+ GICR_PENDBASER
);
1067 if (!(tmp
& GICR_PENDBASER_SHAREABILITY_MASK
)) {
1069 * The HW reports non-shareable, we must remove the
1070 * cacheability attributes as well.
1072 val
&= ~(GICR_PENDBASER_SHAREABILITY_MASK
|
1073 GICR_PENDBASER_CACHEABILITY_MASK
);
1074 val
|= GICR_PENDBASER_nC
;
1075 writeq_relaxed(val
, rbase
+ GICR_PENDBASER
);
1079 val
= readl_relaxed(rbase
+ GICR_CTLR
);
1080 val
|= GICR_CTLR_ENABLE_LPIS
;
1081 writel_relaxed(val
, rbase
+ GICR_CTLR
);
1083 /* Make sure the GIC has seen the above */
1087 static void its_cpu_init_collection(void)
1089 struct its_node
*its
;
1092 spin_lock(&its_lock
);
1093 cpu
= smp_processor_id();
1095 list_for_each_entry(its
, &its_nodes
, entry
) {
1099 * We now have to bind each collection to its target
1102 if (readq_relaxed(its
->base
+ GITS_TYPER
) & GITS_TYPER_PTA
) {
1104 * This ITS wants the physical address of the
1107 target
= gic_data_rdist()->phys_base
;
1110 * This ITS wants a linear CPU number.
1112 target
= readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER
);
1113 target
= GICR_TYPER_CPU_NUMBER(target
) << 16;
1116 /* Perform collection mapping */
1117 its
->collections
[cpu
].target_address
= target
;
1118 its
->collections
[cpu
].col_id
= cpu
;
1120 its_send_mapc(its
, &its
->collections
[cpu
], 1);
1121 its_send_invall(its
, &its
->collections
[cpu
]);
1124 spin_unlock(&its_lock
);
1127 static struct its_device
*its_find_device(struct its_node
*its
, u32 dev_id
)
1129 struct its_device
*its_dev
= NULL
, *tmp
;
1130 unsigned long flags
;
1132 raw_spin_lock_irqsave(&its
->lock
, flags
);
1134 list_for_each_entry(tmp
, &its
->its_device_list
, entry
) {
1135 if (tmp
->device_id
== dev_id
) {
1141 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
1146 static struct its_device
*its_create_device(struct its_node
*its
, u32 dev_id
,
1149 struct its_device
*dev
;
1150 unsigned long *lpi_map
;
1151 unsigned long flags
;
1152 u16
*col_map
= NULL
;
1159 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1161 * At least one bit of EventID is being used, hence a minimum
1162 * of two entries. No, the architecture doesn't let you
1163 * express an ITT with a single entry.
1165 nr_ites
= max(2UL, roundup_pow_of_two(nvecs
));
1166 sz
= nr_ites
* its
->ite_size
;
1167 sz
= max(sz
, ITS_ITT_ALIGN
) + ITS_ITT_ALIGN
- 1;
1168 itt
= kzalloc(sz
, GFP_KERNEL
);
1169 lpi_map
= its_lpi_alloc_chunks(nvecs
, &lpi_base
, &nr_lpis
);
1171 col_map
= kzalloc(sizeof(*col_map
) * nr_lpis
, GFP_KERNEL
);
1173 if (!dev
|| !itt
|| !lpi_map
|| !col_map
) {
1181 __flush_dcache_area(itt
, sz
);
1185 dev
->nr_ites
= nr_ites
;
1186 dev
->event_map
.lpi_map
= lpi_map
;
1187 dev
->event_map
.col_map
= col_map
;
1188 dev
->event_map
.lpi_base
= lpi_base
;
1189 dev
->event_map
.nr_lpis
= nr_lpis
;
1190 dev
->device_id
= dev_id
;
1191 INIT_LIST_HEAD(&dev
->entry
);
1193 raw_spin_lock_irqsave(&its
->lock
, flags
);
1194 list_add(&dev
->entry
, &its
->its_device_list
);
1195 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
1197 /* Map device to its ITT */
1198 its_send_mapd(dev
, 1);
1203 static void its_free_device(struct its_device
*its_dev
)
1205 unsigned long flags
;
1207 raw_spin_lock_irqsave(&its_dev
->its
->lock
, flags
);
1208 list_del(&its_dev
->entry
);
1209 raw_spin_unlock_irqrestore(&its_dev
->its
->lock
, flags
);
1210 kfree(its_dev
->itt
);
1214 static int its_alloc_device_irq(struct its_device
*dev
, irq_hw_number_t
*hwirq
)
1218 idx
= find_first_zero_bit(dev
->event_map
.lpi_map
,
1219 dev
->event_map
.nr_lpis
);
1220 if (idx
== dev
->event_map
.nr_lpis
)
1223 *hwirq
= dev
->event_map
.lpi_base
+ idx
;
1224 set_bit(idx
, dev
->event_map
.lpi_map
);
1229 static int its_msi_prepare(struct irq_domain
*domain
, struct device
*dev
,
1230 int nvec
, msi_alloc_info_t
*info
)
1232 struct its_node
*its
;
1233 struct its_device
*its_dev
;
1234 struct msi_domain_info
*msi_info
;
1238 * We ignore "dev" entierely, and rely on the dev_id that has
1239 * been passed via the scratchpad. This limits this domain's
1240 * usefulness to upper layers that definitely know that they
1241 * are built on top of the ITS.
1243 dev_id
= info
->scratchpad
[0].ul
;
1245 msi_info
= msi_get_domain_info(domain
);
1246 its
= msi_info
->data
;
1248 its_dev
= its_find_device(its
, dev_id
);
1251 * We already have seen this ID, probably through
1252 * another alias (PCI bridge of some sort). No need to
1253 * create the device.
1255 pr_debug("Reusing ITT for devID %x\n", dev_id
);
1259 its_dev
= its_create_device(its
, dev_id
, nvec
);
1263 pr_debug("ITT %d entries, %d bits\n", nvec
, ilog2(nvec
));
1265 info
->scratchpad
[0].ptr
= its_dev
;
1269 static struct msi_domain_ops its_msi_domain_ops
= {
1270 .msi_prepare
= its_msi_prepare
,
1273 static int its_irq_gic_domain_alloc(struct irq_domain
*domain
,
1275 irq_hw_number_t hwirq
)
1277 struct irq_fwspec fwspec
;
1279 if (irq_domain_get_of_node(domain
->parent
)) {
1280 fwspec
.fwnode
= domain
->parent
->fwnode
;
1281 fwspec
.param_count
= 3;
1282 fwspec
.param
[0] = GIC_IRQ_TYPE_LPI
;
1283 fwspec
.param
[1] = hwirq
;
1284 fwspec
.param
[2] = IRQ_TYPE_EDGE_RISING
;
1289 return irq_domain_alloc_irqs_parent(domain
, virq
, 1, &fwspec
);
1292 static int its_irq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
1293 unsigned int nr_irqs
, void *args
)
1295 msi_alloc_info_t
*info
= args
;
1296 struct its_device
*its_dev
= info
->scratchpad
[0].ptr
;
1297 irq_hw_number_t hwirq
;
1301 for (i
= 0; i
< nr_irqs
; i
++) {
1302 err
= its_alloc_device_irq(its_dev
, &hwirq
);
1306 err
= its_irq_gic_domain_alloc(domain
, virq
+ i
, hwirq
);
1310 irq_domain_set_hwirq_and_chip(domain
, virq
+ i
,
1311 hwirq
, &its_irq_chip
, its_dev
);
1312 pr_debug("ID:%d pID:%d vID:%d\n",
1313 (int)(hwirq
- its_dev
->event_map
.lpi_base
),
1314 (int) hwirq
, virq
+ i
);
1320 static void its_irq_domain_activate(struct irq_domain
*domain
,
1323 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1324 u32 event
= its_get_event_id(d
);
1326 /* Bind the LPI to the first possible CPU */
1327 its_dev
->event_map
.col_map
[event
] = cpumask_first(cpu_online_mask
);
1329 /* Map the GIC IRQ and event to the device */
1330 its_send_mapvi(its_dev
, d
->hwirq
, event
);
1333 static void its_irq_domain_deactivate(struct irq_domain
*domain
,
1336 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1337 u32 event
= its_get_event_id(d
);
1339 /* Stop the delivery of interrupts */
1340 its_send_discard(its_dev
, event
);
1343 static void its_irq_domain_free(struct irq_domain
*domain
, unsigned int virq
,
1344 unsigned int nr_irqs
)
1346 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
);
1347 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1350 for (i
= 0; i
< nr_irqs
; i
++) {
1351 struct irq_data
*data
= irq_domain_get_irq_data(domain
,
1353 u32 event
= its_get_event_id(data
);
1355 /* Mark interrupt index as unused */
1356 clear_bit(event
, its_dev
->event_map
.lpi_map
);
1358 /* Nuke the entry in the domain */
1359 irq_domain_reset_irq_data(data
);
1362 /* If all interrupts have been freed, start mopping the floor */
1363 if (bitmap_empty(its_dev
->event_map
.lpi_map
,
1364 its_dev
->event_map
.nr_lpis
)) {
1365 its_lpi_free(&its_dev
->event_map
);
1367 /* Unmap device/itt */
1368 its_send_mapd(its_dev
, 0);
1369 its_free_device(its_dev
);
1372 irq_domain_free_irqs_parent(domain
, virq
, nr_irqs
);
1375 static const struct irq_domain_ops its_domain_ops
= {
1376 .alloc
= its_irq_domain_alloc
,
1377 .free
= its_irq_domain_free
,
1378 .activate
= its_irq_domain_activate
,
1379 .deactivate
= its_irq_domain_deactivate
,
1382 static int its_force_quiescent(void __iomem
*base
)
1384 u32 count
= 1000000; /* 1s */
1387 val
= readl_relaxed(base
+ GITS_CTLR
);
1388 if (val
& GITS_CTLR_QUIESCENT
)
1391 /* Disable the generation of all interrupts to this ITS */
1392 val
&= ~GITS_CTLR_ENABLE
;
1393 writel_relaxed(val
, base
+ GITS_CTLR
);
1395 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1397 val
= readl_relaxed(base
+ GITS_CTLR
);
1398 if (val
& GITS_CTLR_QUIESCENT
)
1410 static void __maybe_unused
its_enable_quirk_cavium_22375(void *data
)
1412 struct its_node
*its
= data
;
1414 its
->flags
|= ITS_FLAGS_WORKAROUND_CAVIUM_22375
;
1417 static const struct gic_quirk its_quirks
[] = {
1418 #ifdef CONFIG_CAVIUM_ERRATUM_22375
1420 .desc
= "ITS: Cavium errata 22375, 24313",
1421 .iidr
= 0xa100034c, /* ThunderX pass 1.x */
1423 .init
= its_enable_quirk_cavium_22375
,
1430 static void its_enable_quirks(struct its_node
*its
)
1432 u32 iidr
= readl_relaxed(its
->base
+ GITS_IIDR
);
1434 gic_enable_quirks(iidr
, its_quirks
, its
);
1437 static int its_probe(struct device_node
*node
, struct irq_domain
*parent
)
1439 struct resource res
;
1440 struct its_node
*its
;
1441 void __iomem
*its_base
;
1442 struct irq_domain
*inner_domain
;
1447 err
= of_address_to_resource(node
, 0, &res
);
1449 pr_warn("%s: no regs?\n", node
->full_name
);
1453 its_base
= ioremap(res
.start
, resource_size(&res
));
1455 pr_warn("%s: unable to map registers\n", node
->full_name
);
1459 val
= readl_relaxed(its_base
+ GITS_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
1460 if (val
!= 0x30 && val
!= 0x40) {
1461 pr_warn("%s: no ITS detected, giving up\n", node
->full_name
);
1466 err
= its_force_quiescent(its_base
);
1468 pr_warn("%s: failed to quiesce, giving up\n",
1473 pr_info("ITS: %s\n", node
->full_name
);
1475 its
= kzalloc(sizeof(*its
), GFP_KERNEL
);
1481 raw_spin_lock_init(&its
->lock
);
1482 INIT_LIST_HEAD(&its
->entry
);
1483 INIT_LIST_HEAD(&its
->its_device_list
);
1484 its
->base
= its_base
;
1485 its
->phys_base
= res
.start
;
1486 its
->ite_size
= ((readl_relaxed(its_base
+ GITS_TYPER
) >> 4) & 0xf) + 1;
1488 its
->cmd_base
= kzalloc(ITS_CMD_QUEUE_SZ
, GFP_KERNEL
);
1489 if (!its
->cmd_base
) {
1493 its
->cmd_write
= its
->cmd_base
;
1495 its_enable_quirks(its
);
1497 err
= its_alloc_tables(node
->full_name
, its
);
1501 err
= its_alloc_collections(its
);
1503 goto out_free_tables
;
1505 baser
= (virt_to_phys(its
->cmd_base
) |
1507 GITS_CBASER_InnerShareable
|
1508 (ITS_CMD_QUEUE_SZ
/ SZ_4K
- 1) |
1511 writeq_relaxed(baser
, its
->base
+ GITS_CBASER
);
1512 tmp
= readq_relaxed(its
->base
+ GITS_CBASER
);
1514 if ((tmp
^ baser
) & GITS_CBASER_SHAREABILITY_MASK
) {
1515 if (!(tmp
& GITS_CBASER_SHAREABILITY_MASK
)) {
1517 * The HW reports non-shareable, we must
1518 * remove the cacheability attributes as
1521 baser
&= ~(GITS_CBASER_SHAREABILITY_MASK
|
1522 GITS_CBASER_CACHEABILITY_MASK
);
1523 baser
|= GITS_CBASER_nC
;
1524 writeq_relaxed(baser
, its
->base
+ GITS_CBASER
);
1526 pr_info("ITS: using cache flushing for cmd queue\n");
1527 its
->flags
|= ITS_FLAGS_CMDQ_NEEDS_FLUSHING
;
1530 writeq_relaxed(0, its
->base
+ GITS_CWRITER
);
1531 writel_relaxed(GITS_CTLR_ENABLE
, its
->base
+ GITS_CTLR
);
1533 if (of_property_read_bool(node
, "msi-controller")) {
1534 struct msi_domain_info
*info
;
1536 info
= kzalloc(sizeof(*info
), GFP_KERNEL
);
1539 goto out_free_tables
;
1542 inner_domain
= irq_domain_add_tree(node
, &its_domain_ops
, its
);
1543 if (!inner_domain
) {
1546 goto out_free_tables
;
1549 inner_domain
->parent
= parent
;
1550 inner_domain
->bus_token
= DOMAIN_BUS_NEXUS
;
1551 info
->ops
= &its_msi_domain_ops
;
1553 inner_domain
->host_data
= info
;
1556 spin_lock(&its_lock
);
1557 list_add(&its
->entry
, &its_nodes
);
1558 spin_unlock(&its_lock
);
1563 its_free_tables(its
);
1565 kfree(its
->cmd_base
);
1570 pr_err("ITS: failed probing %s (%d)\n", node
->full_name
, err
);
1574 static bool gic_rdists_supports_plpis(void)
1576 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER
) & GICR_TYPER_PLPIS
);
1579 int its_cpu_init(void)
1581 if (!list_empty(&its_nodes
)) {
1582 if (!gic_rdists_supports_plpis()) {
1583 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1586 its_cpu_init_lpis();
1587 its_cpu_init_collection();
1593 static struct of_device_id its_device_id
[] = {
1594 { .compatible
= "arm,gic-v3-its", },
1598 int its_init(struct device_node
*node
, struct rdists
*rdists
,
1599 struct irq_domain
*parent_domain
)
1601 struct device_node
*np
;
1603 for (np
= of_find_matching_node(node
, its_device_id
); np
;
1604 np
= of_find_matching_node(np
, its_device_id
)) {
1605 its_probe(np
, parent_domain
);
1608 if (list_empty(&its_nodes
)) {
1609 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1613 gic_rdists
= rdists
;
1614 gic_root_node
= node
;
1616 its_alloc_lpi_tables();
1617 its_lpi_init(rdists
->id_bits
);