1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx SoCs TCU IRQ driver
4 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
8 #include <linux/interrupt.h>
9 #include <linux/irqchip.h>
10 #include <linux/irqchip/chained_irq.h>
11 #include <linux/mfd/ingenic-tcu.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of_irq.h>
14 #include <linux/regmap.h>
19 struct irq_domain
*domain
;
20 unsigned int nb_parent_irqs
;
24 static void ingenic_tcu_intc_cascade(struct irq_desc
*desc
)
26 struct irq_chip
*irq_chip
= irq_data_get_irq_chip(&desc
->irq_data
);
27 struct irq_domain
*domain
= irq_desc_get_handler_data(desc
);
28 struct irq_chip_generic
*gc
= irq_get_domain_generic_chip(domain
, 0);
29 struct regmap
*map
= gc
->private;
30 uint32_t irq_reg
, irq_mask
;
33 regmap_read(map
, TCU_REG_TFR
, &irq_reg
);
34 regmap_read(map
, TCU_REG_TMR
, &irq_mask
);
36 chained_irq_enter(irq_chip
, desc
);
40 for_each_set_bit(i
, (unsigned long *)&irq_reg
, 32)
41 generic_handle_irq(irq_linear_revmap(domain
, i
));
43 chained_irq_exit(irq_chip
, desc
);
46 static void ingenic_tcu_gc_unmask_enable_reg(struct irq_data
*d
)
48 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
49 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
50 struct regmap
*map
= gc
->private;
54 regmap_write(map
, ct
->regs
.ack
, mask
);
55 regmap_write(map
, ct
->regs
.enable
, mask
);
56 *ct
->mask_cache
|= mask
;
60 static void ingenic_tcu_gc_mask_disable_reg(struct irq_data
*d
)
62 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
63 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
64 struct regmap
*map
= gc
->private;
68 regmap_write(map
, ct
->regs
.disable
, mask
);
69 *ct
->mask_cache
&= ~mask
;
73 static void ingenic_tcu_gc_mask_disable_reg_and_ack(struct irq_data
*d
)
75 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
76 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
77 struct regmap
*map
= gc
->private;
81 regmap_write(map
, ct
->regs
.ack
, mask
);
82 regmap_write(map
, ct
->regs
.disable
, mask
);
86 static int __init
ingenic_tcu_irq_init(struct device_node
*np
,
87 struct device_node
*parent
)
89 struct irq_chip_generic
*gc
;
90 struct irq_chip_type
*ct
;
91 struct ingenic_tcu
*tcu
;
96 map
= device_node_to_regmap(np
);
100 tcu
= kzalloc(sizeof(*tcu
), GFP_KERNEL
);
106 irqs
= of_property_count_elems_of_size(np
, "interrupts", sizeof(u32
));
107 if (irqs
< 0 || irqs
> ARRAY_SIZE(tcu
->parent_irqs
)) {
108 pr_crit("%s: Invalid 'interrupts' property\n", __func__
);
113 tcu
->nb_parent_irqs
= irqs
;
115 tcu
->domain
= irq_domain_add_linear(np
, 32, &irq_generic_chip_ops
,
122 ret
= irq_alloc_domain_generic_chips(tcu
->domain
, 32, 1, "TCU",
124 IRQ_NOPROBE
| IRQ_LEVEL
, 0);
126 pr_crit("%s: Invalid 'interrupts' property\n", __func__
);
127 goto out_domain_remove
;
130 gc
= irq_get_domain_generic_chip(tcu
->domain
, 0);
133 gc
->wake_enabled
= IRQ_MSK(32);
134 gc
->private = tcu
->map
;
136 ct
->regs
.disable
= TCU_REG_TMSR
;
137 ct
->regs
.enable
= TCU_REG_TMCR
;
138 ct
->regs
.ack
= TCU_REG_TFCR
;
139 ct
->chip
.irq_unmask
= ingenic_tcu_gc_unmask_enable_reg
;
140 ct
->chip
.irq_mask
= ingenic_tcu_gc_mask_disable_reg
;
141 ct
->chip
.irq_mask_ack
= ingenic_tcu_gc_mask_disable_reg_and_ack
;
142 ct
->chip
.flags
= IRQCHIP_MASK_ON_SUSPEND
| IRQCHIP_SKIP_SET_WAKE
;
144 /* Mask all IRQs by default */
145 regmap_write(tcu
->map
, TCU_REG_TMSR
, IRQ_MSK(32));
148 * On JZ4740, timer 0 and timer 1 have their own interrupt line;
149 * timers 2-7 share one interrupt.
150 * On SoCs >= JZ4770, timer 5 has its own interrupt line;
151 * timers 0-4 and 6-7 share one single interrupt.
153 * To keep things simple, we just register the same handler to
154 * all parent interrupts. The handler will properly detect which
155 * channel fired the interrupt.
157 for (i
= 0; i
< irqs
; i
++) {
158 tcu
->parent_irqs
[i
] = irq_of_parse_and_map(np
, i
);
159 if (!tcu
->parent_irqs
[i
]) {
164 irq_set_chained_handler_and_data(tcu
->parent_irqs
[i
],
165 ingenic_tcu_intc_cascade
,
173 irq_dispose_mapping(tcu
->parent_irqs
[i
- 1]);
175 irq_domain_remove(tcu
->domain
);
180 IRQCHIP_DECLARE(jz4740_tcu_irq
, "ingenic,jz4740-tcu", ingenic_tcu_irq_init
);
181 IRQCHIP_DECLARE(jz4725b_tcu_irq
, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init
);
182 IRQCHIP_DECLARE(jz4770_tcu_irq
, "ingenic,jz4770-tcu", ingenic_tcu_irq_init
);