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[mirror_ubuntu-hirsute-kernel.git] / drivers / irqchip / irq-mips-gic.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */
9 #include <linux/bitmap.h>
10 #include <linux/clocksource.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/mips-gic.h>
15 #include <linux/of_address.h>
16 #include <linux/sched.h>
17 #include <linux/smp.h>
18
19 #include <asm/mips-cm.h>
20 #include <asm/setup.h>
21 #include <asm/traps.h>
22
23 #include <dt-bindings/interrupt-controller/mips-gic.h>
24
25 #include "irqchip.h"
26
27 unsigned int gic_present;
28
29 struct gic_pcpu_mask {
30 DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
31 };
32
33 static void __iomem *gic_base;
34 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
35 static DEFINE_SPINLOCK(gic_lock);
36 static struct irq_domain *gic_irq_domain;
37 static int gic_shared_intrs;
38 static int gic_vpes;
39 static unsigned int gic_cpu_pin;
40 static unsigned int timer_cpu_pin;
41 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
42
43 static void __gic_irq_dispatch(void);
44
45 static inline unsigned int gic_read(unsigned int reg)
46 {
47 return __raw_readl(gic_base + reg);
48 }
49
50 static inline void gic_write(unsigned int reg, unsigned int val)
51 {
52 __raw_writel(val, gic_base + reg);
53 }
54
55 static inline void gic_update_bits(unsigned int reg, unsigned int mask,
56 unsigned int val)
57 {
58 unsigned int regval;
59
60 regval = gic_read(reg);
61 regval &= ~mask;
62 regval |= val;
63 gic_write(reg, regval);
64 }
65
66 static inline void gic_reset_mask(unsigned int intr)
67 {
68 gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
69 1 << GIC_INTR_BIT(intr));
70 }
71
72 static inline void gic_set_mask(unsigned int intr)
73 {
74 gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
75 1 << GIC_INTR_BIT(intr));
76 }
77
78 static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
79 {
80 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
81 GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
82 pol << GIC_INTR_BIT(intr));
83 }
84
85 static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
86 {
87 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
88 GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
89 trig << GIC_INTR_BIT(intr));
90 }
91
92 static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
93 {
94 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
95 1 << GIC_INTR_BIT(intr),
96 dual << GIC_INTR_BIT(intr));
97 }
98
99 static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
100 {
101 gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
102 GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
103 }
104
105 static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
106 {
107 gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
108 GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
109 GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
110 }
111
112 #ifdef CONFIG_CLKSRC_MIPS_GIC
113 cycle_t gic_read_count(void)
114 {
115 unsigned int hi, hi2, lo;
116
117 do {
118 hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
119 lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
120 hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
121 } while (hi2 != hi);
122
123 return (((cycle_t) hi) << 32) + lo;
124 }
125
126 unsigned int gic_get_count_width(void)
127 {
128 unsigned int bits, config;
129
130 config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
131 bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
132 GIC_SH_CONFIG_COUNTBITS_SHF);
133
134 return bits;
135 }
136
137 void gic_write_compare(cycle_t cnt)
138 {
139 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
140 (int)(cnt >> 32));
141 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
142 (int)(cnt & 0xffffffff));
143 }
144
145 void gic_write_cpu_compare(cycle_t cnt, int cpu)
146 {
147 unsigned long flags;
148
149 local_irq_save(flags);
150
151 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
152 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
153 (int)(cnt >> 32));
154 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
155 (int)(cnt & 0xffffffff));
156
157 local_irq_restore(flags);
158 }
159
160 cycle_t gic_read_compare(void)
161 {
162 unsigned int hi, lo;
163
164 hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
165 lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
166
167 return (((cycle_t) hi) << 32) + lo;
168 }
169
170 void gic_start_count(void)
171 {
172 u32 gicconfig;
173
174 /* Start the counter */
175 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
176 gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
177 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
178 }
179
180 void gic_stop_count(void)
181 {
182 u32 gicconfig;
183
184 /* Stop the counter */
185 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
186 gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
187 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
188 }
189
190 #endif
191
192 static bool gic_local_irq_is_routable(int intr)
193 {
194 u32 vpe_ctl;
195
196 /* All local interrupts are routable in EIC mode. */
197 if (cpu_has_veic)
198 return true;
199
200 vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
201 switch (intr) {
202 case GIC_LOCAL_INT_TIMER:
203 return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
204 case GIC_LOCAL_INT_PERFCTR:
205 return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
206 case GIC_LOCAL_INT_FDC:
207 return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
208 case GIC_LOCAL_INT_SWINT0:
209 case GIC_LOCAL_INT_SWINT1:
210 return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
211 default:
212 return true;
213 }
214 }
215
216 static void gic_bind_eic_interrupt(int irq, int set)
217 {
218 /* Convert irq vector # to hw int # */
219 irq -= GIC_PIN_TO_VEC_OFFSET;
220
221 /* Set irq to use shadow set */
222 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
223 GIC_VPE_EIC_SS(irq), set);
224 }
225
226 void gic_send_ipi(unsigned int intr)
227 {
228 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr));
229 }
230
231 int gic_get_c0_compare_int(void)
232 {
233 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
234 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
235 return irq_create_mapping(gic_irq_domain,
236 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
237 }
238
239 int gic_get_c0_perfcount_int(void)
240 {
241 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
242 /* Is the performance counter shared with the timer? */
243 if (cp0_perfcount_irq < 0)
244 return -1;
245 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
246 }
247 return irq_create_mapping(gic_irq_domain,
248 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
249 }
250
251 int gic_get_c0_fdc_int(void)
252 {
253 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
254 /* Is the FDC IRQ even present? */
255 if (cp0_fdc_irq < 0)
256 return -1;
257 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
258 }
259
260 /*
261 * Some cores claim the FDC is routable but it doesn't actually seem to
262 * be connected.
263 */
264 switch (current_cpu_type()) {
265 case CPU_INTERAPTIV:
266 case CPU_PROAPTIV:
267 return -1;
268 }
269
270 return irq_create_mapping(gic_irq_domain,
271 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
272 }
273
274 static void gic_handle_shared_int(bool chained)
275 {
276 unsigned int i, intr, virq;
277 unsigned long *pcpu_mask;
278 unsigned long pending_reg, intrmask_reg;
279 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
280 DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
281
282 /* Get per-cpu bitmaps */
283 pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
284
285 pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
286 intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
287
288 for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
289 pending[i] = gic_read(pending_reg);
290 intrmask[i] = gic_read(intrmask_reg);
291 pending_reg += 0x4;
292 intrmask_reg += 0x4;
293 }
294
295 bitmap_and(pending, pending, intrmask, gic_shared_intrs);
296 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
297
298 intr = find_first_bit(pending, gic_shared_intrs);
299 while (intr != gic_shared_intrs) {
300 virq = irq_linear_revmap(gic_irq_domain,
301 GIC_SHARED_TO_HWIRQ(intr));
302 if (chained)
303 generic_handle_irq(virq);
304 else
305 do_IRQ(virq);
306
307 /* go to next pending bit */
308 bitmap_clear(pending, intr, 1);
309 intr = find_first_bit(pending, gic_shared_intrs);
310 }
311 }
312
313 static void gic_mask_irq(struct irq_data *d)
314 {
315 gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
316 }
317
318 static void gic_unmask_irq(struct irq_data *d)
319 {
320 gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
321 }
322
323 static void gic_ack_irq(struct irq_data *d)
324 {
325 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
326
327 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
328 }
329
330 static int gic_set_type(struct irq_data *d, unsigned int type)
331 {
332 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
333 unsigned long flags;
334 bool is_edge;
335
336 spin_lock_irqsave(&gic_lock, flags);
337 switch (type & IRQ_TYPE_SENSE_MASK) {
338 case IRQ_TYPE_EDGE_FALLING:
339 gic_set_polarity(irq, GIC_POL_NEG);
340 gic_set_trigger(irq, GIC_TRIG_EDGE);
341 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
342 is_edge = true;
343 break;
344 case IRQ_TYPE_EDGE_RISING:
345 gic_set_polarity(irq, GIC_POL_POS);
346 gic_set_trigger(irq, GIC_TRIG_EDGE);
347 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
348 is_edge = true;
349 break;
350 case IRQ_TYPE_EDGE_BOTH:
351 /* polarity is irrelevant in this case */
352 gic_set_trigger(irq, GIC_TRIG_EDGE);
353 gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
354 is_edge = true;
355 break;
356 case IRQ_TYPE_LEVEL_LOW:
357 gic_set_polarity(irq, GIC_POL_NEG);
358 gic_set_trigger(irq, GIC_TRIG_LEVEL);
359 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
360 is_edge = false;
361 break;
362 case IRQ_TYPE_LEVEL_HIGH:
363 default:
364 gic_set_polarity(irq, GIC_POL_POS);
365 gic_set_trigger(irq, GIC_TRIG_LEVEL);
366 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
367 is_edge = false;
368 break;
369 }
370
371 if (is_edge) {
372 __irq_set_chip_handler_name_locked(d->irq,
373 &gic_edge_irq_controller,
374 handle_edge_irq, NULL);
375 } else {
376 __irq_set_chip_handler_name_locked(d->irq,
377 &gic_level_irq_controller,
378 handle_level_irq, NULL);
379 }
380 spin_unlock_irqrestore(&gic_lock, flags);
381
382 return 0;
383 }
384
385 #ifdef CONFIG_SMP
386 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
387 bool force)
388 {
389 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
390 cpumask_t tmp = CPU_MASK_NONE;
391 unsigned long flags;
392 int i;
393
394 cpumask_and(&tmp, cpumask, cpu_online_mask);
395 if (cpumask_empty(&tmp))
396 return -EINVAL;
397
398 /* Assumption : cpumask refers to a single CPU */
399 spin_lock_irqsave(&gic_lock, flags);
400
401 /* Re-route this IRQ */
402 gic_map_to_vpe(irq, cpumask_first(&tmp));
403
404 /* Update the pcpu_masks */
405 for (i = 0; i < NR_CPUS; i++)
406 clear_bit(irq, pcpu_masks[i].pcpu_mask);
407 set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask);
408
409 cpumask_copy(d->affinity, cpumask);
410 spin_unlock_irqrestore(&gic_lock, flags);
411
412 return IRQ_SET_MASK_OK_NOCOPY;
413 }
414 #endif
415
416 static struct irq_chip gic_level_irq_controller = {
417 .name = "MIPS GIC",
418 .irq_mask = gic_mask_irq,
419 .irq_unmask = gic_unmask_irq,
420 .irq_set_type = gic_set_type,
421 #ifdef CONFIG_SMP
422 .irq_set_affinity = gic_set_affinity,
423 #endif
424 };
425
426 static struct irq_chip gic_edge_irq_controller = {
427 .name = "MIPS GIC",
428 .irq_ack = gic_ack_irq,
429 .irq_mask = gic_mask_irq,
430 .irq_unmask = gic_unmask_irq,
431 .irq_set_type = gic_set_type,
432 #ifdef CONFIG_SMP
433 .irq_set_affinity = gic_set_affinity,
434 #endif
435 };
436
437 static void gic_handle_local_int(bool chained)
438 {
439 unsigned long pending, masked;
440 unsigned int intr, virq;
441
442 pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
443 masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
444
445 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
446
447 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
448 while (intr != GIC_NUM_LOCAL_INTRS) {
449 virq = irq_linear_revmap(gic_irq_domain,
450 GIC_LOCAL_TO_HWIRQ(intr));
451 if (chained)
452 generic_handle_irq(virq);
453 else
454 do_IRQ(virq);
455
456 /* go to next pending bit */
457 bitmap_clear(&pending, intr, 1);
458 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
459 }
460 }
461
462 static void gic_mask_local_irq(struct irq_data *d)
463 {
464 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
465
466 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
467 }
468
469 static void gic_unmask_local_irq(struct irq_data *d)
470 {
471 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
472
473 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
474 }
475
476 static struct irq_chip gic_local_irq_controller = {
477 .name = "MIPS GIC Local",
478 .irq_mask = gic_mask_local_irq,
479 .irq_unmask = gic_unmask_local_irq,
480 };
481
482 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
483 {
484 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
485 int i;
486 unsigned long flags;
487
488 spin_lock_irqsave(&gic_lock, flags);
489 for (i = 0; i < gic_vpes; i++) {
490 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
491 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
492 }
493 spin_unlock_irqrestore(&gic_lock, flags);
494 }
495
496 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
497 {
498 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
499 int i;
500 unsigned long flags;
501
502 spin_lock_irqsave(&gic_lock, flags);
503 for (i = 0; i < gic_vpes; i++) {
504 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
505 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
506 }
507 spin_unlock_irqrestore(&gic_lock, flags);
508 }
509
510 static struct irq_chip gic_all_vpes_local_irq_controller = {
511 .name = "MIPS GIC Local",
512 .irq_mask = gic_mask_local_irq_all_vpes,
513 .irq_unmask = gic_unmask_local_irq_all_vpes,
514 };
515
516 static void __gic_irq_dispatch(void)
517 {
518 gic_handle_local_int(false);
519 gic_handle_shared_int(false);
520 }
521
522 static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc)
523 {
524 gic_handle_local_int(true);
525 gic_handle_shared_int(true);
526 }
527
528 #ifdef CONFIG_MIPS_GIC_IPI
529 static int gic_resched_int_base;
530 static int gic_call_int_base;
531
532 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
533 {
534 return gic_resched_int_base + cpu;
535 }
536
537 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
538 {
539 return gic_call_int_base + cpu;
540 }
541
542 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
543 {
544 scheduler_ipi();
545
546 return IRQ_HANDLED;
547 }
548
549 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
550 {
551 smp_call_function_interrupt();
552
553 return IRQ_HANDLED;
554 }
555
556 static struct irqaction irq_resched = {
557 .handler = ipi_resched_interrupt,
558 .flags = IRQF_PERCPU,
559 .name = "IPI resched"
560 };
561
562 static struct irqaction irq_call = {
563 .handler = ipi_call_interrupt,
564 .flags = IRQF_PERCPU,
565 .name = "IPI call"
566 };
567
568 static __init void gic_ipi_init_one(unsigned int intr, int cpu,
569 struct irqaction *action)
570 {
571 int virq = irq_create_mapping(gic_irq_domain,
572 GIC_SHARED_TO_HWIRQ(intr));
573 int i;
574
575 gic_map_to_vpe(intr, cpu);
576 for (i = 0; i < NR_CPUS; i++)
577 clear_bit(intr, pcpu_masks[i].pcpu_mask);
578 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
579
580 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
581
582 irq_set_handler(virq, handle_percpu_irq);
583 setup_irq(virq, action);
584 }
585
586 static __init void gic_ipi_init(void)
587 {
588 int i;
589
590 /* Use last 2 * NR_CPUS interrupts as IPIs */
591 gic_resched_int_base = gic_shared_intrs - nr_cpu_ids;
592 gic_call_int_base = gic_resched_int_base - nr_cpu_ids;
593
594 for (i = 0; i < nr_cpu_ids; i++) {
595 gic_ipi_init_one(gic_call_int_base + i, i, &irq_call);
596 gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched);
597 }
598 }
599 #else
600 static inline void gic_ipi_init(void)
601 {
602 }
603 #endif
604
605 static void __init gic_basic_init(void)
606 {
607 unsigned int i;
608
609 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
610
611 /* Setup defaults */
612 for (i = 0; i < gic_shared_intrs; i++) {
613 gic_set_polarity(i, GIC_POL_POS);
614 gic_set_trigger(i, GIC_TRIG_LEVEL);
615 gic_reset_mask(i);
616 }
617
618 for (i = 0; i < gic_vpes; i++) {
619 unsigned int j;
620
621 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
622 for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
623 if (!gic_local_irq_is_routable(j))
624 continue;
625 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
626 }
627 }
628 }
629
630 static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
631 irq_hw_number_t hw)
632 {
633 int intr = GIC_HWIRQ_TO_LOCAL(hw);
634 int ret = 0;
635 int i;
636 unsigned long flags;
637
638 if (!gic_local_irq_is_routable(intr))
639 return -EPERM;
640
641 /*
642 * HACK: These are all really percpu interrupts, but the rest
643 * of the MIPS kernel code does not use the percpu IRQ API for
644 * the CP0 timer and performance counter interrupts.
645 */
646 switch (intr) {
647 case GIC_LOCAL_INT_TIMER:
648 case GIC_LOCAL_INT_PERFCTR:
649 case GIC_LOCAL_INT_FDC:
650 irq_set_chip_and_handler(virq,
651 &gic_all_vpes_local_irq_controller,
652 handle_percpu_irq);
653 break;
654 default:
655 irq_set_chip_and_handler(virq,
656 &gic_local_irq_controller,
657 handle_percpu_devid_irq);
658 irq_set_percpu_devid(virq);
659 break;
660 }
661
662 spin_lock_irqsave(&gic_lock, flags);
663 for (i = 0; i < gic_vpes; i++) {
664 u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
665
666 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
667
668 switch (intr) {
669 case GIC_LOCAL_INT_WD:
670 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
671 break;
672 case GIC_LOCAL_INT_COMPARE:
673 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
674 break;
675 case GIC_LOCAL_INT_TIMER:
676 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
677 val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
678 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
679 break;
680 case GIC_LOCAL_INT_PERFCTR:
681 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val);
682 break;
683 case GIC_LOCAL_INT_SWINT0:
684 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val);
685 break;
686 case GIC_LOCAL_INT_SWINT1:
687 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val);
688 break;
689 case GIC_LOCAL_INT_FDC:
690 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
691 break;
692 default:
693 pr_err("Invalid local IRQ %d\n", intr);
694 ret = -EINVAL;
695 break;
696 }
697 }
698 spin_unlock_irqrestore(&gic_lock, flags);
699
700 return ret;
701 }
702
703 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
704 irq_hw_number_t hw)
705 {
706 int intr = GIC_HWIRQ_TO_SHARED(hw);
707 unsigned long flags;
708
709 irq_set_chip_and_handler(virq, &gic_level_irq_controller,
710 handle_level_irq);
711
712 spin_lock_irqsave(&gic_lock, flags);
713 gic_map_to_pin(intr, gic_cpu_pin);
714 /* Map to VPE 0 by default */
715 gic_map_to_vpe(intr, 0);
716 set_bit(intr, pcpu_masks[0].pcpu_mask);
717 spin_unlock_irqrestore(&gic_lock, flags);
718
719 return 0;
720 }
721
722 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
723 irq_hw_number_t hw)
724 {
725 if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
726 return gic_local_irq_domain_map(d, virq, hw);
727 return gic_shared_irq_domain_map(d, virq, hw);
728 }
729
730 static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
731 const u32 *intspec, unsigned int intsize,
732 irq_hw_number_t *out_hwirq,
733 unsigned int *out_type)
734 {
735 if (intsize != 3)
736 return -EINVAL;
737
738 if (intspec[0] == GIC_SHARED)
739 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
740 else if (intspec[0] == GIC_LOCAL)
741 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
742 else
743 return -EINVAL;
744 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
745
746 return 0;
747 }
748
749 static const struct irq_domain_ops gic_irq_domain_ops = {
750 .map = gic_irq_domain_map,
751 .xlate = gic_irq_domain_xlate,
752 };
753
754 static void __init __gic_init(unsigned long gic_base_addr,
755 unsigned long gic_addrspace_size,
756 unsigned int cpu_vec, unsigned int irqbase,
757 struct device_node *node)
758 {
759 unsigned int gicconfig;
760
761 gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
762
763 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
764 gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
765 GIC_SH_CONFIG_NUMINTRS_SHF;
766 gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
767
768 gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
769 GIC_SH_CONFIG_NUMVPES_SHF;
770 gic_vpes = gic_vpes + 1;
771
772 if (cpu_has_veic) {
773 /* Always use vector 1 in EIC mode */
774 gic_cpu_pin = 0;
775 timer_cpu_pin = gic_cpu_pin;
776 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
777 __gic_irq_dispatch);
778 } else {
779 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
780 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
781 gic_irq_dispatch);
782 /*
783 * With the CMP implementation of SMP (deprecated), other CPUs
784 * are started by the bootloader and put into a timer based
785 * waiting poll loop. We must not re-route those CPU's local
786 * timer interrupts as the wait instruction will never finish,
787 * so just handle whatever CPU interrupt it is routed to by
788 * default.
789 *
790 * This workaround should be removed when CMP support is
791 * dropped.
792 */
793 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
794 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
795 timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL,
796 GIC_VPE_TIMER_MAP)) &
797 GIC_MAP_MSK;
798 irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
799 GIC_CPU_PIN_OFFSET +
800 timer_cpu_pin,
801 gic_irq_dispatch);
802 } else {
803 timer_cpu_pin = gic_cpu_pin;
804 }
805 }
806
807 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
808 gic_shared_intrs, irqbase,
809 &gic_irq_domain_ops, NULL);
810 if (!gic_irq_domain)
811 panic("Failed to add GIC IRQ domain");
812
813 gic_basic_init();
814
815 gic_ipi_init();
816 }
817
818 void __init gic_init(unsigned long gic_base_addr,
819 unsigned long gic_addrspace_size,
820 unsigned int cpu_vec, unsigned int irqbase)
821 {
822 __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
823 }
824
825 static int __init gic_of_init(struct device_node *node,
826 struct device_node *parent)
827 {
828 struct resource res;
829 unsigned int cpu_vec, i = 0, reserved = 0;
830 phys_addr_t gic_base;
831 size_t gic_len;
832
833 /* Find the first available CPU vector. */
834 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
835 i++, &cpu_vec))
836 reserved |= BIT(cpu_vec);
837 for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
838 if (!(reserved & BIT(cpu_vec)))
839 break;
840 }
841 if (cpu_vec == 8) {
842 pr_err("No CPU vectors available for GIC\n");
843 return -ENODEV;
844 }
845
846 if (of_address_to_resource(node, 0, &res)) {
847 /*
848 * Probe the CM for the GIC base address if not specified
849 * in the device-tree.
850 */
851 if (mips_cm_present()) {
852 gic_base = read_gcr_gic_base() &
853 ~CM_GCR_GIC_BASE_GICEN_MSK;
854 gic_len = 0x20000;
855 } else {
856 pr_err("Failed to get GIC memory range\n");
857 return -ENODEV;
858 }
859 } else {
860 gic_base = res.start;
861 gic_len = resource_size(&res);
862 }
863
864 if (mips_cm_present())
865 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
866 gic_present = true;
867
868 __gic_init(gic_base, gic_len, cpu_vec, 0, node);
869
870 return 0;
871 }
872 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
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