drivers/irqchip/irq-nvic.c

   1 /*
   2  * drivers/irq/irq-nvic.c
   3  *
   4  * Copyright (C) 2008 ARM Limited, All Rights Reserved.
   5  * Copyright (C) 2013 Pengutronix
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Support for the Nested Vectored Interrupt Controller found on the
  12  * ARMv7-M CPUs (Cortex-M3/M4)
  13  */
  14 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
  15
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/irq.h>
  24 #include <linux/irqdomain.h>
  25
  26 #include <asm/v7m.h>
  27 #include <asm/exception.h>
  28
  29 #include "irqchip.h"
  30
  31 #define NVIC_ISER               0x000
  32 #define NVIC_ICER               0x080
  33 #define NVIC_IPR                0x300
  34
  35 #define NVIC_MAX_BANKS          16
  36 /*
  37  * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
  38  * 16 irqs.
  39  */
  40 #define NVIC_MAX_IRQ            ((NVIC_MAX_BANKS - 1) * 32 + 16)
  41
  42 static struct irq_domain *nvic_irq_domain;
  43
  44 asmlinkage void __exception_irq_entry
  45 nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
  46 {
  47         unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq);
  48
  49         handle_IRQ(irq, regs);
  50 }
  51
  52 static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  53                                 unsigned int nr_irqs, void *arg)
  54 {
  55         int i, ret;
  56         irq_hw_number_t hwirq;
  57         unsigned int type = IRQ_TYPE_NONE;
  58         struct of_phandle_args *irq_data = arg;
  59
  60         ret = irq_domain_xlate_onecell(domain, irq_data->np, irq_data->args,
  61                                    irq_data->args_count, &hwirq, &type);
  62         if (ret)
  63                 return ret;
  64
  65         for (i = 0; i < nr_irqs; i++)
  66                 irq_map_generic_chip(domain, virq + i, hwirq + i);
  67
  68         return 0;
  69 }
  70
  71 static const struct irq_domain_ops nvic_irq_domain_ops = {
  72         .xlate = irq_domain_xlate_onecell,
  73         .alloc = nvic_irq_domain_alloc,
  74         .free = irq_domain_free_irqs_top,
  75 };
  76
  77 static int __init nvic_of_init(struct device_node *node,
  78                                struct device_node *parent)
  79 {
  80         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  81         unsigned int irqs, i, ret, numbanks;
  82         void __iomem *nvic_base;
  83
  84         numbanks = (readl_relaxed(V7M_SCS_ICTR) &
  85                     V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
  86
  87         nvic_base = of_iomap(node, 0);
  88         if (!nvic_base) {
  89                 pr_warn("unable to map nvic registers\n");
  90                 return -ENOMEM;
  91         }
  92
  93         irqs = numbanks * 32;
  94         if (irqs > NVIC_MAX_IRQ)
  95                 irqs = NVIC_MAX_IRQ;
  96
  97         nvic_irq_domain =
  98                 irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
  99
 100         if (!nvic_irq_domain) {
 101                 pr_warn("Failed to allocate irq domain\n");
 102                 return -ENOMEM;
 103         }
 104
 105         ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
 106                                              "nvic_irq", handle_fasteoi_irq,
 107                                              clr, 0, IRQ_GC_INIT_MASK_CACHE);
 108         if (ret) {
 109                 pr_warn("Failed to allocate irq chips\n");
 110                 irq_domain_remove(nvic_irq_domain);
 111                 return ret;
 112         }
 113
 114         for (i = 0; i < numbanks; ++i) {
 115                 struct irq_chip_generic *gc;
 116
 117                 gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
 118                 gc->reg_base = nvic_base + 4 * i;
 119                 gc->chip_types[0].regs.enable = NVIC_ISER;
 120                 gc->chip_types[0].regs.disable = NVIC_ICER;
 121                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
 122                 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
 123                 /* This is a no-op as end of interrupt is signaled by the
 124                  * exception return sequence.
 125                  */
 126                 gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
 127
 128                 /* disable interrupts */
 129                 writel_relaxed(~0, gc->reg_base + NVIC_ICER);
 130         }
 131
 132         /* Set priority on all interrupts */
 133         for (i = 0; i < irqs; i += 4)
 134                 writel_relaxed(0, nvic_base + NVIC_IPR + i);
 135
 136         return 0;
 137 }
 138 IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);