drivers/irqchip/irq-riscv-intc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2012 Regents of the University of California
   4  * Copyright (C) 2017-2018 SiFive
   5  * Copyright (C) 2020 Western Digital Corporation or its affiliates.
   6  */
   7
   8 #define pr_fmt(fmt) "riscv-intc: " fmt
   9 #include <linux/atomic.h>
  10 #include <linux/bits.h>
  11 #include <linux/cpu.h>
  12 #include <linux/irq.h>
  13 #include <linux/irqchip.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/smp.h>
  19
  20 static struct irq_domain *intc_domain;
  21
  22 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
  23 {
  24         unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
  25
  26         if (unlikely(cause >= BITS_PER_LONG))
  27                 panic("unexpected interrupt cause");
  28
  29         switch (cause) {
  30 #ifdef CONFIG_SMP
  31         case RV_IRQ_SOFT:
  32                 /*
  33                  * We only use software interrupts to pass IPIs, so if a
  34                  * non-SMP system gets one, then we don't know what to do.
  35                  */
  36                 handle_IPI(regs);
  37                 break;
  38 #endif
  39         default:
  40                 handle_domain_irq(intc_domain, cause, regs);
  41                 break;
  42         }
  43 }
  44
  45 /*
  46  * On RISC-V systems local interrupts are masked or unmasked by writing
  47  * the SIE (Supervisor Interrupt Enable) CSR.  As CSRs can only be written
  48  * on the local hart, these functions can only be called on the hart that
  49  * corresponds to the IRQ chip.
  50  */
  51
  52 static void riscv_intc_irq_mask(struct irq_data *d)
  53 {
  54         csr_clear(CSR_IE, BIT(d->hwirq));
  55 }
  56
  57 static void riscv_intc_irq_unmask(struct irq_data *d)
  58 {
  59         csr_set(CSR_IE, BIT(d->hwirq));
  60 }
  61
  62 static int riscv_intc_cpu_starting(unsigned int cpu)
  63 {
  64         csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
  65         return 0;
  66 }
  67
  68 static int riscv_intc_cpu_dying(unsigned int cpu)
  69 {
  70         csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
  71         return 0;
  72 }
  73
  74 static struct irq_chip riscv_intc_chip = {
  75         .name = "RISC-V INTC",
  76         .irq_mask = riscv_intc_irq_mask,
  77         .irq_unmask = riscv_intc_irq_unmask,
  78 };
  79
  80 static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
  81                                  irq_hw_number_t hwirq)
  82 {
  83         irq_set_percpu_devid(irq);
  84         irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
  85                             handle_percpu_devid_irq, NULL, NULL);
  86
  87         return 0;
  88 }
  89
  90 static const struct irq_domain_ops riscv_intc_domain_ops = {
  91         .map    = riscv_intc_domain_map,
  92         .xlate  = irq_domain_xlate_onecell,
  93 };
  94
  95 static int __init riscv_intc_init(struct device_node *node,
  96                                   struct device_node *parent)
  97 {
  98         int rc, hartid;
  99
 100         hartid = riscv_of_parent_hartid(node);
 101         if (hartid < 0) {
 102                 pr_warn("unable to find hart id for %pOF\n", node);
 103                 return 0;
 104         }
 105
 106         /*
 107          * The DT will have one INTC DT node under each CPU (or HART)
 108          * DT node so riscv_intc_init() function will be called once
 109          * for each INTC DT node. We only need to do INTC initialization
 110          * for the INTC DT node belonging to boot CPU (or boot HART).
 111          */
 112         if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
 113                 return 0;
 114
 115         intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
 116                                             &riscv_intc_domain_ops, NULL);
 117         if (!intc_domain) {
 118                 pr_err("unable to add IRQ domain\n");
 119                 return -ENXIO;
 120         }
 121
 122         rc = set_handle_irq(&riscv_intc_irq);
 123         if (rc) {
 124                 pr_err("failed to set irq handler\n");
 125                 return rc;
 126         }
 127
 128         cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
 129                           "irqchip/riscv/intc:starting",
 130                           riscv_intc_cpu_starting,
 131                           riscv_intc_cpu_dying);
 132
 133         pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
 134
 135         return 0;
 136 }
 137
 138 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);