drivers/irqchip/irq-sun4i.c

   1 /*
   2  * Allwinner A1X SoCs IRQ chip driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqchip.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23
  24 #include <asm/exception.h>
  25 #include <asm/mach/irq.h>
  26
  27 #define SUN4I_IRQ_VECTOR_REG            0x00
  28 #define SUN4I_IRQ_PROTECTION_REG        0x08
  29 #define SUN4I_IRQ_NMI_CTRL_REG          0x0c
  30 #define SUN4I_IRQ_PENDING_REG(x)        (0x10 + 0x4 * x)
  31 #define SUN4I_IRQ_FIQ_PENDING_REG(x)    (0x20 + 0x4 * x)
  32 #define SUN4I_IRQ_ENABLE_REG(x)         (0x40 + 0x4 * x)
  33 #define SUN4I_IRQ_MASK_REG(x)           (0x50 + 0x4 * x)
  34
  35 static void __iomem *sun4i_irq_base;
  36 static struct irq_domain *sun4i_irq_domain;
  37
  38 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
  39
  40 static void sun4i_irq_ack(struct irq_data *irqd)
  41 {
  42         unsigned int irq = irqd_to_hwirq(irqd);
  43
  44         if (irq != 0)
  45                 return; /* Only IRQ 0 / the ENMI needs to be acked */
  46
  47         writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
  48 }
  49
  50 static void sun4i_irq_mask(struct irq_data *irqd)
  51 {
  52         unsigned int irq = irqd_to_hwirq(irqd);
  53         unsigned int irq_off = irq % 32;
  54         int reg = irq / 32;
  55         u32 val;
  56
  57         val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  58         writel(val & ~(1 << irq_off),
  59                sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  60 }
  61
  62 static void sun4i_irq_unmask(struct irq_data *irqd)
  63 {
  64         unsigned int irq = irqd_to_hwirq(irqd);
  65         unsigned int irq_off = irq % 32;
  66         int reg = irq / 32;
  67         u32 val;
  68
  69         val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  70         writel(val | (1 << irq_off),
  71                sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  72 }
  73
  74 static struct irq_chip sun4i_irq_chip = {
  75         .name           = "sun4i_irq",
  76         .irq_eoi        = sun4i_irq_ack,
  77         .irq_mask       = sun4i_irq_mask,
  78         .irq_unmask     = sun4i_irq_unmask,
  79         .flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
  80 };
  81
  82 static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
  83                          irq_hw_number_t hw)
  84 {
  85         irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
  86         irq_set_probe(virq);
  87
  88         return 0;
  89 }
  90
  91 static const struct irq_domain_ops sun4i_irq_ops = {
  92         .map = sun4i_irq_map,
  93         .xlate = irq_domain_xlate_onecell,
  94 };
  95
  96 static int __init sun4i_of_init(struct device_node *node,
  97                                 struct device_node *parent)
  98 {
  99         sun4i_irq_base = of_iomap(node, 0);
 100         if (!sun4i_irq_base)
 101                 panic("%s: unable to map IC registers\n",
 102                         node->full_name);
 103
 104         /* Disable all interrupts */
 105         writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
 106         writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
 107         writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
 108
 109         /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
 110         writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
 111         writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
 112         writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
 113
 114         /* Clear all the pending interrupts */
 115         writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
 116         writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
 117         writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
 118
 119         /* Enable protection mode */
 120         writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
 121
 122         /* Configure the external interrupt source type */
 123         writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
 124
 125         sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
 126                                                  &sun4i_irq_ops, NULL);
 127         if (!sun4i_irq_domain)
 128                 panic("%s: unable to create IRQ domain\n", node->full_name);
 129
 130         set_handle_irq(sun4i_handle_irq);
 131
 132         return 0;
 133 }
 134 IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
 135
 136 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
 137 {
 138         u32 hwirq;
 139
 140         /*
 141          * hwirq == 0 can mean one of 3 things:
 142          * 1) no more irqs pending
 143          * 2) irq 0 pending
 144          * 3) spurious irq
 145          * So if we immediately get a reading of 0, check the irq-pending reg
 146          * to differentiate between 2 and 3. We only do this once to avoid
 147          * the extra check in the common case of 1 hapening after having
 148          * read the vector-reg once.
 149          */
 150         hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
 151         if (hwirq == 0 &&
 152                   !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
 153                 return;
 154
 155         do {
 156                 handle_domain_irq(sun4i_irq_domain, hwirq, regs);
 157                 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
 158         } while (hwirq != 0);
 159 }