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Merge tag 'mmc-v4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
[mirror_ubuntu-bionic-kernel.git] / drivers / isdn / hardware / mISDN / hfcpci.c
1 /*
2 *
3 * hfcpci.c low level driver for CCD's hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
8 *
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Module options:
27 *
28 * debug:
29 * NOTE: only one poll value must be given for all cards
30 * See hfc_pci.h for debug flags.
31 *
32 * poll:
33 * NOTE: only one poll value must be given for all cards
34 * Give the number of samples for each fifo process.
35 * By default 128 is used. Decrease to reduce delay, increase to
36 * reduce cpu load. If unsure, don't mess with it!
37 * A value of 128 will use controller's interrupt. Other values will
38 * use kernel timer, because the controller will not allow lower values
39 * than 128.
40 * Also note that the value depends on the kernel timer frequency.
41 * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
42 * If the kernel uses 100 Hz, steps of 80 samples are possible.
43 * If the kernel uses 300 Hz, steps of about 26 samples are possible.
44 *
45 */
46
47 #include <linux/interrupt.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/delay.h>
51 #include <linux/mISDNhw.h>
52 #include <linux/slab.h>
53
54 #include "hfc_pci.h"
55
56 static const char *hfcpci_revision = "2.0";
57
58 static int HFC_cnt;
59 static uint debug;
60 static uint poll, tics;
61 static struct timer_list hfc_tl;
62 static unsigned long hfc_jiffies;
63
64 MODULE_AUTHOR("Karsten Keil");
65 MODULE_LICENSE("GPL");
66 module_param(debug, uint, S_IRUGO | S_IWUSR);
67 module_param(poll, uint, S_IRUGO | S_IWUSR);
68
69 enum {
70 HFC_CCD_2BD0,
71 HFC_CCD_B000,
72 HFC_CCD_B006,
73 HFC_CCD_B007,
74 HFC_CCD_B008,
75 HFC_CCD_B009,
76 HFC_CCD_B00A,
77 HFC_CCD_B00B,
78 HFC_CCD_B00C,
79 HFC_CCD_B100,
80 HFC_CCD_B700,
81 HFC_CCD_B701,
82 HFC_ASUS_0675,
83 HFC_BERKOM_A1T,
84 HFC_BERKOM_TCONCEPT,
85 HFC_ANIGMA_MC145575,
86 HFC_ZOLTRIX_2BD0,
87 HFC_DIGI_DF_M_IOM2_E,
88 HFC_DIGI_DF_M_E,
89 HFC_DIGI_DF_M_IOM2_A,
90 HFC_DIGI_DF_M_A,
91 HFC_ABOCOM_2BD1,
92 HFC_SITECOM_DC105V2,
93 };
94
95 struct hfcPCI_hw {
96 unsigned char cirm;
97 unsigned char ctmt;
98 unsigned char clkdel;
99 unsigned char states;
100 unsigned char conn;
101 unsigned char mst_m;
102 unsigned char int_m1;
103 unsigned char int_m2;
104 unsigned char sctrl;
105 unsigned char sctrl_r;
106 unsigned char sctrl_e;
107 unsigned char trm;
108 unsigned char fifo_en;
109 unsigned char bswapped;
110 unsigned char protocol;
111 int nt_timer;
112 unsigned char __iomem *pci_io; /* start of PCI IO memory */
113 dma_addr_t dmahandle;
114 void *fifos; /* FIFO memory */
115 int last_bfifo_cnt[2];
116 /* marker saving last b-fifo frame count */
117 struct timer_list timer;
118 };
119
120 #define HFC_CFG_MASTER 1
121 #define HFC_CFG_SLAVE 2
122 #define HFC_CFG_PCM 3
123 #define HFC_CFG_2HFC 4
124 #define HFC_CFG_SLAVEHFC 5
125 #define HFC_CFG_NEG_F0 6
126 #define HFC_CFG_SW_DD_DU 7
127
128 #define FLG_HFC_TIMER_T1 16
129 #define FLG_HFC_TIMER_T3 17
130
131 #define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
132 #define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
133 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
134 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
135
136
137 struct hfc_pci {
138 u_char subtype;
139 u_char chanlimit;
140 u_char initdone;
141 u_long cfg;
142 u_int irq;
143 u_int irqcnt;
144 struct pci_dev *pdev;
145 struct hfcPCI_hw hw;
146 spinlock_t lock; /* card lock */
147 struct dchannel dch;
148 struct bchannel bch[2];
149 };
150
151 /* Interface functions */
152 static void
153 enable_hwirq(struct hfc_pci *hc)
154 {
155 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
156 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
157 }
158
159 static void
160 disable_hwirq(struct hfc_pci *hc)
161 {
162 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
163 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
164 }
165
166 /*
167 * free hardware resources used by driver
168 */
169 static void
170 release_io_hfcpci(struct hfc_pci *hc)
171 {
172 /* disable memory mapped ports + busmaster */
173 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
174 del_timer(&hc->hw.timer);
175 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
176 iounmap(hc->hw.pci_io);
177 }
178
179 /*
180 * set mode (NT or TE)
181 */
182 static void
183 hfcpci_setmode(struct hfc_pci *hc)
184 {
185 if (hc->hw.protocol == ISDN_P_NT_S0) {
186 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
187 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
188 hc->hw.states = 1; /* G1 */
189 } else {
190 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
191 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
192 hc->hw.states = 2; /* F2 */
193 }
194 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
195 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
196 udelay(10);
197 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
198 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
199 }
200
201 /*
202 * function called to reset the HFC PCI chip. A complete software reset of chip
203 * and fifos is done.
204 */
205 static void
206 reset_hfcpci(struct hfc_pci *hc)
207 {
208 u_char val;
209 int cnt = 0;
210
211 printk(KERN_DEBUG "reset_hfcpci: entered\n");
212 val = Read_hfc(hc, HFCPCI_CHIP_ID);
213 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
214 /* enable memory mapped ports, disable busmaster */
215 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
216 disable_hwirq(hc);
217 /* enable memory ports + busmaster */
218 pci_write_config_word(hc->pdev, PCI_COMMAND,
219 PCI_ENA_MEMIO + PCI_ENA_MASTER);
220 val = Read_hfc(hc, HFCPCI_STATUS);
221 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
222 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
223 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
224 set_current_state(TASK_UNINTERRUPTIBLE);
225 mdelay(10); /* Timeout 10ms */
226 hc->hw.cirm = 0; /* Reset Off */
227 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
228 val = Read_hfc(hc, HFCPCI_STATUS);
229 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
230 while (cnt < 50000) { /* max 50000 us */
231 udelay(5);
232 cnt += 5;
233 val = Read_hfc(hc, HFCPCI_STATUS);
234 if (!(val & 2))
235 break;
236 }
237 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
238
239 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
240
241 hc->hw.bswapped = 0; /* no exchange */
242 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
243 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
244 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
245 hc->hw.sctrl_r = 0;
246 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
247 hc->hw.mst_m = 0;
248 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
249 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
250 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
251 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
252 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
253 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
254 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
255 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
256
257 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
258 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
259 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
260
261 /* Clear already pending ints */
262 val = Read_hfc(hc, HFCPCI_INT_S1);
263
264 /* set NT/TE mode */
265 hfcpci_setmode(hc);
266
267 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
268 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
269
270 /*
271 * Init GCI/IOM2 in master mode
272 * Slots 0 and 1 are set for B-chan 1 and 2
273 * D- and monitor/CI channel are not enabled
274 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
275 * STIO2 is used as data input, B1+B2 from IOM->ST
276 * ST B-channel send disabled -> continuous 1s
277 * The IOM slots are always enabled
278 */
279 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
280 /* set data flow directions: connect B1,B2: HFC to/from PCM */
281 hc->hw.conn = 0x09;
282 } else {
283 hc->hw.conn = 0x36; /* set data flow directions */
284 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
285 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
286 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
287 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
288 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
289 } else {
290 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
291 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
292 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
293 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
294 }
295 }
296 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
297 val = Read_hfc(hc, HFCPCI_INT_S2);
298 }
299
300 /*
301 * Timer function called when kernel timer expires
302 */
303 static void
304 hfcpci_Timer(struct timer_list *t)
305 {
306 struct hfc_pci *hc = from_timer(hc, t, hw.timer);
307 hc->hw.timer.expires = jiffies + 75;
308 /* WD RESET */
309 /*
310 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
311 * add_timer(&hc->hw.timer);
312 */
313 }
314
315
316 /*
317 * select a b-channel entry matching and active
318 */
319 static struct bchannel *
320 Sel_BCS(struct hfc_pci *hc, int channel)
321 {
322 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
323 (hc->bch[0].nr & channel))
324 return &hc->bch[0];
325 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
326 (hc->bch[1].nr & channel))
327 return &hc->bch[1];
328 else
329 return NULL;
330 }
331
332 /*
333 * clear the desired B-channel rx fifo
334 */
335 static void
336 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
337 {
338 u_char fifo_state;
339 struct bzfifo *bzr;
340
341 if (fifo) {
342 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
343 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
344 } else {
345 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
346 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
347 }
348 if (fifo_state)
349 hc->hw.fifo_en ^= fifo_state;
350 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
351 hc->hw.last_bfifo_cnt[fifo] = 0;
352 bzr->f1 = MAX_B_FRAMES;
353 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
354 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
355 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
356 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
357 if (fifo_state)
358 hc->hw.fifo_en |= fifo_state;
359 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
360 }
361
362 /*
363 * clear the desired B-channel tx fifo
364 */
365 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
366 {
367 u_char fifo_state;
368 struct bzfifo *bzt;
369
370 if (fifo) {
371 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
372 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
373 } else {
374 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
375 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
376 }
377 if (fifo_state)
378 hc->hw.fifo_en ^= fifo_state;
379 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
380 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
381 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
382 "z1(%x) z2(%x) state(%x)\n",
383 fifo, bzt->f1, bzt->f2,
384 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
385 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
386 fifo_state);
387 bzt->f2 = MAX_B_FRAMES;
388 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
389 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
390 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
391 if (fifo_state)
392 hc->hw.fifo_en |= fifo_state;
393 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
394 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
395 printk(KERN_DEBUG
396 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
397 fifo, bzt->f1, bzt->f2,
398 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
399 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
400 }
401
402 /*
403 * read a complete B-frame out of the buffer
404 */
405 static void
406 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
407 u_char *bdata, int count)
408 {
409 u_char *ptr, *ptr1, new_f2;
410 int maxlen, new_z2;
411 struct zt *zp;
412
413 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
414 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
415 zp = &bz->za[bz->f2]; /* point to Z-Regs */
416 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
417 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
418 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
419 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
420 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
421 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
422 if (bch->debug & DEBUG_HW)
423 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
424 "invalid length %d or crc\n", count);
425 #ifdef ERROR_STATISTIC
426 bch->err_inv++;
427 #endif
428 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
429 bz->f2 = new_f2; /* next buffer */
430 } else {
431 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
432 if (!bch->rx_skb) {
433 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
434 return;
435 }
436 count -= 3;
437 ptr = skb_put(bch->rx_skb, count);
438
439 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
440 maxlen = count; /* complete transfer */
441 else
442 maxlen = B_FIFO_SIZE + B_SUB_VAL -
443 le16_to_cpu(zp->z2); /* maximum */
444
445 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
446 /* start of data */
447 memcpy(ptr, ptr1, maxlen); /* copy data */
448 count -= maxlen;
449
450 if (count) { /* rest remaining */
451 ptr += maxlen;
452 ptr1 = bdata; /* start of buffer */
453 memcpy(ptr, ptr1, count); /* rest */
454 }
455 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
456 bz->f2 = new_f2; /* next buffer */
457 recv_Bchannel(bch, MISDN_ID_ANY, false);
458 }
459 }
460
461 /*
462 * D-channel receive procedure
463 */
464 static int
465 receive_dmsg(struct hfc_pci *hc)
466 {
467 struct dchannel *dch = &hc->dch;
468 int maxlen;
469 int rcnt, total;
470 int count = 5;
471 u_char *ptr, *ptr1;
472 struct dfifo *df;
473 struct zt *zp;
474
475 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
476 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
477 zp = &df->za[df->f2 & D_FREG_MASK];
478 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
479 if (rcnt < 0)
480 rcnt += D_FIFO_SIZE;
481 rcnt++;
482 if (dch->debug & DEBUG_HW_DCHANNEL)
483 printk(KERN_DEBUG
484 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
485 df->f1, df->f2,
486 le16_to_cpu(zp->z1),
487 le16_to_cpu(zp->z2),
488 rcnt);
489
490 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
491 (df->data[le16_to_cpu(zp->z1)])) {
492 if (dch->debug & DEBUG_HW)
493 printk(KERN_DEBUG
494 "empty_fifo hfcpci packet inv. len "
495 "%d or crc %d\n",
496 rcnt,
497 df->data[le16_to_cpu(zp->z1)]);
498 #ifdef ERROR_STATISTIC
499 cs->err_rx++;
500 #endif
501 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
502 (MAX_D_FRAMES + 1); /* next buffer */
503 df->za[df->f2 & D_FREG_MASK].z2 =
504 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
505 (D_FIFO_SIZE - 1));
506 } else {
507 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
508 if (!dch->rx_skb) {
509 printk(KERN_WARNING
510 "HFC-PCI: D receive out of memory\n");
511 break;
512 }
513 total = rcnt;
514 rcnt -= 3;
515 ptr = skb_put(dch->rx_skb, rcnt);
516
517 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
518 maxlen = rcnt; /* complete transfer */
519 else
520 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
521 /* maximum */
522
523 ptr1 = df->data + le16_to_cpu(zp->z2);
524 /* start of data */
525 memcpy(ptr, ptr1, maxlen); /* copy data */
526 rcnt -= maxlen;
527
528 if (rcnt) { /* rest remaining */
529 ptr += maxlen;
530 ptr1 = df->data; /* start of buffer */
531 memcpy(ptr, ptr1, rcnt); /* rest */
532 }
533 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
534 (MAX_D_FRAMES + 1); /* next buffer */
535 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
536 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
537 recv_Dchannel(dch);
538 }
539 }
540 return 1;
541 }
542
543 /*
544 * check for transparent receive data and read max one 'poll' size if avail
545 */
546 static void
547 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
548 struct bzfifo *txbz, u_char *bdata)
549 {
550 __le16 *z1r, *z2r, *z1t, *z2t;
551 int new_z2, fcnt_rx, fcnt_tx, maxlen;
552 u_char *ptr, *ptr1;
553
554 z1r = &rxbz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
555 z2r = z1r + 1;
556 z1t = &txbz->za[MAX_B_FRAMES].z1;
557 z2t = z1t + 1;
558
559 fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
560 if (!fcnt_rx)
561 return; /* no data avail */
562
563 if (fcnt_rx <= 0)
564 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
565 new_z2 = le16_to_cpu(*z2r) + fcnt_rx; /* new position in fifo */
566 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
567 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
568
569 fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
570 if (fcnt_tx <= 0)
571 fcnt_tx += B_FIFO_SIZE;
572 /* fcnt_tx contains available bytes in tx-fifo */
573 fcnt_tx = B_FIFO_SIZE - fcnt_tx;
574 /* remaining bytes to send (bytes in tx-fifo) */
575
576 if (test_bit(FLG_RX_OFF, &bch->Flags)) {
577 bch->dropcnt += fcnt_rx;
578 *z2r = cpu_to_le16(new_z2);
579 return;
580 }
581 maxlen = bchannel_get_rxbuf(bch, fcnt_rx);
582 if (maxlen < 0) {
583 pr_warning("B%d: No bufferspace for %d bytes\n",
584 bch->nr, fcnt_rx);
585 } else {
586 ptr = skb_put(bch->rx_skb, fcnt_rx);
587 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
588 maxlen = fcnt_rx; /* complete transfer */
589 else
590 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
591 /* maximum */
592
593 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
594 /* start of data */
595 memcpy(ptr, ptr1, maxlen); /* copy data */
596 fcnt_rx -= maxlen;
597
598 if (fcnt_rx) { /* rest remaining */
599 ptr += maxlen;
600 ptr1 = bdata; /* start of buffer */
601 memcpy(ptr, ptr1, fcnt_rx); /* rest */
602 }
603 recv_Bchannel(bch, fcnt_tx, false); /* bch, id, !force */
604 }
605 *z2r = cpu_to_le16(new_z2); /* new position */
606 }
607
608 /*
609 * B-channel main receive routine
610 */
611 static void
612 main_rec_hfcpci(struct bchannel *bch)
613 {
614 struct hfc_pci *hc = bch->hw;
615 int rcnt, real_fifo;
616 int receive = 0, count = 5;
617 struct bzfifo *txbz, *rxbz;
618 u_char *bdata;
619 struct zt *zp;
620
621 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
622 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
623 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
624 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
625 real_fifo = 1;
626 } else {
627 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
628 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
629 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
630 real_fifo = 0;
631 }
632 Begin:
633 count--;
634 if (rxbz->f1 != rxbz->f2) {
635 if (bch->debug & DEBUG_HW_BCHANNEL)
636 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
637 bch->nr, rxbz->f1, rxbz->f2);
638 zp = &rxbz->za[rxbz->f2];
639
640 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
641 if (rcnt < 0)
642 rcnt += B_FIFO_SIZE;
643 rcnt++;
644 if (bch->debug & DEBUG_HW_BCHANNEL)
645 printk(KERN_DEBUG
646 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
647 bch->nr, le16_to_cpu(zp->z1),
648 le16_to_cpu(zp->z2), rcnt);
649 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
650 rcnt = rxbz->f1 - rxbz->f2;
651 if (rcnt < 0)
652 rcnt += MAX_B_FRAMES + 1;
653 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
654 rcnt = 0;
655 hfcpci_clear_fifo_rx(hc, real_fifo);
656 }
657 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
658 if (rcnt > 1)
659 receive = 1;
660 else
661 receive = 0;
662 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
663 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
664 return;
665 } else
666 receive = 0;
667 if (count && receive)
668 goto Begin;
669
670 }
671
672 /*
673 * D-channel send routine
674 */
675 static void
676 hfcpci_fill_dfifo(struct hfc_pci *hc)
677 {
678 struct dchannel *dch = &hc->dch;
679 int fcnt;
680 int count, new_z1, maxlen;
681 struct dfifo *df;
682 u_char *src, *dst, new_f1;
683
684 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
685 printk(KERN_DEBUG "%s\n", __func__);
686
687 if (!dch->tx_skb)
688 return;
689 count = dch->tx_skb->len - dch->tx_idx;
690 if (count <= 0)
691 return;
692 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
693
694 if (dch->debug & DEBUG_HW_DFIFO)
695 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
696 df->f1, df->f2,
697 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
698 fcnt = df->f1 - df->f2; /* frame count actually buffered */
699 if (fcnt < 0)
700 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
701 if (fcnt > (MAX_D_FRAMES - 1)) {
702 if (dch->debug & DEBUG_HW_DCHANNEL)
703 printk(KERN_DEBUG
704 "hfcpci_fill_Dfifo more as 14 frames\n");
705 #ifdef ERROR_STATISTIC
706 cs->err_tx++;
707 #endif
708 return;
709 }
710 /* now determine free bytes in FIFO buffer */
711 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
712 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
713 if (maxlen <= 0)
714 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
715
716 if (dch->debug & DEBUG_HW_DCHANNEL)
717 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
718 count, maxlen);
719 if (count > maxlen) {
720 if (dch->debug & DEBUG_HW_DCHANNEL)
721 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
722 return;
723 }
724 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
725 (D_FIFO_SIZE - 1);
726 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
727 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
728 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
729 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
730 /* end fifo */
731 if (maxlen > count)
732 maxlen = count; /* limit size */
733 memcpy(dst, src, maxlen); /* first copy */
734
735 count -= maxlen; /* remaining bytes */
736 if (count) {
737 dst = df->data; /* start of buffer */
738 src += maxlen; /* new position */
739 memcpy(dst, src, count);
740 }
741 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
742 /* for next buffer */
743 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
744 /* new pos actual buffer */
745 df->f1 = new_f1; /* next frame */
746 dch->tx_idx = dch->tx_skb->len;
747 }
748
749 /*
750 * B-channel send routine
751 */
752 static void
753 hfcpci_fill_fifo(struct bchannel *bch)
754 {
755 struct hfc_pci *hc = bch->hw;
756 int maxlen, fcnt;
757 int count, new_z1;
758 struct bzfifo *bz;
759 u_char *bdata;
760 u_char new_f1, *src, *dst;
761 __le16 *z1t, *z2t;
762
763 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
764 printk(KERN_DEBUG "%s\n", __func__);
765 if ((!bch->tx_skb) || bch->tx_skb->len == 0) {
766 if (!test_bit(FLG_FILLEMPTY, &bch->Flags) &&
767 !test_bit(FLG_TRANSPARENT, &bch->Flags))
768 return;
769 count = HFCPCI_FILLEMPTY;
770 } else {
771 count = bch->tx_skb->len - bch->tx_idx;
772 }
773 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
774 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
775 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
776 } else {
777 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
778 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
779 }
780
781 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
782 z1t = &bz->za[MAX_B_FRAMES].z1;
783 z2t = z1t + 1;
784 if (bch->debug & DEBUG_HW_BCHANNEL)
785 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
786 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
787 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
788 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
789 if (fcnt <= 0)
790 fcnt += B_FIFO_SIZE;
791 if (test_bit(FLG_FILLEMPTY, &bch->Flags)) {
792 /* fcnt contains available bytes in fifo */
793 if (count > fcnt)
794 count = fcnt;
795 new_z1 = le16_to_cpu(*z1t) + count;
796 /* new buffer Position */
797 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
798 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
799 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
800 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
801 /* end of fifo */
802 if (bch->debug & DEBUG_HW_BFIFO)
803 printk(KERN_DEBUG "hfcpci_FFt fillempty "
804 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
805 fcnt, maxlen, new_z1, dst);
806 if (maxlen > count)
807 maxlen = count; /* limit size */
808 memset(dst, bch->fill[0], maxlen); /* first copy */
809 count -= maxlen; /* remaining bytes */
810 if (count) {
811 dst = bdata; /* start of buffer */
812 memset(dst, bch->fill[0], count);
813 }
814 *z1t = cpu_to_le16(new_z1); /* now send data */
815 return;
816 }
817 /* fcnt contains available bytes in fifo */
818 fcnt = B_FIFO_SIZE - fcnt;
819 /* remaining bytes to send (bytes in fifo) */
820
821 next_t_frame:
822 count = bch->tx_skb->len - bch->tx_idx;
823 /* maximum fill shall be poll*2 */
824 if (count > (poll << 1) - fcnt)
825 count = (poll << 1) - fcnt;
826 if (count <= 0)
827 return;
828 /* data is suitable for fifo */
829 new_z1 = le16_to_cpu(*z1t) + count;
830 /* new buffer Position */
831 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
832 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
833 src = bch->tx_skb->data + bch->tx_idx;
834 /* source pointer */
835 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
836 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
837 /* end of fifo */
838 if (bch->debug & DEBUG_HW_BFIFO)
839 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
840 "maxl(%d) nz1(%x) dst(%p)\n",
841 fcnt, maxlen, new_z1, dst);
842 fcnt += count;
843 bch->tx_idx += count;
844 if (maxlen > count)
845 maxlen = count; /* limit size */
846 memcpy(dst, src, maxlen); /* first copy */
847 count -= maxlen; /* remaining bytes */
848 if (count) {
849 dst = bdata; /* start of buffer */
850 src += maxlen; /* new position */
851 memcpy(dst, src, count);
852 }
853 *z1t = cpu_to_le16(new_z1); /* now send data */
854 if (bch->tx_idx < bch->tx_skb->len)
855 return;
856 dev_kfree_skb(bch->tx_skb);
857 if (get_next_bframe(bch))
858 goto next_t_frame;
859 return;
860 }
861 if (bch->debug & DEBUG_HW_BCHANNEL)
862 printk(KERN_DEBUG
863 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
864 __func__, bch->nr, bz->f1, bz->f2,
865 bz->za[bz->f1].z1);
866 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
867 if (fcnt < 0)
868 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
869 if (fcnt > (MAX_B_FRAMES - 1)) {
870 if (bch->debug & DEBUG_HW_BCHANNEL)
871 printk(KERN_DEBUG
872 "hfcpci_fill_Bfifo more as 14 frames\n");
873 return;
874 }
875 /* now determine free bytes in FIFO buffer */
876 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
877 le16_to_cpu(bz->za[bz->f1].z1) - 1;
878 if (maxlen <= 0)
879 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
880
881 if (bch->debug & DEBUG_HW_BCHANNEL)
882 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
883 bch->nr, count, maxlen);
884
885 if (maxlen < count) {
886 if (bch->debug & DEBUG_HW_BCHANNEL)
887 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
888 return;
889 }
890 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
891 /* new buffer Position */
892 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
893 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
894
895 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
896 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
897 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
898 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
899 /* end fifo */
900 if (maxlen > count)
901 maxlen = count; /* limit size */
902 memcpy(dst, src, maxlen); /* first copy */
903
904 count -= maxlen; /* remaining bytes */
905 if (count) {
906 dst = bdata; /* start of buffer */
907 src += maxlen; /* new position */
908 memcpy(dst, src, count);
909 }
910 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
911 bz->f1 = new_f1; /* next frame */
912 dev_kfree_skb(bch->tx_skb);
913 get_next_bframe(bch);
914 }
915
916
917
918 /*
919 * handle L1 state changes TE
920 */
921
922 static void
923 ph_state_te(struct dchannel *dch)
924 {
925 if (dch->debug)
926 printk(KERN_DEBUG "%s: TE newstate %x\n",
927 __func__, dch->state);
928 switch (dch->state) {
929 case 0:
930 l1_event(dch->l1, HW_RESET_IND);
931 break;
932 case 3:
933 l1_event(dch->l1, HW_DEACT_IND);
934 break;
935 case 5:
936 case 8:
937 l1_event(dch->l1, ANYSIGNAL);
938 break;
939 case 6:
940 l1_event(dch->l1, INFO2);
941 break;
942 case 7:
943 l1_event(dch->l1, INFO4_P8);
944 break;
945 }
946 }
947
948 /*
949 * handle L1 state changes NT
950 */
951
952 static void
953 handle_nt_timer3(struct dchannel *dch) {
954 struct hfc_pci *hc = dch->hw;
955
956 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
957 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
958 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
959 hc->hw.nt_timer = 0;
960 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
961 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
962 hc->hw.mst_m |= HFCPCI_MASTER;
963 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
964 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
965 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
966 }
967
968 static void
969 ph_state_nt(struct dchannel *dch)
970 {
971 struct hfc_pci *hc = dch->hw;
972
973 if (dch->debug)
974 printk(KERN_DEBUG "%s: NT newstate %x\n",
975 __func__, dch->state);
976 switch (dch->state) {
977 case 2:
978 if (hc->hw.nt_timer < 0) {
979 hc->hw.nt_timer = 0;
980 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
981 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
982 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
983 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
984 /* Clear already pending ints */
985 (void) Read_hfc(hc, HFCPCI_INT_S1);
986 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
987 udelay(10);
988 Write_hfc(hc, HFCPCI_STATES, 4);
989 dch->state = 4;
990 } else if (hc->hw.nt_timer == 0) {
991 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
992 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
993 hc->hw.nt_timer = NT_T1_COUNT;
994 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
995 hc->hw.ctmt |= HFCPCI_TIM3_125;
996 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
997 HFCPCI_CLTIMER);
998 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
999 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1000 /* allow G2 -> G3 transition */
1001 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1002 } else {
1003 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1004 }
1005 break;
1006 case 1:
1007 hc->hw.nt_timer = 0;
1008 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1009 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1010 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1011 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1012 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1013 hc->hw.mst_m &= ~HFCPCI_MASTER;
1014 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1015 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1016 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1017 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1018 break;
1019 case 4:
1020 hc->hw.nt_timer = 0;
1021 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1022 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1023 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1024 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1025 break;
1026 case 3:
1027 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1028 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1029 &dch->Flags)) {
1030 handle_nt_timer3(dch);
1031 break;
1032 }
1033 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1034 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1035 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1036 hc->hw.nt_timer = NT_T3_COUNT;
1037 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1038 hc->hw.ctmt |= HFCPCI_TIM3_125;
1039 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1040 HFCPCI_CLTIMER);
1041 }
1042 break;
1043 }
1044 }
1045
1046 static void
1047 ph_state(struct dchannel *dch)
1048 {
1049 struct hfc_pci *hc = dch->hw;
1050
1051 if (hc->hw.protocol == ISDN_P_NT_S0) {
1052 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1053 hc->hw.nt_timer < 0)
1054 handle_nt_timer3(dch);
1055 else
1056 ph_state_nt(dch);
1057 } else
1058 ph_state_te(dch);
1059 }
1060
1061 /*
1062 * Layer 1 callback function
1063 */
1064 static int
1065 hfc_l1callback(struct dchannel *dch, u_int cmd)
1066 {
1067 struct hfc_pci *hc = dch->hw;
1068
1069 switch (cmd) {
1070 case INFO3_P8:
1071 case INFO3_P10:
1072 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1073 hc->hw.mst_m |= HFCPCI_MASTER;
1074 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1075 break;
1076 case HW_RESET_REQ:
1077 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1078 /* HFC ST 3 */
1079 udelay(6);
1080 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1081 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1082 hc->hw.mst_m |= HFCPCI_MASTER;
1083 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1084 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1085 HFCPCI_DO_ACTION);
1086 l1_event(dch->l1, HW_POWERUP_IND);
1087 break;
1088 case HW_DEACT_REQ:
1089 hc->hw.mst_m &= ~HFCPCI_MASTER;
1090 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1091 skb_queue_purge(&dch->squeue);
1092 if (dch->tx_skb) {
1093 dev_kfree_skb(dch->tx_skb);
1094 dch->tx_skb = NULL;
1095 }
1096 dch->tx_idx = 0;
1097 if (dch->rx_skb) {
1098 dev_kfree_skb(dch->rx_skb);
1099 dch->rx_skb = NULL;
1100 }
1101 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1102 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1103 del_timer(&dch->timer);
1104 break;
1105 case HW_POWERUP_REQ:
1106 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1107 break;
1108 case PH_ACTIVATE_IND:
1109 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1110 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1111 GFP_ATOMIC);
1112 break;
1113 case PH_DEACTIVATE_IND:
1114 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1115 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1116 GFP_ATOMIC);
1117 break;
1118 default:
1119 if (dch->debug & DEBUG_HW)
1120 printk(KERN_DEBUG "%s: unknown command %x\n",
1121 __func__, cmd);
1122 return -1;
1123 }
1124 return 0;
1125 }
1126
1127 /*
1128 * Interrupt handler
1129 */
1130 static inline void
1131 tx_birq(struct bchannel *bch)
1132 {
1133 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1134 hfcpci_fill_fifo(bch);
1135 else {
1136 if (bch->tx_skb)
1137 dev_kfree_skb(bch->tx_skb);
1138 if (get_next_bframe(bch))
1139 hfcpci_fill_fifo(bch);
1140 }
1141 }
1142
1143 static inline void
1144 tx_dirq(struct dchannel *dch)
1145 {
1146 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1147 hfcpci_fill_dfifo(dch->hw);
1148 else {
1149 if (dch->tx_skb)
1150 dev_kfree_skb(dch->tx_skb);
1151 if (get_next_dframe(dch))
1152 hfcpci_fill_dfifo(dch->hw);
1153 }
1154 }
1155
1156 static irqreturn_t
1157 hfcpci_int(int intno, void *dev_id)
1158 {
1159 struct hfc_pci *hc = dev_id;
1160 u_char exval;
1161 struct bchannel *bch;
1162 u_char val, stat;
1163
1164 spin_lock(&hc->lock);
1165 if (!(hc->hw.int_m2 & 0x08)) {
1166 spin_unlock(&hc->lock);
1167 return IRQ_NONE; /* not initialised */
1168 }
1169 stat = Read_hfc(hc, HFCPCI_STATUS);
1170 if (HFCPCI_ANYINT & stat) {
1171 val = Read_hfc(hc, HFCPCI_INT_S1);
1172 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1173 printk(KERN_DEBUG
1174 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1175 } else {
1176 /* shared */
1177 spin_unlock(&hc->lock);
1178 return IRQ_NONE;
1179 }
1180 hc->irqcnt++;
1181
1182 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1183 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1184 val &= hc->hw.int_m1;
1185 if (val & 0x40) { /* state machine irq */
1186 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1187 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1188 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1189 hc->dch.state, exval);
1190 hc->dch.state = exval;
1191 schedule_event(&hc->dch, FLG_PHCHANGE);
1192 val &= ~0x40;
1193 }
1194 if (val & 0x80) { /* timer irq */
1195 if (hc->hw.protocol == ISDN_P_NT_S0) {
1196 if ((--hc->hw.nt_timer) < 0)
1197 schedule_event(&hc->dch, FLG_PHCHANGE);
1198 }
1199 val &= ~0x80;
1200 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1201 }
1202 if (val & 0x08) { /* B1 rx */
1203 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1204 if (bch)
1205 main_rec_hfcpci(bch);
1206 else if (hc->dch.debug)
1207 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1208 }
1209 if (val & 0x10) { /* B2 rx */
1210 bch = Sel_BCS(hc, 2);
1211 if (bch)
1212 main_rec_hfcpci(bch);
1213 else if (hc->dch.debug)
1214 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1215 }
1216 if (val & 0x01) { /* B1 tx */
1217 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1218 if (bch)
1219 tx_birq(bch);
1220 else if (hc->dch.debug)
1221 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1222 }
1223 if (val & 0x02) { /* B2 tx */
1224 bch = Sel_BCS(hc, 2);
1225 if (bch)
1226 tx_birq(bch);
1227 else if (hc->dch.debug)
1228 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1229 }
1230 if (val & 0x20) /* D rx */
1231 receive_dmsg(hc);
1232 if (val & 0x04) { /* D tx */
1233 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1234 del_timer(&hc->dch.timer);
1235 tx_dirq(&hc->dch);
1236 }
1237 spin_unlock(&hc->lock);
1238 return IRQ_HANDLED;
1239 }
1240
1241 /*
1242 * timer callback for D-chan busy resolution. Currently no function
1243 */
1244 static void
1245 hfcpci_dbusy_timer(struct timer_list *t)
1246 {
1247 }
1248
1249 /*
1250 * activate/deactivate hardware for selected channels and mode
1251 */
1252 static int
1253 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1254 {
1255 struct hfc_pci *hc = bch->hw;
1256 int fifo2;
1257 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1258
1259 if (bch->debug & DEBUG_HW_BCHANNEL)
1260 printk(KERN_DEBUG
1261 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1262 bch->state, protocol, bch->nr, bc);
1263
1264 fifo2 = bc;
1265 pcm_mode = (bc >> 24) & 0xff;
1266 if (pcm_mode) { /* PCM SLOT USE */
1267 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1268 printk(KERN_WARNING
1269 "%s: pcm channel id without HFC_CFG_PCM\n",
1270 __func__);
1271 rx_slot = (bc >> 8) & 0xff;
1272 tx_slot = (bc >> 16) & 0xff;
1273 bc = bc & 0xff;
1274 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1275 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1276 __func__);
1277 if (hc->chanlimit > 1) {
1278 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1279 hc->hw.sctrl_e &= ~0x80;
1280 } else {
1281 if (bc & 2) {
1282 if (protocol != ISDN_P_NONE) {
1283 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1284 hc->hw.sctrl_e |= 0x80;
1285 } else {
1286 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1287 hc->hw.sctrl_e &= ~0x80;
1288 }
1289 fifo2 = 1;
1290 } else {
1291 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1292 hc->hw.sctrl_e &= ~0x80;
1293 }
1294 }
1295 switch (protocol) {
1296 case (-1): /* used for init */
1297 bch->state = -1;
1298 bch->nr = bc;
1299 case (ISDN_P_NONE):
1300 if (bch->state == ISDN_P_NONE)
1301 return 0;
1302 if (bc & 2) {
1303 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1304 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1305 } else {
1306 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1307 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1308 }
1309 if (fifo2 & 2) {
1310 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1311 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS |
1312 HFCPCI_INTS_B2REC);
1313 } else {
1314 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1315 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS |
1316 HFCPCI_INTS_B1REC);
1317 }
1318 #ifdef REVERSE_BITORDER
1319 if (bch->nr & 2)
1320 hc->hw.cirm &= 0x7f;
1321 else
1322 hc->hw.cirm &= 0xbf;
1323 #endif
1324 bch->state = ISDN_P_NONE;
1325 bch->nr = bc;
1326 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1327 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1328 break;
1329 case (ISDN_P_B_RAW):
1330 bch->state = protocol;
1331 bch->nr = bc;
1332 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1333 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1334 if (bc & 2) {
1335 hc->hw.sctrl |= SCTRL_B2_ENA;
1336 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1337 #ifdef REVERSE_BITORDER
1338 hc->hw.cirm |= 0x80;
1339 #endif
1340 } else {
1341 hc->hw.sctrl |= SCTRL_B1_ENA;
1342 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1343 #ifdef REVERSE_BITORDER
1344 hc->hw.cirm |= 0x40;
1345 #endif
1346 }
1347 if (fifo2 & 2) {
1348 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1349 if (!tics)
1350 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1351 HFCPCI_INTS_B2REC);
1352 hc->hw.ctmt |= 2;
1353 hc->hw.conn &= ~0x18;
1354 } else {
1355 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1356 if (!tics)
1357 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1358 HFCPCI_INTS_B1REC);
1359 hc->hw.ctmt |= 1;
1360 hc->hw.conn &= ~0x03;
1361 }
1362 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1363 break;
1364 case (ISDN_P_B_HDLC):
1365 bch->state = protocol;
1366 bch->nr = bc;
1367 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1368 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1369 if (bc & 2) {
1370 hc->hw.sctrl |= SCTRL_B2_ENA;
1371 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1372 } else {
1373 hc->hw.sctrl |= SCTRL_B1_ENA;
1374 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1375 }
1376 if (fifo2 & 2) {
1377 hc->hw.last_bfifo_cnt[1] = 0;
1378 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1379 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1380 HFCPCI_INTS_B2REC);
1381 hc->hw.ctmt &= ~2;
1382 hc->hw.conn &= ~0x18;
1383 } else {
1384 hc->hw.last_bfifo_cnt[0] = 0;
1385 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1386 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1387 HFCPCI_INTS_B1REC);
1388 hc->hw.ctmt &= ~1;
1389 hc->hw.conn &= ~0x03;
1390 }
1391 test_and_set_bit(FLG_HDLC, &bch->Flags);
1392 break;
1393 default:
1394 printk(KERN_DEBUG "prot not known %x\n", protocol);
1395 return -ENOPROTOOPT;
1396 }
1397 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1398 if ((protocol == ISDN_P_NONE) ||
1399 (protocol == -1)) { /* init case */
1400 rx_slot = 0;
1401 tx_slot = 0;
1402 } else {
1403 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1404 rx_slot |= 0xC0;
1405 tx_slot |= 0xC0;
1406 } else {
1407 rx_slot |= 0x80;
1408 tx_slot |= 0x80;
1409 }
1410 }
1411 if (bc & 2) {
1412 hc->hw.conn &= 0xc7;
1413 hc->hw.conn |= 0x08;
1414 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1415 __func__, tx_slot);
1416 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1417 __func__, rx_slot);
1418 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1419 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1420 } else {
1421 hc->hw.conn &= 0xf8;
1422 hc->hw.conn |= 0x01;
1423 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1424 __func__, tx_slot);
1425 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1426 __func__, rx_slot);
1427 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1428 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1429 }
1430 }
1431 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1432 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1433 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1434 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1435 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1436 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1437 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1438 #ifdef REVERSE_BITORDER
1439 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1440 #endif
1441 return 0;
1442 }
1443
1444 static int
1445 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1446 {
1447 struct hfc_pci *hc = bch->hw;
1448
1449 if (bch->debug & DEBUG_HW_BCHANNEL)
1450 printk(KERN_DEBUG
1451 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1452 bch->state, protocol, bch->nr, chan);
1453 if (bch->nr != chan) {
1454 printk(KERN_DEBUG
1455 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1456 bch->nr, chan);
1457 return -EINVAL;
1458 }
1459 switch (protocol) {
1460 case (ISDN_P_B_RAW):
1461 bch->state = protocol;
1462 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1463 if (chan & 2) {
1464 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1465 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1466 if (!tics)
1467 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1468 hc->hw.ctmt |= 2;
1469 hc->hw.conn &= ~0x18;
1470 #ifdef REVERSE_BITORDER
1471 hc->hw.cirm |= 0x80;
1472 #endif
1473 } else {
1474 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1475 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1476 if (!tics)
1477 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1478 hc->hw.ctmt |= 1;
1479 hc->hw.conn &= ~0x03;
1480 #ifdef REVERSE_BITORDER
1481 hc->hw.cirm |= 0x40;
1482 #endif
1483 }
1484 break;
1485 case (ISDN_P_B_HDLC):
1486 bch->state = protocol;
1487 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1488 if (chan & 2) {
1489 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1490 hc->hw.last_bfifo_cnt[1] = 0;
1491 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1492 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1493 hc->hw.ctmt &= ~2;
1494 hc->hw.conn &= ~0x18;
1495 } else {
1496 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1497 hc->hw.last_bfifo_cnt[0] = 0;
1498 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1499 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1500 hc->hw.ctmt &= ~1;
1501 hc->hw.conn &= ~0x03;
1502 }
1503 break;
1504 default:
1505 printk(KERN_DEBUG "prot not known %x\n", protocol);
1506 return -ENOPROTOOPT;
1507 }
1508 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1509 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1510 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1511 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1512 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1513 #ifdef REVERSE_BITORDER
1514 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1515 #endif
1516 return 0;
1517 }
1518
1519 static void
1520 deactivate_bchannel(struct bchannel *bch)
1521 {
1522 struct hfc_pci *hc = bch->hw;
1523 u_long flags;
1524
1525 spin_lock_irqsave(&hc->lock, flags);
1526 mISDN_clear_bchannel(bch);
1527 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1528 spin_unlock_irqrestore(&hc->lock, flags);
1529 }
1530
1531 /*
1532 * Layer 1 B-channel hardware access
1533 */
1534 static int
1535 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1536 {
1537 return mISDN_ctrl_bchannel(bch, cq);
1538 }
1539 static int
1540 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1541 {
1542 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1543 struct hfc_pci *hc = bch->hw;
1544 int ret = -EINVAL;
1545 u_long flags;
1546
1547 if (bch->debug & DEBUG_HW)
1548 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1549 switch (cmd) {
1550 case HW_TESTRX_RAW:
1551 spin_lock_irqsave(&hc->lock, flags);
1552 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1553 spin_unlock_irqrestore(&hc->lock, flags);
1554 break;
1555 case HW_TESTRX_HDLC:
1556 spin_lock_irqsave(&hc->lock, flags);
1557 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1558 spin_unlock_irqrestore(&hc->lock, flags);
1559 break;
1560 case HW_TESTRX_OFF:
1561 spin_lock_irqsave(&hc->lock, flags);
1562 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1563 spin_unlock_irqrestore(&hc->lock, flags);
1564 ret = 0;
1565 break;
1566 case CLOSE_CHANNEL:
1567 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1568 deactivate_bchannel(bch);
1569 ch->protocol = ISDN_P_NONE;
1570 ch->peer = NULL;
1571 module_put(THIS_MODULE);
1572 ret = 0;
1573 break;
1574 case CONTROL_CHANNEL:
1575 ret = channel_bctrl(bch, arg);
1576 break;
1577 default:
1578 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1579 __func__, cmd);
1580 }
1581 return ret;
1582 }
1583
1584 /*
1585 * Layer2 -> Layer 1 Dchannel data
1586 */
1587 static int
1588 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1589 {
1590 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1591 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1592 struct hfc_pci *hc = dch->hw;
1593 int ret = -EINVAL;
1594 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1595 unsigned int id;
1596 u_long flags;
1597
1598 switch (hh->prim) {
1599 case PH_DATA_REQ:
1600 spin_lock_irqsave(&hc->lock, flags);
1601 ret = dchannel_senddata(dch, skb);
1602 if (ret > 0) { /* direct TX */
1603 id = hh->id; /* skb can be freed */
1604 hfcpci_fill_dfifo(dch->hw);
1605 ret = 0;
1606 spin_unlock_irqrestore(&hc->lock, flags);
1607 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1608 } else
1609 spin_unlock_irqrestore(&hc->lock, flags);
1610 return ret;
1611 case PH_ACTIVATE_REQ:
1612 spin_lock_irqsave(&hc->lock, flags);
1613 if (hc->hw.protocol == ISDN_P_NT_S0) {
1614 ret = 0;
1615 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1616 hc->hw.mst_m |= HFCPCI_MASTER;
1617 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1618 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1619 spin_unlock_irqrestore(&hc->lock, flags);
1620 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1621 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1622 break;
1623 }
1624 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1625 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1626 HFCPCI_DO_ACTION | 1);
1627 } else
1628 ret = l1_event(dch->l1, hh->prim);
1629 spin_unlock_irqrestore(&hc->lock, flags);
1630 break;
1631 case PH_DEACTIVATE_REQ:
1632 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1633 spin_lock_irqsave(&hc->lock, flags);
1634 if (hc->hw.protocol == ISDN_P_NT_S0) {
1635 /* prepare deactivation */
1636 Write_hfc(hc, HFCPCI_STATES, 0x40);
1637 skb_queue_purge(&dch->squeue);
1638 if (dch->tx_skb) {
1639 dev_kfree_skb(dch->tx_skb);
1640 dch->tx_skb = NULL;
1641 }
1642 dch->tx_idx = 0;
1643 if (dch->rx_skb) {
1644 dev_kfree_skb(dch->rx_skb);
1645 dch->rx_skb = NULL;
1646 }
1647 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1648 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1649 del_timer(&dch->timer);
1650 #ifdef FIXME
1651 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1652 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1653 #endif
1654 hc->hw.mst_m &= ~HFCPCI_MASTER;
1655 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1656 ret = 0;
1657 } else {
1658 ret = l1_event(dch->l1, hh->prim);
1659 }
1660 spin_unlock_irqrestore(&hc->lock, flags);
1661 break;
1662 }
1663 if (!ret)
1664 dev_kfree_skb(skb);
1665 return ret;
1666 }
1667
1668 /*
1669 * Layer2 -> Layer 1 Bchannel data
1670 */
1671 static int
1672 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1673 {
1674 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1675 struct hfc_pci *hc = bch->hw;
1676 int ret = -EINVAL;
1677 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1678 unsigned long flags;
1679
1680 switch (hh->prim) {
1681 case PH_DATA_REQ:
1682 spin_lock_irqsave(&hc->lock, flags);
1683 ret = bchannel_senddata(bch, skb);
1684 if (ret > 0) { /* direct TX */
1685 hfcpci_fill_fifo(bch);
1686 ret = 0;
1687 }
1688 spin_unlock_irqrestore(&hc->lock, flags);
1689 return ret;
1690 case PH_ACTIVATE_REQ:
1691 spin_lock_irqsave(&hc->lock, flags);
1692 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1693 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1694 else
1695 ret = 0;
1696 spin_unlock_irqrestore(&hc->lock, flags);
1697 if (!ret)
1698 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1699 NULL, GFP_KERNEL);
1700 break;
1701 case PH_DEACTIVATE_REQ:
1702 deactivate_bchannel(bch);
1703 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1704 NULL, GFP_KERNEL);
1705 ret = 0;
1706 break;
1707 }
1708 if (!ret)
1709 dev_kfree_skb(skb);
1710 return ret;
1711 }
1712
1713 /*
1714 * called for card init message
1715 */
1716
1717 static void
1718 inithfcpci(struct hfc_pci *hc)
1719 {
1720 printk(KERN_DEBUG "inithfcpci: entered\n");
1721 timer_setup(&hc->dch.timer, hfcpci_dbusy_timer, 0);
1722 hc->chanlimit = 2;
1723 mode_hfcpci(&hc->bch[0], 1, -1);
1724 mode_hfcpci(&hc->bch[1], 2, -1);
1725 }
1726
1727
1728 static int
1729 init_card(struct hfc_pci *hc)
1730 {
1731 int cnt = 3;
1732 u_long flags;
1733
1734 printk(KERN_DEBUG "init_card: entered\n");
1735
1736
1737 spin_lock_irqsave(&hc->lock, flags);
1738 disable_hwirq(hc);
1739 spin_unlock_irqrestore(&hc->lock, flags);
1740 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1741 printk(KERN_WARNING
1742 "mISDN: couldn't get interrupt %d\n", hc->irq);
1743 return -EIO;
1744 }
1745 spin_lock_irqsave(&hc->lock, flags);
1746 reset_hfcpci(hc);
1747 while (cnt) {
1748 inithfcpci(hc);
1749 /*
1750 * Finally enable IRQ output
1751 * this is only allowed, if an IRQ routine is already
1752 * established for this HFC, so don't do that earlier
1753 */
1754 enable_hwirq(hc);
1755 spin_unlock_irqrestore(&hc->lock, flags);
1756 /* Timeout 80ms */
1757 set_current_state(TASK_UNINTERRUPTIBLE);
1758 schedule_timeout((80 * HZ) / 1000);
1759 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1760 hc->irq, hc->irqcnt);
1761 /* now switch timer interrupt off */
1762 spin_lock_irqsave(&hc->lock, flags);
1763 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1764 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1765 /* reinit mode reg */
1766 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1767 if (!hc->irqcnt) {
1768 printk(KERN_WARNING
1769 "HFC PCI: IRQ(%d) getting no interrupts "
1770 "during init %d\n", hc->irq, 4 - cnt);
1771 if (cnt == 1)
1772 break;
1773 else {
1774 reset_hfcpci(hc);
1775 cnt--;
1776 }
1777 } else {
1778 spin_unlock_irqrestore(&hc->lock, flags);
1779 hc->initdone = 1;
1780 return 0;
1781 }
1782 }
1783 disable_hwirq(hc);
1784 spin_unlock_irqrestore(&hc->lock, flags);
1785 free_irq(hc->irq, hc);
1786 return -EIO;
1787 }
1788
1789 static int
1790 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1791 {
1792 int ret = 0;
1793 u_char slot;
1794
1795 switch (cq->op) {
1796 case MISDN_CTRL_GETOP:
1797 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1798 MISDN_CTRL_DISCONNECT | MISDN_CTRL_L1_TIMER3;
1799 break;
1800 case MISDN_CTRL_LOOP:
1801 /* channel 0 disabled loop */
1802 if (cq->channel < 0 || cq->channel > 2) {
1803 ret = -EINVAL;
1804 break;
1805 }
1806 if (cq->channel & 1) {
1807 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1808 slot = 0xC0;
1809 else
1810 slot = 0x80;
1811 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1812 __func__, slot);
1813 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1814 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1815 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1816 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1817 }
1818 if (cq->channel & 2) {
1819 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1820 slot = 0xC1;
1821 else
1822 slot = 0x81;
1823 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1824 __func__, slot);
1825 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1826 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1827 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1828 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1829 }
1830 if (cq->channel & 3)
1831 hc->hw.trm |= 0x80; /* enable IOM-loop */
1832 else {
1833 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1834 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1835 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1836 }
1837 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1838 break;
1839 case MISDN_CTRL_CONNECT:
1840 if (cq->channel == cq->p1) {
1841 ret = -EINVAL;
1842 break;
1843 }
1844 if (cq->channel < 1 || cq->channel > 2 ||
1845 cq->p1 < 1 || cq->p1 > 2) {
1846 ret = -EINVAL;
1847 break;
1848 }
1849 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1850 slot = 0xC0;
1851 else
1852 slot = 0x80;
1853 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1854 __func__, slot);
1855 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1856 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1857 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1858 slot = 0xC1;
1859 else
1860 slot = 0x81;
1861 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1862 __func__, slot);
1863 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1864 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1865 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1866 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1867 hc->hw.trm |= 0x80;
1868 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1869 break;
1870 case MISDN_CTRL_DISCONNECT:
1871 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1872 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1873 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1874 break;
1875 case MISDN_CTRL_L1_TIMER3:
1876 ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
1877 break;
1878 default:
1879 printk(KERN_WARNING "%s: unknown Op %x\n",
1880 __func__, cq->op);
1881 ret = -EINVAL;
1882 break;
1883 }
1884 return ret;
1885 }
1886
1887 static int
1888 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1889 struct channel_req *rq)
1890 {
1891 int err = 0;
1892
1893 if (debug & DEBUG_HW_OPEN)
1894 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1895 hc->dch.dev.id, __builtin_return_address(0));
1896 if (rq->protocol == ISDN_P_NONE)
1897 return -EINVAL;
1898 if (rq->adr.channel == 1) {
1899 /* TODO: E-Channel */
1900 return -EINVAL;
1901 }
1902 if (!hc->initdone) {
1903 if (rq->protocol == ISDN_P_TE_S0) {
1904 err = create_l1(&hc->dch, hfc_l1callback);
1905 if (err)
1906 return err;
1907 }
1908 hc->hw.protocol = rq->protocol;
1909 ch->protocol = rq->protocol;
1910 err = init_card(hc);
1911 if (err)
1912 return err;
1913 } else {
1914 if (rq->protocol != ch->protocol) {
1915 if (hc->hw.protocol == ISDN_P_TE_S0)
1916 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1917 if (rq->protocol == ISDN_P_TE_S0) {
1918 err = create_l1(&hc->dch, hfc_l1callback);
1919 if (err)
1920 return err;
1921 }
1922 hc->hw.protocol = rq->protocol;
1923 ch->protocol = rq->protocol;
1924 hfcpci_setmode(hc);
1925 }
1926 }
1927
1928 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1929 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1930 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1931 0, NULL, GFP_KERNEL);
1932 }
1933 rq->ch = ch;
1934 if (!try_module_get(THIS_MODULE))
1935 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1936 return 0;
1937 }
1938
1939 static int
1940 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1941 {
1942 struct bchannel *bch;
1943
1944 if (rq->adr.channel == 0 || rq->adr.channel > 2)
1945 return -EINVAL;
1946 if (rq->protocol == ISDN_P_NONE)
1947 return -EINVAL;
1948 bch = &hc->bch[rq->adr.channel - 1];
1949 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1950 return -EBUSY; /* b-channel can be only open once */
1951 bch->ch.protocol = rq->protocol;
1952 rq->ch = &bch->ch; /* TODO: E-channel */
1953 if (!try_module_get(THIS_MODULE))
1954 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1955 return 0;
1956 }
1957
1958 /*
1959 * device control function
1960 */
1961 static int
1962 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1963 {
1964 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1965 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1966 struct hfc_pci *hc = dch->hw;
1967 struct channel_req *rq;
1968 int err = 0;
1969
1970 if (dch->debug & DEBUG_HW)
1971 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1972 __func__, cmd, arg);
1973 switch (cmd) {
1974 case OPEN_CHANNEL:
1975 rq = arg;
1976 if ((rq->protocol == ISDN_P_TE_S0) ||
1977 (rq->protocol == ISDN_P_NT_S0))
1978 err = open_dchannel(hc, ch, rq);
1979 else
1980 err = open_bchannel(hc, rq);
1981 break;
1982 case CLOSE_CHANNEL:
1983 if (debug & DEBUG_HW_OPEN)
1984 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1985 __func__, hc->dch.dev.id,
1986 __builtin_return_address(0));
1987 module_put(THIS_MODULE);
1988 break;
1989 case CONTROL_CHANNEL:
1990 err = channel_ctrl(hc, arg);
1991 break;
1992 default:
1993 if (dch->debug & DEBUG_HW)
1994 printk(KERN_DEBUG "%s: unknown command %x\n",
1995 __func__, cmd);
1996 return -EINVAL;
1997 }
1998 return err;
1999 }
2000
2001 static int
2002 setup_hw(struct hfc_pci *hc)
2003 {
2004 void *buffer;
2005
2006 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2007 hc->hw.cirm = 0;
2008 hc->dch.state = 0;
2009 pci_set_master(hc->pdev);
2010 if (!hc->irq) {
2011 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2012 return 1;
2013 }
2014 hc->hw.pci_io =
2015 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2016
2017 if (!hc->hw.pci_io) {
2018 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2019 return 1;
2020 }
2021 /* Allocate memory for FIFOS */
2022 /* the memory needs to be on a 32k boundary within the first 4G */
2023 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2024 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2025 /* We silently assume the address is okay if nonzero */
2026 if (!buffer) {
2027 printk(KERN_WARNING
2028 "HFC-PCI: Error allocating memory for FIFO!\n");
2029 return 1;
2030 }
2031 hc->hw.fifos = buffer;
2032 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2033 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2034 printk(KERN_INFO
2035 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2036 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2037 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2038 /* enable memory mapped ports, disable busmaster */
2039 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2040 hc->hw.int_m2 = 0;
2041 disable_hwirq(hc);
2042 hc->hw.int_m1 = 0;
2043 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2044 /* At this point the needed PCI config is done */
2045 /* fifos are still not enabled */
2046 timer_setup(&hc->hw.timer, hfcpci_Timer, 0);
2047 /* default PCM master */
2048 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2049 return 0;
2050 }
2051
2052 static void
2053 release_card(struct hfc_pci *hc) {
2054 u_long flags;
2055
2056 spin_lock_irqsave(&hc->lock, flags);
2057 hc->hw.int_m2 = 0; /* interrupt output off ! */
2058 disable_hwirq(hc);
2059 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2060 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2061 if (hc->dch.timer.function != NULL) {
2062 del_timer(&hc->dch.timer);
2063 hc->dch.timer.function = NULL;
2064 }
2065 spin_unlock_irqrestore(&hc->lock, flags);
2066 if (hc->hw.protocol == ISDN_P_TE_S0)
2067 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2068 if (hc->initdone)
2069 free_irq(hc->irq, hc);
2070 release_io_hfcpci(hc); /* must release after free_irq! */
2071 mISDN_unregister_device(&hc->dch.dev);
2072 mISDN_freebchannel(&hc->bch[1]);
2073 mISDN_freebchannel(&hc->bch[0]);
2074 mISDN_freedchannel(&hc->dch);
2075 pci_set_drvdata(hc->pdev, NULL);
2076 kfree(hc);
2077 }
2078
2079 static int
2080 setup_card(struct hfc_pci *card)
2081 {
2082 int err = -EINVAL;
2083 u_int i;
2084 char name[MISDN_MAX_IDLEN];
2085
2086 card->dch.debug = debug;
2087 spin_lock_init(&card->lock);
2088 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2089 card->dch.hw = card;
2090 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2091 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2092 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2093 card->dch.dev.D.send = hfcpci_l2l1D;
2094 card->dch.dev.D.ctrl = hfc_dctrl;
2095 card->dch.dev.nrbchan = 2;
2096 for (i = 0; i < 2; i++) {
2097 card->bch[i].nr = i + 1;
2098 set_channelmap(i + 1, card->dch.dev.channelmap);
2099 card->bch[i].debug = debug;
2100 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM, poll >> 1);
2101 card->bch[i].hw = card;
2102 card->bch[i].ch.send = hfcpci_l2l1B;
2103 card->bch[i].ch.ctrl = hfc_bctrl;
2104 card->bch[i].ch.nr = i + 1;
2105 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2106 }
2107 err = setup_hw(card);
2108 if (err)
2109 goto error;
2110 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2111 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2112 if (err)
2113 goto error;
2114 HFC_cnt++;
2115 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2116 return 0;
2117 error:
2118 mISDN_freebchannel(&card->bch[1]);
2119 mISDN_freebchannel(&card->bch[0]);
2120 mISDN_freedchannel(&card->dch);
2121 kfree(card);
2122 return err;
2123 }
2124
2125 /* private data in the PCI devices list */
2126 struct _hfc_map {
2127 u_int subtype;
2128 u_int flag;
2129 char *name;
2130 };
2131
2132 static const struct _hfc_map hfc_map[] =
2133 {
2134 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2135 {HFC_CCD_B000, 0, "Billion B000"},
2136 {HFC_CCD_B006, 0, "Billion B006"},
2137 {HFC_CCD_B007, 0, "Billion B007"},
2138 {HFC_CCD_B008, 0, "Billion B008"},
2139 {HFC_CCD_B009, 0, "Billion B009"},
2140 {HFC_CCD_B00A, 0, "Billion B00A"},
2141 {HFC_CCD_B00B, 0, "Billion B00B"},
2142 {HFC_CCD_B00C, 0, "Billion B00C"},
2143 {HFC_CCD_B100, 0, "Seyeon B100"},
2144 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2145 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2146 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2147 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2148 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2149 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2150 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2151 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2152 {HFC_DIGI_DF_M_IOM2_E, 0,
2153 "Digi International DataFire Micro V IOM2 (Europe)"},
2154 {HFC_DIGI_DF_M_E, 0,
2155 "Digi International DataFire Micro V (Europe)"},
2156 {HFC_DIGI_DF_M_IOM2_A, 0,
2157 "Digi International DataFire Micro V IOM2 (North America)"},
2158 {HFC_DIGI_DF_M_A, 0,
2159 "Digi International DataFire Micro V (North America)"},
2160 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2161 {},
2162 };
2163
2164 static const struct pci_device_id hfc_ids[] =
2165 {
2166 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2167 (unsigned long) &hfc_map[0] },
2168 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2169 (unsigned long) &hfc_map[1] },
2170 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2171 (unsigned long) &hfc_map[2] },
2172 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2173 (unsigned long) &hfc_map[3] },
2174 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2175 (unsigned long) &hfc_map[4] },
2176 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2177 (unsigned long) &hfc_map[5] },
2178 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2179 (unsigned long) &hfc_map[6] },
2180 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2181 (unsigned long) &hfc_map[7] },
2182 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2183 (unsigned long) &hfc_map[8] },
2184 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2185 (unsigned long) &hfc_map[9] },
2186 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2187 (unsigned long) &hfc_map[10] },
2188 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2189 (unsigned long) &hfc_map[11] },
2190 { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2191 (unsigned long) &hfc_map[12] },
2192 { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2193 (unsigned long) &hfc_map[13] },
2194 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2195 (unsigned long) &hfc_map[14] },
2196 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2197 (unsigned long) &hfc_map[15] },
2198 { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2199 (unsigned long) &hfc_map[16] },
2200 { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2201 (unsigned long) &hfc_map[17] },
2202 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2203 (unsigned long) &hfc_map[18] },
2204 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2205 (unsigned long) &hfc_map[19] },
2206 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2207 (unsigned long) &hfc_map[20] },
2208 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2209 (unsigned long) &hfc_map[21] },
2210 { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2211 (unsigned long) &hfc_map[22] },
2212 {},
2213 };
2214
2215 static int
2216 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2217 {
2218 int err = -ENOMEM;
2219 struct hfc_pci *card;
2220 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2221
2222 card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2223 if (!card) {
2224 printk(KERN_ERR "No kmem for HFC card\n");
2225 return err;
2226 }
2227 card->pdev = pdev;
2228 card->subtype = m->subtype;
2229 err = pci_enable_device(pdev);
2230 if (err) {
2231 kfree(card);
2232 return err;
2233 }
2234
2235 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2236 m->name, pci_name(pdev));
2237
2238 card->irq = pdev->irq;
2239 pci_set_drvdata(pdev, card);
2240 err = setup_card(card);
2241 if (err)
2242 pci_set_drvdata(pdev, NULL);
2243 return err;
2244 }
2245
2246 static void
2247 hfc_remove_pci(struct pci_dev *pdev)
2248 {
2249 struct hfc_pci *card = pci_get_drvdata(pdev);
2250
2251 if (card)
2252 release_card(card);
2253 else
2254 if (debug)
2255 printk(KERN_DEBUG "%s: drvdata already removed\n",
2256 __func__);
2257 }
2258
2259
2260 static struct pci_driver hfc_driver = {
2261 .name = "hfcpci",
2262 .probe = hfc_probe,
2263 .remove = hfc_remove_pci,
2264 .id_table = hfc_ids,
2265 };
2266
2267 static int
2268 _hfcpci_softirq(struct device *dev, void *unused)
2269 {
2270 struct hfc_pci *hc = dev_get_drvdata(dev);
2271 struct bchannel *bch;
2272 if (hc == NULL)
2273 return 0;
2274
2275 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2276 spin_lock(&hc->lock);
2277 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2278 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2279 main_rec_hfcpci(bch);
2280 tx_birq(bch);
2281 }
2282 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2283 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2284 main_rec_hfcpci(bch);
2285 tx_birq(bch);
2286 }
2287 spin_unlock(&hc->lock);
2288 }
2289 return 0;
2290 }
2291
2292 static void
2293 hfcpci_softirq(struct timer_list *unused)
2294 {
2295 WARN_ON_ONCE(driver_for_each_device(&hfc_driver.driver, NULL, NULL,
2296 _hfcpci_softirq) != 0);
2297
2298 /* if next event would be in the past ... */
2299 if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2300 hfc_jiffies = jiffies + 1;
2301 else
2302 hfc_jiffies += tics;
2303 hfc_tl.expires = hfc_jiffies;
2304 add_timer(&hfc_tl);
2305 }
2306
2307 static int __init
2308 HFC_init(void)
2309 {
2310 int err;
2311
2312 if (!poll)
2313 poll = HFCPCI_BTRANS_THRESHOLD;
2314
2315 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2316 tics = (poll * HZ) / 8000;
2317 if (tics < 1)
2318 tics = 1;
2319 poll = (tics * 8000) / HZ;
2320 if (poll > 256 || poll < 8) {
2321 printk(KERN_ERR "%s: Wrong poll value %d not in range "
2322 "of 8..256.\n", __func__, poll);
2323 err = -EINVAL;
2324 return err;
2325 }
2326 }
2327 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2328 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2329 __func__, poll);
2330 timer_setup(&hfc_tl, hfcpci_softirq, 0);
2331 hfc_tl.expires = jiffies + tics;
2332 hfc_jiffies = hfc_tl.expires;
2333 add_timer(&hfc_tl);
2334 } else
2335 tics = 0; /* indicate the use of controller's timer */
2336
2337 err = pci_register_driver(&hfc_driver);
2338 if (err) {
2339 if (timer_pending(&hfc_tl))
2340 del_timer(&hfc_tl);
2341 }
2342
2343 return err;
2344 }
2345
2346 static void __exit
2347 HFC_cleanup(void)
2348 {
2349 if (timer_pending(&hfc_tl))
2350 del_timer(&hfc_tl);
2351
2352 pci_unregister_driver(&hfc_driver);
2353 }
2354
2355 module_init(HFC_init);
2356 module_exit(HFC_cleanup);
2357
2358 MODULE_DEVICE_TABLE(pci, hfc_ids);
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