3 * hfcpci.c low level driver for CCD's hfc-pci based cards
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * NOTE: only one poll value must be given for all cards
30 * See hfc_pci.h for debug flags.
33 * NOTE: only one poll value must be given for all cards
34 * Give the number of samples for each fifo process.
35 * By default 128 is used. Decrease to reduce delay, increase to
36 * reduce cpu load. If unsure, don't mess with it!
37 * A value of 128 will use controller's interrupt. Other values will
38 * use kernel timer, because the controller will not allow lower values
40 * Also note that the value depends on the kernel timer frequency.
41 * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
42 * If the kernel uses 100 Hz, steps of 80 samples are possible.
43 * If the kernel uses 300 Hz, steps of about 26 samples are possible.
47 #include <linux/interrupt.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/delay.h>
51 #include <linux/mISDNhw.h>
52 #include <linux/slab.h>
56 static const char *hfcpci_revision
= "2.0";
60 static uint poll
, tics
;
61 static struct timer_list hfc_tl
;
62 static unsigned long hfc_jiffies
;
64 MODULE_AUTHOR("Karsten Keil");
65 MODULE_LICENSE("GPL");
66 module_param(debug
, uint
, S_IRUGO
| S_IWUSR
);
67 module_param(poll
, uint
, S_IRUGO
| S_IWUSR
);
102 unsigned char int_m1
;
103 unsigned char int_m2
;
105 unsigned char sctrl_r
;
106 unsigned char sctrl_e
;
108 unsigned char fifo_en
;
109 unsigned char bswapped
;
110 unsigned char protocol
;
112 unsigned char __iomem
*pci_io
; /* start of PCI IO memory */
113 dma_addr_t dmahandle
;
114 void *fifos
; /* FIFO memory */
115 int last_bfifo_cnt
[2];
116 /* marker saving last b-fifo frame count */
117 struct timer_list timer
;
120 #define HFC_CFG_MASTER 1
121 #define HFC_CFG_SLAVE 2
122 #define HFC_CFG_PCM 3
123 #define HFC_CFG_2HFC 4
124 #define HFC_CFG_SLAVEHFC 5
125 #define HFC_CFG_NEG_F0 6
126 #define HFC_CFG_SW_DD_DU 7
128 #define FLG_HFC_TIMER_T1 16
129 #define FLG_HFC_TIMER_T3 17
131 #define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
132 #define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
133 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
134 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
144 struct pci_dev
*pdev
;
146 spinlock_t lock
; /* card lock */
148 struct bchannel bch
[2];
151 /* Interface functions */
153 enable_hwirq(struct hfc_pci
*hc
)
155 hc
->hw
.int_m2
|= HFCPCI_IRQ_ENABLE
;
156 Write_hfc(hc
, HFCPCI_INT_M2
, hc
->hw
.int_m2
);
160 disable_hwirq(struct hfc_pci
*hc
)
162 hc
->hw
.int_m2
&= ~((u_char
)HFCPCI_IRQ_ENABLE
);
163 Write_hfc(hc
, HFCPCI_INT_M2
, hc
->hw
.int_m2
);
167 * free hardware resources used by driver
170 release_io_hfcpci(struct hfc_pci
*hc
)
172 /* disable memory mapped ports + busmaster */
173 pci_write_config_word(hc
->pdev
, PCI_COMMAND
, 0);
174 del_timer(&hc
->hw
.timer
);
175 pci_free_consistent(hc
->pdev
, 0x8000, hc
->hw
.fifos
, hc
->hw
.dmahandle
);
176 iounmap(hc
->hw
.pci_io
);
180 * set mode (NT or TE)
183 hfcpci_setmode(struct hfc_pci
*hc
)
185 if (hc
->hw
.protocol
== ISDN_P_NT_S0
) {
186 hc
->hw
.clkdel
= CLKDEL_NT
; /* ST-Bit delay for NT-Mode */
187 hc
->hw
.sctrl
|= SCTRL_MODE_NT
; /* NT-MODE */
188 hc
->hw
.states
= 1; /* G1 */
190 hc
->hw
.clkdel
= CLKDEL_TE
; /* ST-Bit delay for TE-Mode */
191 hc
->hw
.sctrl
&= ~SCTRL_MODE_NT
; /* TE-MODE */
192 hc
->hw
.states
= 2; /* F2 */
194 Write_hfc(hc
, HFCPCI_CLKDEL
, hc
->hw
.clkdel
);
195 Write_hfc(hc
, HFCPCI_STATES
, HFCPCI_LOAD_STATE
| hc
->hw
.states
);
197 Write_hfc(hc
, HFCPCI_STATES
, hc
->hw
.states
| 0x40); /* Deactivate */
198 Write_hfc(hc
, HFCPCI_SCTRL
, hc
->hw
.sctrl
);
202 * function called to reset the HFC PCI chip. A complete software reset of chip
206 reset_hfcpci(struct hfc_pci
*hc
)
211 printk(KERN_DEBUG
"reset_hfcpci: entered\n");
212 val
= Read_hfc(hc
, HFCPCI_CHIP_ID
);
213 printk(KERN_INFO
"HFC_PCI: resetting HFC ChipId(%x)\n", val
);
214 /* enable memory mapped ports, disable busmaster */
215 pci_write_config_word(hc
->pdev
, PCI_COMMAND
, PCI_ENA_MEMIO
);
217 /* enable memory ports + busmaster */
218 pci_write_config_word(hc
->pdev
, PCI_COMMAND
,
219 PCI_ENA_MEMIO
+ PCI_ENA_MASTER
);
220 val
= Read_hfc(hc
, HFCPCI_STATUS
);
221 printk(KERN_DEBUG
"HFC-PCI status(%x) before reset\n", val
);
222 hc
->hw
.cirm
= HFCPCI_RESET
; /* Reset On */
223 Write_hfc(hc
, HFCPCI_CIRM
, hc
->hw
.cirm
);
224 set_current_state(TASK_UNINTERRUPTIBLE
);
225 mdelay(10); /* Timeout 10ms */
226 hc
->hw
.cirm
= 0; /* Reset Off */
227 Write_hfc(hc
, HFCPCI_CIRM
, hc
->hw
.cirm
);
228 val
= Read_hfc(hc
, HFCPCI_STATUS
);
229 printk(KERN_DEBUG
"HFC-PCI status(%x) after reset\n", val
);
230 while (cnt
< 50000) { /* max 50000 us */
233 val
= Read_hfc(hc
, HFCPCI_STATUS
);
237 printk(KERN_DEBUG
"HFC-PCI status(%x) after %dus\n", val
, cnt
);
239 hc
->hw
.fifo_en
= 0x30; /* only D fifos enabled */
241 hc
->hw
.bswapped
= 0; /* no exchange */
242 hc
->hw
.ctmt
= HFCPCI_TIM3_125
| HFCPCI_AUTO_TIMER
;
243 hc
->hw
.trm
= HFCPCI_BTRANS_THRESMASK
; /* no echo connect , threshold */
244 hc
->hw
.sctrl
= 0x40; /* set tx_lo mode, error in datasheet ! */
246 hc
->hw
.sctrl_e
= HFCPCI_AUTO_AWAKE
; /* S/T Auto awake */
248 if (test_bit(HFC_CFG_MASTER
, &hc
->cfg
))
249 hc
->hw
.mst_m
|= HFCPCI_MASTER
; /* HFC Master Mode */
250 if (test_bit(HFC_CFG_NEG_F0
, &hc
->cfg
))
251 hc
->hw
.mst_m
|= HFCPCI_F0_NEGATIV
;
252 Write_hfc(hc
, HFCPCI_FIFO_EN
, hc
->hw
.fifo_en
);
253 Write_hfc(hc
, HFCPCI_TRM
, hc
->hw
.trm
);
254 Write_hfc(hc
, HFCPCI_SCTRL_E
, hc
->hw
.sctrl_e
);
255 Write_hfc(hc
, HFCPCI_CTMT
, hc
->hw
.ctmt
);
257 hc
->hw
.int_m1
= HFCPCI_INTS_DTRANS
| HFCPCI_INTS_DREC
|
258 HFCPCI_INTS_L1STATE
| HFCPCI_INTS_TIMER
;
259 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
261 /* Clear already pending ints */
262 val
= Read_hfc(hc
, HFCPCI_INT_S1
);
267 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
268 Write_hfc(hc
, HFCPCI_SCTRL_R
, hc
->hw
.sctrl_r
);
271 * Init GCI/IOM2 in master mode
272 * Slots 0 and 1 are set for B-chan 1 and 2
273 * D- and monitor/CI channel are not enabled
274 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
275 * STIO2 is used as data input, B1+B2 from IOM->ST
276 * ST B-channel send disabled -> continuous 1s
277 * The IOM slots are always enabled
279 if (test_bit(HFC_CFG_PCM
, &hc
->cfg
)) {
280 /* set data flow directions: connect B1,B2: HFC to/from PCM */
283 hc
->hw
.conn
= 0x36; /* set data flow directions */
284 if (test_bit(HFC_CFG_SW_DD_DU
, &hc
->cfg
)) {
285 Write_hfc(hc
, HFCPCI_B1_SSL
, 0xC0);
286 Write_hfc(hc
, HFCPCI_B2_SSL
, 0xC1);
287 Write_hfc(hc
, HFCPCI_B1_RSL
, 0xC0);
288 Write_hfc(hc
, HFCPCI_B2_RSL
, 0xC1);
290 Write_hfc(hc
, HFCPCI_B1_SSL
, 0x80);
291 Write_hfc(hc
, HFCPCI_B2_SSL
, 0x81);
292 Write_hfc(hc
, HFCPCI_B1_RSL
, 0x80);
293 Write_hfc(hc
, HFCPCI_B2_RSL
, 0x81);
296 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
297 val
= Read_hfc(hc
, HFCPCI_INT_S2
);
301 * Timer function called when kernel timer expires
304 hfcpci_Timer(struct hfc_pci
*hc
)
306 hc
->hw
.timer
.expires
= jiffies
+ 75;
309 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
310 * add_timer(&hc->hw.timer);
316 * select a b-channel entry matching and active
318 static struct bchannel
*
319 Sel_BCS(struct hfc_pci
*hc
, int channel
)
321 if (test_bit(FLG_ACTIVE
, &hc
->bch
[0].Flags
) &&
322 (hc
->bch
[0].nr
& channel
))
324 else if (test_bit(FLG_ACTIVE
, &hc
->bch
[1].Flags
) &&
325 (hc
->bch
[1].nr
& channel
))
332 * clear the desired B-channel rx fifo
335 hfcpci_clear_fifo_rx(struct hfc_pci
*hc
, int fifo
)
341 bzr
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.rxbz_b2
;
342 fifo_state
= hc
->hw
.fifo_en
& HFCPCI_FIFOEN_B2RX
;
344 bzr
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.rxbz_b1
;
345 fifo_state
= hc
->hw
.fifo_en
& HFCPCI_FIFOEN_B1RX
;
348 hc
->hw
.fifo_en
^= fifo_state
;
349 Write_hfc(hc
, HFCPCI_FIFO_EN
, hc
->hw
.fifo_en
);
350 hc
->hw
.last_bfifo_cnt
[fifo
] = 0;
351 bzr
->f1
= MAX_B_FRAMES
;
352 bzr
->f2
= bzr
->f1
; /* init F pointers to remain constant */
353 bzr
->za
[MAX_B_FRAMES
].z1
= cpu_to_le16(B_FIFO_SIZE
+ B_SUB_VAL
- 1);
354 bzr
->za
[MAX_B_FRAMES
].z2
= cpu_to_le16(
355 le16_to_cpu(bzr
->za
[MAX_B_FRAMES
].z1
));
357 hc
->hw
.fifo_en
|= fifo_state
;
358 Write_hfc(hc
, HFCPCI_FIFO_EN
, hc
->hw
.fifo_en
);
362 * clear the desired B-channel tx fifo
364 static void hfcpci_clear_fifo_tx(struct hfc_pci
*hc
, int fifo
)
370 bzt
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txbz_b2
;
371 fifo_state
= hc
->hw
.fifo_en
& HFCPCI_FIFOEN_B2TX
;
373 bzt
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txbz_b1
;
374 fifo_state
= hc
->hw
.fifo_en
& HFCPCI_FIFOEN_B1TX
;
377 hc
->hw
.fifo_en
^= fifo_state
;
378 Write_hfc(hc
, HFCPCI_FIFO_EN
, hc
->hw
.fifo_en
);
379 if (hc
->bch
[fifo
].debug
& DEBUG_HW_BCHANNEL
)
380 printk(KERN_DEBUG
"hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
381 "z1(%x) z2(%x) state(%x)\n",
382 fifo
, bzt
->f1
, bzt
->f2
,
383 le16_to_cpu(bzt
->za
[MAX_B_FRAMES
].z1
),
384 le16_to_cpu(bzt
->za
[MAX_B_FRAMES
].z2
),
386 bzt
->f2
= MAX_B_FRAMES
;
387 bzt
->f1
= bzt
->f2
; /* init F pointers to remain constant */
388 bzt
->za
[MAX_B_FRAMES
].z1
= cpu_to_le16(B_FIFO_SIZE
+ B_SUB_VAL
- 1);
389 bzt
->za
[MAX_B_FRAMES
].z2
= cpu_to_le16(B_FIFO_SIZE
+ B_SUB_VAL
- 2);
391 hc
->hw
.fifo_en
|= fifo_state
;
392 Write_hfc(hc
, HFCPCI_FIFO_EN
, hc
->hw
.fifo_en
);
393 if (hc
->bch
[fifo
].debug
& DEBUG_HW_BCHANNEL
)
395 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
396 fifo
, bzt
->f1
, bzt
->f2
,
397 le16_to_cpu(bzt
->za
[MAX_B_FRAMES
].z1
),
398 le16_to_cpu(bzt
->za
[MAX_B_FRAMES
].z2
));
402 * read a complete B-frame out of the buffer
405 hfcpci_empty_bfifo(struct bchannel
*bch
, struct bzfifo
*bz
,
406 u_char
*bdata
, int count
)
408 u_char
*ptr
, *ptr1
, new_f2
;
412 if ((bch
->debug
& DEBUG_HW_BCHANNEL
) && !(bch
->debug
& DEBUG_HW_BFIFO
))
413 printk(KERN_DEBUG
"hfcpci_empty_fifo\n");
414 zp
= &bz
->za
[bz
->f2
]; /* point to Z-Regs */
415 new_z2
= le16_to_cpu(zp
->z2
) + count
; /* new position in fifo */
416 if (new_z2
>= (B_FIFO_SIZE
+ B_SUB_VAL
))
417 new_z2
-= B_FIFO_SIZE
; /* buffer wrap */
418 new_f2
= (bz
->f2
+ 1) & MAX_B_FRAMES
;
419 if ((count
> MAX_DATA_SIZE
+ 3) || (count
< 4) ||
420 (*(bdata
+ (le16_to_cpu(zp
->z1
) - B_SUB_VAL
)))) {
421 if (bch
->debug
& DEBUG_HW
)
422 printk(KERN_DEBUG
"hfcpci_empty_fifo: incoming packet "
423 "invalid length %d or crc\n", count
);
424 #ifdef ERROR_STATISTIC
427 bz
->za
[new_f2
].z2
= cpu_to_le16(new_z2
);
428 bz
->f2
= new_f2
; /* next buffer */
430 bch
->rx_skb
= mI_alloc_skb(count
- 3, GFP_ATOMIC
);
432 printk(KERN_WARNING
"HFCPCI: receive out of memory\n");
436 ptr
= skb_put(bch
->rx_skb
, count
);
438 if (le16_to_cpu(zp
->z2
) + count
<= B_FIFO_SIZE
+ B_SUB_VAL
)
439 maxlen
= count
; /* complete transfer */
441 maxlen
= B_FIFO_SIZE
+ B_SUB_VAL
-
442 le16_to_cpu(zp
->z2
); /* maximum */
444 ptr1
= bdata
+ (le16_to_cpu(zp
->z2
) - B_SUB_VAL
);
446 memcpy(ptr
, ptr1
, maxlen
); /* copy data */
449 if (count
) { /* rest remaining */
451 ptr1
= bdata
; /* start of buffer */
452 memcpy(ptr
, ptr1
, count
); /* rest */
454 bz
->za
[new_f2
].z2
= cpu_to_le16(new_z2
);
455 bz
->f2
= new_f2
; /* next buffer */
456 recv_Bchannel(bch
, MISDN_ID_ANY
, false);
461 * D-channel receive procedure
464 receive_dmsg(struct hfc_pci
*hc
)
466 struct dchannel
*dch
= &hc
->dch
;
474 df
= &((union fifo_area
*)(hc
->hw
.fifos
))->d_chan
.d_rx
;
475 while (((df
->f1
& D_FREG_MASK
) != (df
->f2
& D_FREG_MASK
)) && count
--) {
476 zp
= &df
->za
[df
->f2
& D_FREG_MASK
];
477 rcnt
= le16_to_cpu(zp
->z1
) - le16_to_cpu(zp
->z2
);
481 if (dch
->debug
& DEBUG_HW_DCHANNEL
)
483 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
489 if ((rcnt
> MAX_DFRAME_LEN
+ 3) || (rcnt
< 4) ||
490 (df
->data
[le16_to_cpu(zp
->z1
)])) {
491 if (dch
->debug
& DEBUG_HW
)
493 "empty_fifo hfcpci packet inv. len "
496 df
->data
[le16_to_cpu(zp
->z1
)]);
497 #ifdef ERROR_STATISTIC
500 df
->f2
= ((df
->f2
+ 1) & MAX_D_FRAMES
) |
501 (MAX_D_FRAMES
+ 1); /* next buffer */
502 df
->za
[df
->f2
& D_FREG_MASK
].z2
=
503 cpu_to_le16((le16_to_cpu(zp
->z2
) + rcnt
) &
506 dch
->rx_skb
= mI_alloc_skb(rcnt
- 3, GFP_ATOMIC
);
509 "HFC-PCI: D receive out of memory\n");
514 ptr
= skb_put(dch
->rx_skb
, rcnt
);
516 if (le16_to_cpu(zp
->z2
) + rcnt
<= D_FIFO_SIZE
)
517 maxlen
= rcnt
; /* complete transfer */
519 maxlen
= D_FIFO_SIZE
- le16_to_cpu(zp
->z2
);
522 ptr1
= df
->data
+ le16_to_cpu(zp
->z2
);
524 memcpy(ptr
, ptr1
, maxlen
); /* copy data */
527 if (rcnt
) { /* rest remaining */
529 ptr1
= df
->data
; /* start of buffer */
530 memcpy(ptr
, ptr1
, rcnt
); /* rest */
532 df
->f2
= ((df
->f2
+ 1) & MAX_D_FRAMES
) |
533 (MAX_D_FRAMES
+ 1); /* next buffer */
534 df
->za
[df
->f2
& D_FREG_MASK
].z2
= cpu_to_le16((
535 le16_to_cpu(zp
->z2
) + total
) & (D_FIFO_SIZE
- 1));
543 * check for transparent receive data and read max one 'poll' size if avail
546 hfcpci_empty_fifo_trans(struct bchannel
*bch
, struct bzfifo
*rxbz
,
547 struct bzfifo
*txbz
, u_char
*bdata
)
549 __le16
*z1r
, *z2r
, *z1t
, *z2t
;
550 int new_z2
, fcnt_rx
, fcnt_tx
, maxlen
;
553 z1r
= &rxbz
->za
[MAX_B_FRAMES
].z1
; /* pointer to z reg */
555 z1t
= &txbz
->za
[MAX_B_FRAMES
].z1
;
558 fcnt_rx
= le16_to_cpu(*z1r
) - le16_to_cpu(*z2r
);
560 return; /* no data avail */
563 fcnt_rx
+= B_FIFO_SIZE
; /* bytes actually buffered */
564 new_z2
= le16_to_cpu(*z2r
) + fcnt_rx
; /* new position in fifo */
565 if (new_z2
>= (B_FIFO_SIZE
+ B_SUB_VAL
))
566 new_z2
-= B_FIFO_SIZE
; /* buffer wrap */
568 fcnt_tx
= le16_to_cpu(*z2t
) - le16_to_cpu(*z1t
);
570 fcnt_tx
+= B_FIFO_SIZE
;
571 /* fcnt_tx contains available bytes in tx-fifo */
572 fcnt_tx
= B_FIFO_SIZE
- fcnt_tx
;
573 /* remaining bytes to send (bytes in tx-fifo) */
575 if (test_bit(FLG_RX_OFF
, &bch
->Flags
)) {
576 bch
->dropcnt
+= fcnt_rx
;
577 *z2r
= cpu_to_le16(new_z2
);
580 maxlen
= bchannel_get_rxbuf(bch
, fcnt_rx
);
582 pr_warning("B%d: No bufferspace for %d bytes\n",
585 ptr
= skb_put(bch
->rx_skb
, fcnt_rx
);
586 if (le16_to_cpu(*z2r
) + fcnt_rx
<= B_FIFO_SIZE
+ B_SUB_VAL
)
587 maxlen
= fcnt_rx
; /* complete transfer */
589 maxlen
= B_FIFO_SIZE
+ B_SUB_VAL
- le16_to_cpu(*z2r
);
592 ptr1
= bdata
+ (le16_to_cpu(*z2r
) - B_SUB_VAL
);
594 memcpy(ptr
, ptr1
, maxlen
); /* copy data */
597 if (fcnt_rx
) { /* rest remaining */
599 ptr1
= bdata
; /* start of buffer */
600 memcpy(ptr
, ptr1
, fcnt_rx
); /* rest */
602 recv_Bchannel(bch
, fcnt_tx
, false); /* bch, id, !force */
604 *z2r
= cpu_to_le16(new_z2
); /* new position */
608 * B-channel main receive routine
611 main_rec_hfcpci(struct bchannel
*bch
)
613 struct hfc_pci
*hc
= bch
->hw
;
615 int receive
= 0, count
= 5;
616 struct bzfifo
*txbz
, *rxbz
;
620 if ((bch
->nr
& 2) && (!hc
->hw
.bswapped
)) {
621 rxbz
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.rxbz_b2
;
622 txbz
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txbz_b2
;
623 bdata
= ((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.rxdat_b2
;
626 rxbz
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.rxbz_b1
;
627 txbz
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txbz_b1
;
628 bdata
= ((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.rxdat_b1
;
633 if (rxbz
->f1
!= rxbz
->f2
) {
634 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
635 printk(KERN_DEBUG
"hfcpci rec ch(%x) f1(%d) f2(%d)\n",
636 bch
->nr
, rxbz
->f1
, rxbz
->f2
);
637 zp
= &rxbz
->za
[rxbz
->f2
];
639 rcnt
= le16_to_cpu(zp
->z1
) - le16_to_cpu(zp
->z2
);
643 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
645 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
646 bch
->nr
, le16_to_cpu(zp
->z1
),
647 le16_to_cpu(zp
->z2
), rcnt
);
648 hfcpci_empty_bfifo(bch
, rxbz
, bdata
, rcnt
);
649 rcnt
= rxbz
->f1
- rxbz
->f2
;
651 rcnt
+= MAX_B_FRAMES
+ 1;
652 if (hc
->hw
.last_bfifo_cnt
[real_fifo
] > rcnt
+ 1) {
654 hfcpci_clear_fifo_rx(hc
, real_fifo
);
656 hc
->hw
.last_bfifo_cnt
[real_fifo
] = rcnt
;
661 } else if (test_bit(FLG_TRANSPARENT
, &bch
->Flags
)) {
662 hfcpci_empty_fifo_trans(bch
, rxbz
, txbz
, bdata
);
666 if (count
&& receive
)
672 * D-channel send routine
675 hfcpci_fill_dfifo(struct hfc_pci
*hc
)
677 struct dchannel
*dch
= &hc
->dch
;
679 int count
, new_z1
, maxlen
;
681 u_char
*src
, *dst
, new_f1
;
683 if ((dch
->debug
& DEBUG_HW_DCHANNEL
) && !(dch
->debug
& DEBUG_HW_DFIFO
))
684 printk(KERN_DEBUG
"%s\n", __func__
);
688 count
= dch
->tx_skb
->len
- dch
->tx_idx
;
691 df
= &((union fifo_area
*) (hc
->hw
.fifos
))->d_chan
.d_tx
;
693 if (dch
->debug
& DEBUG_HW_DFIFO
)
694 printk(KERN_DEBUG
"%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__
,
696 le16_to_cpu(df
->za
[df
->f1
& D_FREG_MASK
].z1
));
697 fcnt
= df
->f1
- df
->f2
; /* frame count actually buffered */
699 fcnt
+= (MAX_D_FRAMES
+ 1); /* if wrap around */
700 if (fcnt
> (MAX_D_FRAMES
- 1)) {
701 if (dch
->debug
& DEBUG_HW_DCHANNEL
)
703 "hfcpci_fill_Dfifo more as 14 frames\n");
704 #ifdef ERROR_STATISTIC
709 /* now determine free bytes in FIFO buffer */
710 maxlen
= le16_to_cpu(df
->za
[df
->f2
& D_FREG_MASK
].z2
) -
711 le16_to_cpu(df
->za
[df
->f1
& D_FREG_MASK
].z1
) - 1;
713 maxlen
+= D_FIFO_SIZE
; /* count now contains available bytes */
715 if (dch
->debug
& DEBUG_HW_DCHANNEL
)
716 printk(KERN_DEBUG
"hfcpci_fill_Dfifo count(%d/%d)\n",
718 if (count
> maxlen
) {
719 if (dch
->debug
& DEBUG_HW_DCHANNEL
)
720 printk(KERN_DEBUG
"hfcpci_fill_Dfifo no fifo mem\n");
723 new_z1
= (le16_to_cpu(df
->za
[df
->f1
& D_FREG_MASK
].z1
) + count
) &
725 new_f1
= ((df
->f1
+ 1) & D_FREG_MASK
) | (D_FREG_MASK
+ 1);
726 src
= dch
->tx_skb
->data
+ dch
->tx_idx
; /* source pointer */
727 dst
= df
->data
+ le16_to_cpu(df
->za
[df
->f1
& D_FREG_MASK
].z1
);
728 maxlen
= D_FIFO_SIZE
- le16_to_cpu(df
->za
[df
->f1
& D_FREG_MASK
].z1
);
731 maxlen
= count
; /* limit size */
732 memcpy(dst
, src
, maxlen
); /* first copy */
734 count
-= maxlen
; /* remaining bytes */
736 dst
= df
->data
; /* start of buffer */
737 src
+= maxlen
; /* new position */
738 memcpy(dst
, src
, count
);
740 df
->za
[new_f1
& D_FREG_MASK
].z1
= cpu_to_le16(new_z1
);
741 /* for next buffer */
742 df
->za
[df
->f1
& D_FREG_MASK
].z1
= cpu_to_le16(new_z1
);
743 /* new pos actual buffer */
744 df
->f1
= new_f1
; /* next frame */
745 dch
->tx_idx
= dch
->tx_skb
->len
;
749 * B-channel send routine
752 hfcpci_fill_fifo(struct bchannel
*bch
)
754 struct hfc_pci
*hc
= bch
->hw
;
759 u_char new_f1
, *src
, *dst
;
762 if ((bch
->debug
& DEBUG_HW_BCHANNEL
) && !(bch
->debug
& DEBUG_HW_BFIFO
))
763 printk(KERN_DEBUG
"%s\n", __func__
);
764 if ((!bch
->tx_skb
) || bch
->tx_skb
->len
== 0) {
765 if (!test_bit(FLG_FILLEMPTY
, &bch
->Flags
) &&
766 !test_bit(FLG_TRANSPARENT
, &bch
->Flags
))
768 count
= HFCPCI_FILLEMPTY
;
770 count
= bch
->tx_skb
->len
- bch
->tx_idx
;
772 if ((bch
->nr
& 2) && (!hc
->hw
.bswapped
)) {
773 bz
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txbz_b2
;
774 bdata
= ((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txdat_b2
;
776 bz
= &((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txbz_b1
;
777 bdata
= ((union fifo_area
*)(hc
->hw
.fifos
))->b_chans
.txdat_b1
;
780 if (test_bit(FLG_TRANSPARENT
, &bch
->Flags
)) {
781 z1t
= &bz
->za
[MAX_B_FRAMES
].z1
;
783 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
784 printk(KERN_DEBUG
"hfcpci_fill_fifo_trans ch(%x) "
785 "cnt(%d) z1(%x) z2(%x)\n", bch
->nr
, count
,
786 le16_to_cpu(*z1t
), le16_to_cpu(*z2t
));
787 fcnt
= le16_to_cpu(*z2t
) - le16_to_cpu(*z1t
);
790 if (test_bit(FLG_FILLEMPTY
, &bch
->Flags
)) {
791 /* fcnt contains available bytes in fifo */
794 new_z1
= le16_to_cpu(*z1t
) + count
;
795 /* new buffer Position */
796 if (new_z1
>= (B_FIFO_SIZE
+ B_SUB_VAL
))
797 new_z1
-= B_FIFO_SIZE
; /* buffer wrap */
798 dst
= bdata
+ (le16_to_cpu(*z1t
) - B_SUB_VAL
);
799 maxlen
= (B_FIFO_SIZE
+ B_SUB_VAL
) - le16_to_cpu(*z1t
);
801 if (bch
->debug
& DEBUG_HW_BFIFO
)
802 printk(KERN_DEBUG
"hfcpci_FFt fillempty "
803 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
804 fcnt
, maxlen
, new_z1
, dst
);
806 maxlen
= count
; /* limit size */
807 memset(dst
, bch
->fill
[0], maxlen
); /* first copy */
808 count
-= maxlen
; /* remaining bytes */
810 dst
= bdata
; /* start of buffer */
811 memset(dst
, bch
->fill
[0], count
);
813 *z1t
= cpu_to_le16(new_z1
); /* now send data */
816 /* fcnt contains available bytes in fifo */
817 fcnt
= B_FIFO_SIZE
- fcnt
;
818 /* remaining bytes to send (bytes in fifo) */
821 count
= bch
->tx_skb
->len
- bch
->tx_idx
;
822 /* maximum fill shall be poll*2 */
823 if (count
> (poll
<< 1) - fcnt
)
824 count
= (poll
<< 1) - fcnt
;
827 /* data is suitable for fifo */
828 new_z1
= le16_to_cpu(*z1t
) + count
;
829 /* new buffer Position */
830 if (new_z1
>= (B_FIFO_SIZE
+ B_SUB_VAL
))
831 new_z1
-= B_FIFO_SIZE
; /* buffer wrap */
832 src
= bch
->tx_skb
->data
+ bch
->tx_idx
;
834 dst
= bdata
+ (le16_to_cpu(*z1t
) - B_SUB_VAL
);
835 maxlen
= (B_FIFO_SIZE
+ B_SUB_VAL
) - le16_to_cpu(*z1t
);
837 if (bch
->debug
& DEBUG_HW_BFIFO
)
838 printk(KERN_DEBUG
"hfcpci_FFt fcnt(%d) "
839 "maxl(%d) nz1(%x) dst(%p)\n",
840 fcnt
, maxlen
, new_z1
, dst
);
842 bch
->tx_idx
+= count
;
844 maxlen
= count
; /* limit size */
845 memcpy(dst
, src
, maxlen
); /* first copy */
846 count
-= maxlen
; /* remaining bytes */
848 dst
= bdata
; /* start of buffer */
849 src
+= maxlen
; /* new position */
850 memcpy(dst
, src
, count
);
852 *z1t
= cpu_to_le16(new_z1
); /* now send data */
853 if (bch
->tx_idx
< bch
->tx_skb
->len
)
855 dev_kfree_skb(bch
->tx_skb
);
856 if (get_next_bframe(bch
))
860 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
862 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
863 __func__
, bch
->nr
, bz
->f1
, bz
->f2
,
865 fcnt
= bz
->f1
- bz
->f2
; /* frame count actually buffered */
867 fcnt
+= (MAX_B_FRAMES
+ 1); /* if wrap around */
868 if (fcnt
> (MAX_B_FRAMES
- 1)) {
869 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
871 "hfcpci_fill_Bfifo more as 14 frames\n");
874 /* now determine free bytes in FIFO buffer */
875 maxlen
= le16_to_cpu(bz
->za
[bz
->f2
].z2
) -
876 le16_to_cpu(bz
->za
[bz
->f1
].z1
) - 1;
878 maxlen
+= B_FIFO_SIZE
; /* count now contains available bytes */
880 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
881 printk(KERN_DEBUG
"hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
882 bch
->nr
, count
, maxlen
);
884 if (maxlen
< count
) {
885 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
886 printk(KERN_DEBUG
"hfcpci_fill_fifo no fifo mem\n");
889 new_z1
= le16_to_cpu(bz
->za
[bz
->f1
].z1
) + count
;
890 /* new buffer Position */
891 if (new_z1
>= (B_FIFO_SIZE
+ B_SUB_VAL
))
892 new_z1
-= B_FIFO_SIZE
; /* buffer wrap */
894 new_f1
= ((bz
->f1
+ 1) & MAX_B_FRAMES
);
895 src
= bch
->tx_skb
->data
+ bch
->tx_idx
; /* source pointer */
896 dst
= bdata
+ (le16_to_cpu(bz
->za
[bz
->f1
].z1
) - B_SUB_VAL
);
897 maxlen
= (B_FIFO_SIZE
+ B_SUB_VAL
) - le16_to_cpu(bz
->za
[bz
->f1
].z1
);
900 maxlen
= count
; /* limit size */
901 memcpy(dst
, src
, maxlen
); /* first copy */
903 count
-= maxlen
; /* remaining bytes */
905 dst
= bdata
; /* start of buffer */
906 src
+= maxlen
; /* new position */
907 memcpy(dst
, src
, count
);
909 bz
->za
[new_f1
].z1
= cpu_to_le16(new_z1
); /* for next buffer */
910 bz
->f1
= new_f1
; /* next frame */
911 dev_kfree_skb(bch
->tx_skb
);
912 get_next_bframe(bch
);
918 * handle L1 state changes TE
922 ph_state_te(struct dchannel
*dch
)
925 printk(KERN_DEBUG
"%s: TE newstate %x\n",
926 __func__
, dch
->state
);
927 switch (dch
->state
) {
929 l1_event(dch
->l1
, HW_RESET_IND
);
932 l1_event(dch
->l1
, HW_DEACT_IND
);
936 l1_event(dch
->l1
, ANYSIGNAL
);
939 l1_event(dch
->l1
, INFO2
);
942 l1_event(dch
->l1
, INFO4_P8
);
948 * handle L1 state changes NT
952 handle_nt_timer3(struct dchannel
*dch
) {
953 struct hfc_pci
*hc
= dch
->hw
;
955 test_and_clear_bit(FLG_HFC_TIMER_T3
, &dch
->Flags
);
956 hc
->hw
.int_m1
&= ~HFCPCI_INTS_TIMER
;
957 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
959 test_and_set_bit(FLG_ACTIVE
, &dch
->Flags
);
960 if (test_bit(HFC_CFG_MASTER
, &hc
->cfg
))
961 hc
->hw
.mst_m
|= HFCPCI_MASTER
;
962 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
963 _queue_data(&dch
->dev
.D
, PH_ACTIVATE_IND
,
964 MISDN_ID_ANY
, 0, NULL
, GFP_ATOMIC
);
968 ph_state_nt(struct dchannel
*dch
)
970 struct hfc_pci
*hc
= dch
->hw
;
973 printk(KERN_DEBUG
"%s: NT newstate %x\n",
974 __func__
, dch
->state
);
975 switch (dch
->state
) {
977 if (hc
->hw
.nt_timer
< 0) {
979 test_and_clear_bit(FLG_HFC_TIMER_T3
, &dch
->Flags
);
980 test_and_clear_bit(FLG_HFC_TIMER_T1
, &dch
->Flags
);
981 hc
->hw
.int_m1
&= ~HFCPCI_INTS_TIMER
;
982 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
983 /* Clear already pending ints */
984 (void) Read_hfc(hc
, HFCPCI_INT_S1
);
985 Write_hfc(hc
, HFCPCI_STATES
, 4 | HFCPCI_LOAD_STATE
);
987 Write_hfc(hc
, HFCPCI_STATES
, 4);
989 } else if (hc
->hw
.nt_timer
== 0) {
990 hc
->hw
.int_m1
|= HFCPCI_INTS_TIMER
;
991 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
992 hc
->hw
.nt_timer
= NT_T1_COUNT
;
993 hc
->hw
.ctmt
&= ~HFCPCI_AUTO_TIMER
;
994 hc
->hw
.ctmt
|= HFCPCI_TIM3_125
;
995 Write_hfc(hc
, HFCPCI_CTMT
, hc
->hw
.ctmt
|
997 test_and_clear_bit(FLG_HFC_TIMER_T3
, &dch
->Flags
);
998 test_and_set_bit(FLG_HFC_TIMER_T1
, &dch
->Flags
);
999 /* allow G2 -> G3 transition */
1000 Write_hfc(hc
, HFCPCI_STATES
, 2 | HFCPCI_NT_G2_G3
);
1002 Write_hfc(hc
, HFCPCI_STATES
, 2 | HFCPCI_NT_G2_G3
);
1006 hc
->hw
.nt_timer
= 0;
1007 test_and_clear_bit(FLG_HFC_TIMER_T3
, &dch
->Flags
);
1008 test_and_clear_bit(FLG_HFC_TIMER_T1
, &dch
->Flags
);
1009 hc
->hw
.int_m1
&= ~HFCPCI_INTS_TIMER
;
1010 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
1011 test_and_clear_bit(FLG_ACTIVE
, &dch
->Flags
);
1012 hc
->hw
.mst_m
&= ~HFCPCI_MASTER
;
1013 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
1014 test_and_clear_bit(FLG_L2_ACTIVATED
, &dch
->Flags
);
1015 _queue_data(&dch
->dev
.D
, PH_DEACTIVATE_IND
,
1016 MISDN_ID_ANY
, 0, NULL
, GFP_ATOMIC
);
1019 hc
->hw
.nt_timer
= 0;
1020 test_and_clear_bit(FLG_HFC_TIMER_T3
, &dch
->Flags
);
1021 test_and_clear_bit(FLG_HFC_TIMER_T1
, &dch
->Flags
);
1022 hc
->hw
.int_m1
&= ~HFCPCI_INTS_TIMER
;
1023 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
1026 if (!test_and_set_bit(FLG_HFC_TIMER_T3
, &dch
->Flags
)) {
1027 if (!test_and_clear_bit(FLG_L2_ACTIVATED
,
1029 handle_nt_timer3(dch
);
1032 test_and_clear_bit(FLG_HFC_TIMER_T1
, &dch
->Flags
);
1033 hc
->hw
.int_m1
|= HFCPCI_INTS_TIMER
;
1034 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
1035 hc
->hw
.nt_timer
= NT_T3_COUNT
;
1036 hc
->hw
.ctmt
&= ~HFCPCI_AUTO_TIMER
;
1037 hc
->hw
.ctmt
|= HFCPCI_TIM3_125
;
1038 Write_hfc(hc
, HFCPCI_CTMT
, hc
->hw
.ctmt
|
1046 ph_state(struct dchannel
*dch
)
1048 struct hfc_pci
*hc
= dch
->hw
;
1050 if (hc
->hw
.protocol
== ISDN_P_NT_S0
) {
1051 if (test_bit(FLG_HFC_TIMER_T3
, &dch
->Flags
) &&
1052 hc
->hw
.nt_timer
< 0)
1053 handle_nt_timer3(dch
);
1061 * Layer 1 callback function
1064 hfc_l1callback(struct dchannel
*dch
, u_int cmd
)
1066 struct hfc_pci
*hc
= dch
->hw
;
1071 if (test_bit(HFC_CFG_MASTER
, &hc
->cfg
))
1072 hc
->hw
.mst_m
|= HFCPCI_MASTER
;
1073 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
1076 Write_hfc(hc
, HFCPCI_STATES
, HFCPCI_LOAD_STATE
| 3);
1079 Write_hfc(hc
, HFCPCI_STATES
, 3); /* HFC ST 2 */
1080 if (test_bit(HFC_CFG_MASTER
, &hc
->cfg
))
1081 hc
->hw
.mst_m
|= HFCPCI_MASTER
;
1082 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
1083 Write_hfc(hc
, HFCPCI_STATES
, HFCPCI_ACTIVATE
|
1085 l1_event(dch
->l1
, HW_POWERUP_IND
);
1088 hc
->hw
.mst_m
&= ~HFCPCI_MASTER
;
1089 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
1090 skb_queue_purge(&dch
->squeue
);
1092 dev_kfree_skb(dch
->tx_skb
);
1097 dev_kfree_skb(dch
->rx_skb
);
1100 test_and_clear_bit(FLG_TX_BUSY
, &dch
->Flags
);
1101 if (test_and_clear_bit(FLG_BUSY_TIMER
, &dch
->Flags
))
1102 del_timer(&dch
->timer
);
1104 case HW_POWERUP_REQ
:
1105 Write_hfc(hc
, HFCPCI_STATES
, HFCPCI_DO_ACTION
);
1107 case PH_ACTIVATE_IND
:
1108 test_and_set_bit(FLG_ACTIVE
, &dch
->Flags
);
1109 _queue_data(&dch
->dev
.D
, cmd
, MISDN_ID_ANY
, 0, NULL
,
1112 case PH_DEACTIVATE_IND
:
1113 test_and_clear_bit(FLG_ACTIVE
, &dch
->Flags
);
1114 _queue_data(&dch
->dev
.D
, cmd
, MISDN_ID_ANY
, 0, NULL
,
1118 if (dch
->debug
& DEBUG_HW
)
1119 printk(KERN_DEBUG
"%s: unknown command %x\n",
1130 tx_birq(struct bchannel
*bch
)
1132 if (bch
->tx_skb
&& bch
->tx_idx
< bch
->tx_skb
->len
)
1133 hfcpci_fill_fifo(bch
);
1136 dev_kfree_skb(bch
->tx_skb
);
1137 if (get_next_bframe(bch
))
1138 hfcpci_fill_fifo(bch
);
1143 tx_dirq(struct dchannel
*dch
)
1145 if (dch
->tx_skb
&& dch
->tx_idx
< dch
->tx_skb
->len
)
1146 hfcpci_fill_dfifo(dch
->hw
);
1149 dev_kfree_skb(dch
->tx_skb
);
1150 if (get_next_dframe(dch
))
1151 hfcpci_fill_dfifo(dch
->hw
);
1156 hfcpci_int(int intno
, void *dev_id
)
1158 struct hfc_pci
*hc
= dev_id
;
1160 struct bchannel
*bch
;
1163 spin_lock(&hc
->lock
);
1164 if (!(hc
->hw
.int_m2
& 0x08)) {
1165 spin_unlock(&hc
->lock
);
1166 return IRQ_NONE
; /* not initialised */
1168 stat
= Read_hfc(hc
, HFCPCI_STATUS
);
1169 if (HFCPCI_ANYINT
& stat
) {
1170 val
= Read_hfc(hc
, HFCPCI_INT_S1
);
1171 if (hc
->dch
.debug
& DEBUG_HW_DCHANNEL
)
1173 "HFC-PCI: stat(%02x) s1(%02x)\n", stat
, val
);
1176 spin_unlock(&hc
->lock
);
1181 if (hc
->dch
.debug
& DEBUG_HW_DCHANNEL
)
1182 printk(KERN_DEBUG
"HFC-PCI irq %x\n", val
);
1183 val
&= hc
->hw
.int_m1
;
1184 if (val
& 0x40) { /* state machine irq */
1185 exval
= Read_hfc(hc
, HFCPCI_STATES
) & 0xf;
1186 if (hc
->dch
.debug
& DEBUG_HW_DCHANNEL
)
1187 printk(KERN_DEBUG
"ph_state chg %d->%d\n",
1188 hc
->dch
.state
, exval
);
1189 hc
->dch
.state
= exval
;
1190 schedule_event(&hc
->dch
, FLG_PHCHANGE
);
1193 if (val
& 0x80) { /* timer irq */
1194 if (hc
->hw
.protocol
== ISDN_P_NT_S0
) {
1195 if ((--hc
->hw
.nt_timer
) < 0)
1196 schedule_event(&hc
->dch
, FLG_PHCHANGE
);
1199 Write_hfc(hc
, HFCPCI_CTMT
, hc
->hw
.ctmt
| HFCPCI_CLTIMER
);
1201 if (val
& 0x08) { /* B1 rx */
1202 bch
= Sel_BCS(hc
, hc
->hw
.bswapped
? 2 : 1);
1204 main_rec_hfcpci(bch
);
1205 else if (hc
->dch
.debug
)
1206 printk(KERN_DEBUG
"hfcpci spurious 0x08 IRQ\n");
1208 if (val
& 0x10) { /* B2 rx */
1209 bch
= Sel_BCS(hc
, 2);
1211 main_rec_hfcpci(bch
);
1212 else if (hc
->dch
.debug
)
1213 printk(KERN_DEBUG
"hfcpci spurious 0x10 IRQ\n");
1215 if (val
& 0x01) { /* B1 tx */
1216 bch
= Sel_BCS(hc
, hc
->hw
.bswapped
? 2 : 1);
1219 else if (hc
->dch
.debug
)
1220 printk(KERN_DEBUG
"hfcpci spurious 0x01 IRQ\n");
1222 if (val
& 0x02) { /* B2 tx */
1223 bch
= Sel_BCS(hc
, 2);
1226 else if (hc
->dch
.debug
)
1227 printk(KERN_DEBUG
"hfcpci spurious 0x02 IRQ\n");
1229 if (val
& 0x20) /* D rx */
1231 if (val
& 0x04) { /* D tx */
1232 if (test_and_clear_bit(FLG_BUSY_TIMER
, &hc
->dch
.Flags
))
1233 del_timer(&hc
->dch
.timer
);
1236 spin_unlock(&hc
->lock
);
1241 * timer callback for D-chan busy resolution. Currently no function
1244 hfcpci_dbusy_timer(struct hfc_pci
*hc
)
1249 * activate/deactivate hardware for selected channels and mode
1252 mode_hfcpci(struct bchannel
*bch
, int bc
, int protocol
)
1254 struct hfc_pci
*hc
= bch
->hw
;
1256 u_char rx_slot
= 0, tx_slot
= 0, pcm_mode
;
1258 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
1260 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1261 bch
->state
, protocol
, bch
->nr
, bc
);
1264 pcm_mode
= (bc
>> 24) & 0xff;
1265 if (pcm_mode
) { /* PCM SLOT USE */
1266 if (!test_bit(HFC_CFG_PCM
, &hc
->cfg
))
1268 "%s: pcm channel id without HFC_CFG_PCM\n",
1270 rx_slot
= (bc
>> 8) & 0xff;
1271 tx_slot
= (bc
>> 16) & 0xff;
1273 } else if (test_bit(HFC_CFG_PCM
, &hc
->cfg
) && (protocol
> ISDN_P_NONE
))
1274 printk(KERN_WARNING
"%s: no pcm channel id but HFC_CFG_PCM\n",
1276 if (hc
->chanlimit
> 1) {
1277 hc
->hw
.bswapped
= 0; /* B1 and B2 normal mode */
1278 hc
->hw
.sctrl_e
&= ~0x80;
1281 if (protocol
!= ISDN_P_NONE
) {
1282 hc
->hw
.bswapped
= 1; /* B1 and B2 exchanged */
1283 hc
->hw
.sctrl_e
|= 0x80;
1285 hc
->hw
.bswapped
= 0; /* B1 and B2 normal mode */
1286 hc
->hw
.sctrl_e
&= ~0x80;
1290 hc
->hw
.bswapped
= 0; /* B1 and B2 normal mode */
1291 hc
->hw
.sctrl_e
&= ~0x80;
1295 case (-1): /* used for init */
1299 if (bch
->state
== ISDN_P_NONE
)
1302 hc
->hw
.sctrl
&= ~SCTRL_B2_ENA
;
1303 hc
->hw
.sctrl_r
&= ~SCTRL_B2_ENA
;
1305 hc
->hw
.sctrl
&= ~SCTRL_B1_ENA
;
1306 hc
->hw
.sctrl_r
&= ~SCTRL_B1_ENA
;
1309 hc
->hw
.fifo_en
&= ~HFCPCI_FIFOEN_B2
;
1310 hc
->hw
.int_m1
&= ~(HFCPCI_INTS_B2TRANS
|
1313 hc
->hw
.fifo_en
&= ~HFCPCI_FIFOEN_B1
;
1314 hc
->hw
.int_m1
&= ~(HFCPCI_INTS_B1TRANS
|
1317 #ifdef REVERSE_BITORDER
1319 hc
->hw
.cirm
&= 0x7f;
1321 hc
->hw
.cirm
&= 0xbf;
1323 bch
->state
= ISDN_P_NONE
;
1325 test_and_clear_bit(FLG_HDLC
, &bch
->Flags
);
1326 test_and_clear_bit(FLG_TRANSPARENT
, &bch
->Flags
);
1328 case (ISDN_P_B_RAW
):
1329 bch
->state
= protocol
;
1331 hfcpci_clear_fifo_rx(hc
, (fifo2
& 2) ? 1 : 0);
1332 hfcpci_clear_fifo_tx(hc
, (fifo2
& 2) ? 1 : 0);
1334 hc
->hw
.sctrl
|= SCTRL_B2_ENA
;
1335 hc
->hw
.sctrl_r
|= SCTRL_B2_ENA
;
1336 #ifdef REVERSE_BITORDER
1337 hc
->hw
.cirm
|= 0x80;
1340 hc
->hw
.sctrl
|= SCTRL_B1_ENA
;
1341 hc
->hw
.sctrl_r
|= SCTRL_B1_ENA
;
1342 #ifdef REVERSE_BITORDER
1343 hc
->hw
.cirm
|= 0x40;
1347 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B2
;
1349 hc
->hw
.int_m1
|= (HFCPCI_INTS_B2TRANS
|
1352 hc
->hw
.conn
&= ~0x18;
1354 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B1
;
1356 hc
->hw
.int_m1
|= (HFCPCI_INTS_B1TRANS
|
1359 hc
->hw
.conn
&= ~0x03;
1361 test_and_set_bit(FLG_TRANSPARENT
, &bch
->Flags
);
1363 case (ISDN_P_B_HDLC
):
1364 bch
->state
= protocol
;
1366 hfcpci_clear_fifo_rx(hc
, (fifo2
& 2) ? 1 : 0);
1367 hfcpci_clear_fifo_tx(hc
, (fifo2
& 2) ? 1 : 0);
1369 hc
->hw
.sctrl
|= SCTRL_B2_ENA
;
1370 hc
->hw
.sctrl_r
|= SCTRL_B2_ENA
;
1372 hc
->hw
.sctrl
|= SCTRL_B1_ENA
;
1373 hc
->hw
.sctrl_r
|= SCTRL_B1_ENA
;
1376 hc
->hw
.last_bfifo_cnt
[1] = 0;
1377 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B2
;
1378 hc
->hw
.int_m1
|= (HFCPCI_INTS_B2TRANS
|
1381 hc
->hw
.conn
&= ~0x18;
1383 hc
->hw
.last_bfifo_cnt
[0] = 0;
1384 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B1
;
1385 hc
->hw
.int_m1
|= (HFCPCI_INTS_B1TRANS
|
1388 hc
->hw
.conn
&= ~0x03;
1390 test_and_set_bit(FLG_HDLC
, &bch
->Flags
);
1393 printk(KERN_DEBUG
"prot not known %x\n", protocol
);
1394 return -ENOPROTOOPT
;
1396 if (test_bit(HFC_CFG_PCM
, &hc
->cfg
)) {
1397 if ((protocol
== ISDN_P_NONE
) ||
1398 (protocol
== -1)) { /* init case */
1402 if (test_bit(HFC_CFG_SW_DD_DU
, &hc
->cfg
)) {
1411 hc
->hw
.conn
&= 0xc7;
1412 hc
->hw
.conn
|= 0x08;
1413 printk(KERN_DEBUG
"%s: Write_hfc: B2_SSL 0x%x\n",
1415 printk(KERN_DEBUG
"%s: Write_hfc: B2_RSL 0x%x\n",
1417 Write_hfc(hc
, HFCPCI_B2_SSL
, tx_slot
);
1418 Write_hfc(hc
, HFCPCI_B2_RSL
, rx_slot
);
1420 hc
->hw
.conn
&= 0xf8;
1421 hc
->hw
.conn
|= 0x01;
1422 printk(KERN_DEBUG
"%s: Write_hfc: B1_SSL 0x%x\n",
1424 printk(KERN_DEBUG
"%s: Write_hfc: B1_RSL 0x%x\n",
1426 Write_hfc(hc
, HFCPCI_B1_SSL
, tx_slot
);
1427 Write_hfc(hc
, HFCPCI_B1_RSL
, rx_slot
);
1430 Write_hfc(hc
, HFCPCI_SCTRL_E
, hc
->hw
.sctrl_e
);
1431 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
1432 Write_hfc(hc
, HFCPCI_FIFO_EN
, hc
->hw
.fifo_en
);
1433 Write_hfc(hc
, HFCPCI_SCTRL
, hc
->hw
.sctrl
);
1434 Write_hfc(hc
, HFCPCI_SCTRL_R
, hc
->hw
.sctrl_r
);
1435 Write_hfc(hc
, HFCPCI_CTMT
, hc
->hw
.ctmt
);
1436 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
1437 #ifdef REVERSE_BITORDER
1438 Write_hfc(hc
, HFCPCI_CIRM
, hc
->hw
.cirm
);
1444 set_hfcpci_rxtest(struct bchannel
*bch
, int protocol
, int chan
)
1446 struct hfc_pci
*hc
= bch
->hw
;
1448 if (bch
->debug
& DEBUG_HW_BCHANNEL
)
1450 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1451 bch
->state
, protocol
, bch
->nr
, chan
);
1452 if (bch
->nr
!= chan
) {
1454 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1459 case (ISDN_P_B_RAW
):
1460 bch
->state
= protocol
;
1461 hfcpci_clear_fifo_rx(hc
, (chan
& 2) ? 1 : 0);
1463 hc
->hw
.sctrl_r
|= SCTRL_B2_ENA
;
1464 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B2RX
;
1466 hc
->hw
.int_m1
|= HFCPCI_INTS_B2REC
;
1468 hc
->hw
.conn
&= ~0x18;
1469 #ifdef REVERSE_BITORDER
1470 hc
->hw
.cirm
|= 0x80;
1473 hc
->hw
.sctrl_r
|= SCTRL_B1_ENA
;
1474 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B1RX
;
1476 hc
->hw
.int_m1
|= HFCPCI_INTS_B1REC
;
1478 hc
->hw
.conn
&= ~0x03;
1479 #ifdef REVERSE_BITORDER
1480 hc
->hw
.cirm
|= 0x40;
1484 case (ISDN_P_B_HDLC
):
1485 bch
->state
= protocol
;
1486 hfcpci_clear_fifo_rx(hc
, (chan
& 2) ? 1 : 0);
1488 hc
->hw
.sctrl_r
|= SCTRL_B2_ENA
;
1489 hc
->hw
.last_bfifo_cnt
[1] = 0;
1490 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B2RX
;
1491 hc
->hw
.int_m1
|= HFCPCI_INTS_B2REC
;
1493 hc
->hw
.conn
&= ~0x18;
1495 hc
->hw
.sctrl_r
|= SCTRL_B1_ENA
;
1496 hc
->hw
.last_bfifo_cnt
[0] = 0;
1497 hc
->hw
.fifo_en
|= HFCPCI_FIFOEN_B1RX
;
1498 hc
->hw
.int_m1
|= HFCPCI_INTS_B1REC
;
1500 hc
->hw
.conn
&= ~0x03;
1504 printk(KERN_DEBUG
"prot not known %x\n", protocol
);
1505 return -ENOPROTOOPT
;
1507 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
1508 Write_hfc(hc
, HFCPCI_FIFO_EN
, hc
->hw
.fifo_en
);
1509 Write_hfc(hc
, HFCPCI_SCTRL_R
, hc
->hw
.sctrl_r
);
1510 Write_hfc(hc
, HFCPCI_CTMT
, hc
->hw
.ctmt
);
1511 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
1512 #ifdef REVERSE_BITORDER
1513 Write_hfc(hc
, HFCPCI_CIRM
, hc
->hw
.cirm
);
1519 deactivate_bchannel(struct bchannel
*bch
)
1521 struct hfc_pci
*hc
= bch
->hw
;
1524 spin_lock_irqsave(&hc
->lock
, flags
);
1525 mISDN_clear_bchannel(bch
);
1526 mode_hfcpci(bch
, bch
->nr
, ISDN_P_NONE
);
1527 spin_unlock_irqrestore(&hc
->lock
, flags
);
1531 * Layer 1 B-channel hardware access
1534 channel_bctrl(struct bchannel
*bch
, struct mISDN_ctrl_req
*cq
)
1536 return mISDN_ctrl_bchannel(bch
, cq
);
1539 hfc_bctrl(struct mISDNchannel
*ch
, u_int cmd
, void *arg
)
1541 struct bchannel
*bch
= container_of(ch
, struct bchannel
, ch
);
1542 struct hfc_pci
*hc
= bch
->hw
;
1546 if (bch
->debug
& DEBUG_HW
)
1547 printk(KERN_DEBUG
"%s: cmd:%x %p\n", __func__
, cmd
, arg
);
1550 spin_lock_irqsave(&hc
->lock
, flags
);
1551 ret
= set_hfcpci_rxtest(bch
, ISDN_P_B_RAW
, (int)(long)arg
);
1552 spin_unlock_irqrestore(&hc
->lock
, flags
);
1554 case HW_TESTRX_HDLC
:
1555 spin_lock_irqsave(&hc
->lock
, flags
);
1556 ret
= set_hfcpci_rxtest(bch
, ISDN_P_B_HDLC
, (int)(long)arg
);
1557 spin_unlock_irqrestore(&hc
->lock
, flags
);
1560 spin_lock_irqsave(&hc
->lock
, flags
);
1561 mode_hfcpci(bch
, bch
->nr
, ISDN_P_NONE
);
1562 spin_unlock_irqrestore(&hc
->lock
, flags
);
1566 test_and_clear_bit(FLG_OPEN
, &bch
->Flags
);
1567 deactivate_bchannel(bch
);
1568 ch
->protocol
= ISDN_P_NONE
;
1570 module_put(THIS_MODULE
);
1573 case CONTROL_CHANNEL
:
1574 ret
= channel_bctrl(bch
, arg
);
1577 printk(KERN_WARNING
"%s: unknown prim(%x)\n",
1584 * Layer2 -> Layer 1 Dchannel data
1587 hfcpci_l2l1D(struct mISDNchannel
*ch
, struct sk_buff
*skb
)
1589 struct mISDNdevice
*dev
= container_of(ch
, struct mISDNdevice
, D
);
1590 struct dchannel
*dch
= container_of(dev
, struct dchannel
, dev
);
1591 struct hfc_pci
*hc
= dch
->hw
;
1593 struct mISDNhead
*hh
= mISDN_HEAD_P(skb
);
1599 spin_lock_irqsave(&hc
->lock
, flags
);
1600 ret
= dchannel_senddata(dch
, skb
);
1601 if (ret
> 0) { /* direct TX */
1602 id
= hh
->id
; /* skb can be freed */
1603 hfcpci_fill_dfifo(dch
->hw
);
1605 spin_unlock_irqrestore(&hc
->lock
, flags
);
1606 queue_ch_frame(ch
, PH_DATA_CNF
, id
, NULL
);
1608 spin_unlock_irqrestore(&hc
->lock
, flags
);
1610 case PH_ACTIVATE_REQ
:
1611 spin_lock_irqsave(&hc
->lock
, flags
);
1612 if (hc
->hw
.protocol
== ISDN_P_NT_S0
) {
1614 if (test_bit(HFC_CFG_MASTER
, &hc
->cfg
))
1615 hc
->hw
.mst_m
|= HFCPCI_MASTER
;
1616 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
1617 if (test_bit(FLG_ACTIVE
, &dch
->Flags
)) {
1618 spin_unlock_irqrestore(&hc
->lock
, flags
);
1619 _queue_data(&dch
->dev
.D
, PH_ACTIVATE_IND
,
1620 MISDN_ID_ANY
, 0, NULL
, GFP_ATOMIC
);
1623 test_and_set_bit(FLG_L2_ACTIVATED
, &dch
->Flags
);
1624 Write_hfc(hc
, HFCPCI_STATES
, HFCPCI_ACTIVATE
|
1625 HFCPCI_DO_ACTION
| 1);
1627 ret
= l1_event(dch
->l1
, hh
->prim
);
1628 spin_unlock_irqrestore(&hc
->lock
, flags
);
1630 case PH_DEACTIVATE_REQ
:
1631 test_and_clear_bit(FLG_L2_ACTIVATED
, &dch
->Flags
);
1632 spin_lock_irqsave(&hc
->lock
, flags
);
1633 if (hc
->hw
.protocol
== ISDN_P_NT_S0
) {
1634 /* prepare deactivation */
1635 Write_hfc(hc
, HFCPCI_STATES
, 0x40);
1636 skb_queue_purge(&dch
->squeue
);
1638 dev_kfree_skb(dch
->tx_skb
);
1643 dev_kfree_skb(dch
->rx_skb
);
1646 test_and_clear_bit(FLG_TX_BUSY
, &dch
->Flags
);
1647 if (test_and_clear_bit(FLG_BUSY_TIMER
, &dch
->Flags
))
1648 del_timer(&dch
->timer
);
1650 if (test_and_clear_bit(FLG_L1_BUSY
, &dch
->Flags
))
1651 dchannel_sched_event(&hc
->dch
, D_CLEARBUSY
);
1653 hc
->hw
.mst_m
&= ~HFCPCI_MASTER
;
1654 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
1657 ret
= l1_event(dch
->l1
, hh
->prim
);
1659 spin_unlock_irqrestore(&hc
->lock
, flags
);
1668 * Layer2 -> Layer 1 Bchannel data
1671 hfcpci_l2l1B(struct mISDNchannel
*ch
, struct sk_buff
*skb
)
1673 struct bchannel
*bch
= container_of(ch
, struct bchannel
, ch
);
1674 struct hfc_pci
*hc
= bch
->hw
;
1676 struct mISDNhead
*hh
= mISDN_HEAD_P(skb
);
1677 unsigned long flags
;
1681 spin_lock_irqsave(&hc
->lock
, flags
);
1682 ret
= bchannel_senddata(bch
, skb
);
1683 if (ret
> 0) { /* direct TX */
1684 hfcpci_fill_fifo(bch
);
1687 spin_unlock_irqrestore(&hc
->lock
, flags
);
1689 case PH_ACTIVATE_REQ
:
1690 spin_lock_irqsave(&hc
->lock
, flags
);
1691 if (!test_and_set_bit(FLG_ACTIVE
, &bch
->Flags
))
1692 ret
= mode_hfcpci(bch
, bch
->nr
, ch
->protocol
);
1695 spin_unlock_irqrestore(&hc
->lock
, flags
);
1697 _queue_data(ch
, PH_ACTIVATE_IND
, MISDN_ID_ANY
, 0,
1700 case PH_DEACTIVATE_REQ
:
1701 deactivate_bchannel(bch
);
1702 _queue_data(ch
, PH_DEACTIVATE_IND
, MISDN_ID_ANY
, 0,
1713 * called for card init message
1717 inithfcpci(struct hfc_pci
*hc
)
1719 printk(KERN_DEBUG
"inithfcpci: entered\n");
1720 setup_timer(&hc
->dch
.timer
, (void *)hfcpci_dbusy_timer
,
1723 mode_hfcpci(&hc
->bch
[0], 1, -1);
1724 mode_hfcpci(&hc
->bch
[1], 2, -1);
1729 init_card(struct hfc_pci
*hc
)
1734 printk(KERN_DEBUG
"init_card: entered\n");
1737 spin_lock_irqsave(&hc
->lock
, flags
);
1739 spin_unlock_irqrestore(&hc
->lock
, flags
);
1740 if (request_irq(hc
->irq
, hfcpci_int
, IRQF_SHARED
, "HFC PCI", hc
)) {
1742 "mISDN: couldn't get interrupt %d\n", hc
->irq
);
1745 spin_lock_irqsave(&hc
->lock
, flags
);
1750 * Finally enable IRQ output
1751 * this is only allowed, if an IRQ routine is already
1752 * established for this HFC, so don't do that earlier
1755 spin_unlock_irqrestore(&hc
->lock
, flags
);
1757 set_current_state(TASK_UNINTERRUPTIBLE
);
1758 schedule_timeout((80 * HZ
) / 1000);
1759 printk(KERN_INFO
"HFC PCI: IRQ %d count %d\n",
1760 hc
->irq
, hc
->irqcnt
);
1761 /* now switch timer interrupt off */
1762 spin_lock_irqsave(&hc
->lock
, flags
);
1763 hc
->hw
.int_m1
&= ~HFCPCI_INTS_TIMER
;
1764 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
1765 /* reinit mode reg */
1766 Write_hfc(hc
, HFCPCI_MST_MODE
, hc
->hw
.mst_m
);
1769 "HFC PCI: IRQ(%d) getting no interrupts "
1770 "during init %d\n", hc
->irq
, 4 - cnt
);
1778 spin_unlock_irqrestore(&hc
->lock
, flags
);
1784 spin_unlock_irqrestore(&hc
->lock
, flags
);
1785 free_irq(hc
->irq
, hc
);
1790 channel_ctrl(struct hfc_pci
*hc
, struct mISDN_ctrl_req
*cq
)
1796 case MISDN_CTRL_GETOP
:
1797 cq
->op
= MISDN_CTRL_LOOP
| MISDN_CTRL_CONNECT
|
1798 MISDN_CTRL_DISCONNECT
| MISDN_CTRL_L1_TIMER3
;
1800 case MISDN_CTRL_LOOP
:
1801 /* channel 0 disabled loop */
1802 if (cq
->channel
< 0 || cq
->channel
> 2) {
1806 if (cq
->channel
& 1) {
1807 if (test_bit(HFC_CFG_SW_DD_DU
, &hc
->cfg
))
1811 printk(KERN_DEBUG
"%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1813 Write_hfc(hc
, HFCPCI_B1_SSL
, slot
);
1814 Write_hfc(hc
, HFCPCI_B1_RSL
, slot
);
1815 hc
->hw
.conn
= (hc
->hw
.conn
& ~7) | 6;
1816 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
1818 if (cq
->channel
& 2) {
1819 if (test_bit(HFC_CFG_SW_DD_DU
, &hc
->cfg
))
1823 printk(KERN_DEBUG
"%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1825 Write_hfc(hc
, HFCPCI_B2_SSL
, slot
);
1826 Write_hfc(hc
, HFCPCI_B2_RSL
, slot
);
1827 hc
->hw
.conn
= (hc
->hw
.conn
& ~0x38) | 0x30;
1828 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
1830 if (cq
->channel
& 3)
1831 hc
->hw
.trm
|= 0x80; /* enable IOM-loop */
1833 hc
->hw
.conn
= (hc
->hw
.conn
& ~0x3f) | 0x09;
1834 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
1835 hc
->hw
.trm
&= 0x7f; /* disable IOM-loop */
1837 Write_hfc(hc
, HFCPCI_TRM
, hc
->hw
.trm
);
1839 case MISDN_CTRL_CONNECT
:
1840 if (cq
->channel
== cq
->p1
) {
1844 if (cq
->channel
< 1 || cq
->channel
> 2 ||
1845 cq
->p1
< 1 || cq
->p1
> 2) {
1849 if (test_bit(HFC_CFG_SW_DD_DU
, &hc
->cfg
))
1853 printk(KERN_DEBUG
"%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1855 Write_hfc(hc
, HFCPCI_B1_SSL
, slot
);
1856 Write_hfc(hc
, HFCPCI_B2_RSL
, slot
);
1857 if (test_bit(HFC_CFG_SW_DD_DU
, &hc
->cfg
))
1861 printk(KERN_DEBUG
"%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1863 Write_hfc(hc
, HFCPCI_B2_SSL
, slot
);
1864 Write_hfc(hc
, HFCPCI_B1_RSL
, slot
);
1865 hc
->hw
.conn
= (hc
->hw
.conn
& ~0x3f) | 0x36;
1866 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
1868 Write_hfc(hc
, HFCPCI_TRM
, hc
->hw
.trm
);
1870 case MISDN_CTRL_DISCONNECT
:
1871 hc
->hw
.conn
= (hc
->hw
.conn
& ~0x3f) | 0x09;
1872 Write_hfc(hc
, HFCPCI_CONNECT
, hc
->hw
.conn
);
1873 hc
->hw
.trm
&= 0x7f; /* disable IOM-loop */
1875 case MISDN_CTRL_L1_TIMER3
:
1876 ret
= l1_event(hc
->dch
.l1
, HW_TIMER3_VALUE
| (cq
->p1
& 0xff));
1879 printk(KERN_WARNING
"%s: unknown Op %x\n",
1888 open_dchannel(struct hfc_pci
*hc
, struct mISDNchannel
*ch
,
1889 struct channel_req
*rq
)
1893 if (debug
& DEBUG_HW_OPEN
)
1894 printk(KERN_DEBUG
"%s: dev(%d) open from %p\n", __func__
,
1895 hc
->dch
.dev
.id
, __builtin_return_address(0));
1896 if (rq
->protocol
== ISDN_P_NONE
)
1898 if (rq
->adr
.channel
== 1) {
1899 /* TODO: E-Channel */
1902 if (!hc
->initdone
) {
1903 if (rq
->protocol
== ISDN_P_TE_S0
) {
1904 err
= create_l1(&hc
->dch
, hfc_l1callback
);
1908 hc
->hw
.protocol
= rq
->protocol
;
1909 ch
->protocol
= rq
->protocol
;
1910 err
= init_card(hc
);
1914 if (rq
->protocol
!= ch
->protocol
) {
1915 if (hc
->hw
.protocol
== ISDN_P_TE_S0
)
1916 l1_event(hc
->dch
.l1
, CLOSE_CHANNEL
);
1917 if (rq
->protocol
== ISDN_P_TE_S0
) {
1918 err
= create_l1(&hc
->dch
, hfc_l1callback
);
1922 hc
->hw
.protocol
= rq
->protocol
;
1923 ch
->protocol
= rq
->protocol
;
1928 if (((ch
->protocol
== ISDN_P_NT_S0
) && (hc
->dch
.state
== 3)) ||
1929 ((ch
->protocol
== ISDN_P_TE_S0
) && (hc
->dch
.state
== 7))) {
1930 _queue_data(ch
, PH_ACTIVATE_IND
, MISDN_ID_ANY
,
1931 0, NULL
, GFP_KERNEL
);
1934 if (!try_module_get(THIS_MODULE
))
1935 printk(KERN_WARNING
"%s:cannot get module\n", __func__
);
1940 open_bchannel(struct hfc_pci
*hc
, struct channel_req
*rq
)
1942 struct bchannel
*bch
;
1944 if (rq
->adr
.channel
== 0 || rq
->adr
.channel
> 2)
1946 if (rq
->protocol
== ISDN_P_NONE
)
1948 bch
= &hc
->bch
[rq
->adr
.channel
- 1];
1949 if (test_and_set_bit(FLG_OPEN
, &bch
->Flags
))
1950 return -EBUSY
; /* b-channel can be only open once */
1951 bch
->ch
.protocol
= rq
->protocol
;
1952 rq
->ch
= &bch
->ch
; /* TODO: E-channel */
1953 if (!try_module_get(THIS_MODULE
))
1954 printk(KERN_WARNING
"%s:cannot get module\n", __func__
);
1959 * device control function
1962 hfc_dctrl(struct mISDNchannel
*ch
, u_int cmd
, void *arg
)
1964 struct mISDNdevice
*dev
= container_of(ch
, struct mISDNdevice
, D
);
1965 struct dchannel
*dch
= container_of(dev
, struct dchannel
, dev
);
1966 struct hfc_pci
*hc
= dch
->hw
;
1967 struct channel_req
*rq
;
1970 if (dch
->debug
& DEBUG_HW
)
1971 printk(KERN_DEBUG
"%s: cmd:%x %p\n",
1972 __func__
, cmd
, arg
);
1976 if ((rq
->protocol
== ISDN_P_TE_S0
) ||
1977 (rq
->protocol
== ISDN_P_NT_S0
))
1978 err
= open_dchannel(hc
, ch
, rq
);
1980 err
= open_bchannel(hc
, rq
);
1983 if (debug
& DEBUG_HW_OPEN
)
1984 printk(KERN_DEBUG
"%s: dev(%d) close from %p\n",
1985 __func__
, hc
->dch
.dev
.id
,
1986 __builtin_return_address(0));
1987 module_put(THIS_MODULE
);
1989 case CONTROL_CHANNEL
:
1990 err
= channel_ctrl(hc
, arg
);
1993 if (dch
->debug
& DEBUG_HW
)
1994 printk(KERN_DEBUG
"%s: unknown command %x\n",
2002 setup_hw(struct hfc_pci
*hc
)
2006 printk(KERN_INFO
"mISDN: HFC-PCI driver %s\n", hfcpci_revision
);
2009 pci_set_master(hc
->pdev
);
2011 printk(KERN_WARNING
"HFC-PCI: No IRQ for PCI card found\n");
2015 (char __iomem
*)(unsigned long)hc
->pdev
->resource
[1].start
;
2017 if (!hc
->hw
.pci_io
) {
2018 printk(KERN_WARNING
"HFC-PCI: No IO-Mem for PCI card found\n");
2021 /* Allocate memory for FIFOS */
2022 /* the memory needs to be on a 32k boundary within the first 4G */
2023 pci_set_dma_mask(hc
->pdev
, 0xFFFF8000);
2024 buffer
= pci_alloc_consistent(hc
->pdev
, 0x8000, &hc
->hw
.dmahandle
);
2025 /* We silently assume the address is okay if nonzero */
2028 "HFC-PCI: Error allocating memory for FIFO!\n");
2031 hc
->hw
.fifos
= buffer
;
2032 pci_write_config_dword(hc
->pdev
, 0x80, hc
->hw
.dmahandle
);
2033 hc
->hw
.pci_io
= ioremap((ulong
) hc
->hw
.pci_io
, 256);
2035 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2036 (u_long
) hc
->hw
.pci_io
, (u_long
) hc
->hw
.fifos
,
2037 (u_long
) hc
->hw
.dmahandle
, hc
->irq
, HZ
);
2038 /* enable memory mapped ports, disable busmaster */
2039 pci_write_config_word(hc
->pdev
, PCI_COMMAND
, PCI_ENA_MEMIO
);
2043 Write_hfc(hc
, HFCPCI_INT_M1
, hc
->hw
.int_m1
);
2044 /* At this point the needed PCI config is done */
2045 /* fifos are still not enabled */
2046 setup_timer(&hc
->hw
.timer
, (void *)hfcpci_Timer
, (long)hc
);
2047 /* default PCM master */
2048 test_and_set_bit(HFC_CFG_MASTER
, &hc
->cfg
);
2053 release_card(struct hfc_pci
*hc
) {
2056 spin_lock_irqsave(&hc
->lock
, flags
);
2057 hc
->hw
.int_m2
= 0; /* interrupt output off ! */
2059 mode_hfcpci(&hc
->bch
[0], 1, ISDN_P_NONE
);
2060 mode_hfcpci(&hc
->bch
[1], 2, ISDN_P_NONE
);
2061 if (hc
->dch
.timer
.function
!= NULL
) {
2062 del_timer(&hc
->dch
.timer
);
2063 hc
->dch
.timer
.function
= NULL
;
2065 spin_unlock_irqrestore(&hc
->lock
, flags
);
2066 if (hc
->hw
.protocol
== ISDN_P_TE_S0
)
2067 l1_event(hc
->dch
.l1
, CLOSE_CHANNEL
);
2069 free_irq(hc
->irq
, hc
);
2070 release_io_hfcpci(hc
); /* must release after free_irq! */
2071 mISDN_unregister_device(&hc
->dch
.dev
);
2072 mISDN_freebchannel(&hc
->bch
[1]);
2073 mISDN_freebchannel(&hc
->bch
[0]);
2074 mISDN_freedchannel(&hc
->dch
);
2075 pci_set_drvdata(hc
->pdev
, NULL
);
2080 setup_card(struct hfc_pci
*card
)
2084 char name
[MISDN_MAX_IDLEN
];
2086 card
->dch
.debug
= debug
;
2087 spin_lock_init(&card
->lock
);
2088 mISDN_initdchannel(&card
->dch
, MAX_DFRAME_LEN_L1
, ph_state
);
2089 card
->dch
.hw
= card
;
2090 card
->dch
.dev
.Dprotocols
= (1 << ISDN_P_TE_S0
) | (1 << ISDN_P_NT_S0
);
2091 card
->dch
.dev
.Bprotocols
= (1 << (ISDN_P_B_RAW
& ISDN_P_B_MASK
)) |
2092 (1 << (ISDN_P_B_HDLC
& ISDN_P_B_MASK
));
2093 card
->dch
.dev
.D
.send
= hfcpci_l2l1D
;
2094 card
->dch
.dev
.D
.ctrl
= hfc_dctrl
;
2095 card
->dch
.dev
.nrbchan
= 2;
2096 for (i
= 0; i
< 2; i
++) {
2097 card
->bch
[i
].nr
= i
+ 1;
2098 set_channelmap(i
+ 1, card
->dch
.dev
.channelmap
);
2099 card
->bch
[i
].debug
= debug
;
2100 mISDN_initbchannel(&card
->bch
[i
], MAX_DATA_MEM
, poll
>> 1);
2101 card
->bch
[i
].hw
= card
;
2102 card
->bch
[i
].ch
.send
= hfcpci_l2l1B
;
2103 card
->bch
[i
].ch
.ctrl
= hfc_bctrl
;
2104 card
->bch
[i
].ch
.nr
= i
+ 1;
2105 list_add(&card
->bch
[i
].ch
.list
, &card
->dch
.dev
.bchannels
);
2107 err
= setup_hw(card
);
2110 snprintf(name
, MISDN_MAX_IDLEN
- 1, "hfc-pci.%d", HFC_cnt
+ 1);
2111 err
= mISDN_register_device(&card
->dch
.dev
, &card
->pdev
->dev
, name
);
2115 printk(KERN_INFO
"HFC %d cards installed\n", HFC_cnt
);
2118 mISDN_freebchannel(&card
->bch
[1]);
2119 mISDN_freebchannel(&card
->bch
[0]);
2120 mISDN_freedchannel(&card
->dch
);
2125 /* private data in the PCI devices list */
2132 static const struct _hfc_map hfc_map
[] =
2134 {HFC_CCD_2BD0
, 0, "CCD/Billion/Asuscom 2BD0"},
2135 {HFC_CCD_B000
, 0, "Billion B000"},
2136 {HFC_CCD_B006
, 0, "Billion B006"},
2137 {HFC_CCD_B007
, 0, "Billion B007"},
2138 {HFC_CCD_B008
, 0, "Billion B008"},
2139 {HFC_CCD_B009
, 0, "Billion B009"},
2140 {HFC_CCD_B00A
, 0, "Billion B00A"},
2141 {HFC_CCD_B00B
, 0, "Billion B00B"},
2142 {HFC_CCD_B00C
, 0, "Billion B00C"},
2143 {HFC_CCD_B100
, 0, "Seyeon B100"},
2144 {HFC_CCD_B700
, 0, "Primux II S0 B700"},
2145 {HFC_CCD_B701
, 0, "Primux II S0 NT B701"},
2146 {HFC_ABOCOM_2BD1
, 0, "Abocom/Magitek 2BD1"},
2147 {HFC_ASUS_0675
, 0, "Asuscom/Askey 675"},
2148 {HFC_BERKOM_TCONCEPT
, 0, "German telekom T-Concept"},
2149 {HFC_BERKOM_A1T
, 0, "German telekom A1T"},
2150 {HFC_ANIGMA_MC145575
, 0, "Motorola MC145575"},
2151 {HFC_ZOLTRIX_2BD0
, 0, "Zoltrix 2BD0"},
2152 {HFC_DIGI_DF_M_IOM2_E
, 0,
2153 "Digi International DataFire Micro V IOM2 (Europe)"},
2154 {HFC_DIGI_DF_M_E
, 0,
2155 "Digi International DataFire Micro V (Europe)"},
2156 {HFC_DIGI_DF_M_IOM2_A
, 0,
2157 "Digi International DataFire Micro V IOM2 (North America)"},
2158 {HFC_DIGI_DF_M_A
, 0,
2159 "Digi International DataFire Micro V (North America)"},
2160 {HFC_SITECOM_DC105V2
, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2164 static struct pci_device_id hfc_ids
[] =
2166 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_2BD0
),
2167 (unsigned long) &hfc_map
[0] },
2168 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B000
),
2169 (unsigned long) &hfc_map
[1] },
2170 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B006
),
2171 (unsigned long) &hfc_map
[2] },
2172 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B007
),
2173 (unsigned long) &hfc_map
[3] },
2174 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B008
),
2175 (unsigned long) &hfc_map
[4] },
2176 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B009
),
2177 (unsigned long) &hfc_map
[5] },
2178 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B00A
),
2179 (unsigned long) &hfc_map
[6] },
2180 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B00B
),
2181 (unsigned long) &hfc_map
[7] },
2182 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B00C
),
2183 (unsigned long) &hfc_map
[8] },
2184 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B100
),
2185 (unsigned long) &hfc_map
[9] },
2186 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B700
),
2187 (unsigned long) &hfc_map
[10] },
2188 { PCI_VDEVICE(CCD
, PCI_DEVICE_ID_CCD_B701
),
2189 (unsigned long) &hfc_map
[11] },
2190 { PCI_VDEVICE(ABOCOM
, PCI_DEVICE_ID_ABOCOM_2BD1
),
2191 (unsigned long) &hfc_map
[12] },
2192 { PCI_VDEVICE(ASUSTEK
, PCI_DEVICE_ID_ASUSTEK_0675
),
2193 (unsigned long) &hfc_map
[13] },
2194 { PCI_VDEVICE(BERKOM
, PCI_DEVICE_ID_BERKOM_T_CONCEPT
),
2195 (unsigned long) &hfc_map
[14] },
2196 { PCI_VDEVICE(BERKOM
, PCI_DEVICE_ID_BERKOM_A1T
),
2197 (unsigned long) &hfc_map
[15] },
2198 { PCI_VDEVICE(ANIGMA
, PCI_DEVICE_ID_ANIGMA_MC145575
),
2199 (unsigned long) &hfc_map
[16] },
2200 { PCI_VDEVICE(ZOLTRIX
, PCI_DEVICE_ID_ZOLTRIX_2BD0
),
2201 (unsigned long) &hfc_map
[17] },
2202 { PCI_VDEVICE(DIGI
, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E
),
2203 (unsigned long) &hfc_map
[18] },
2204 { PCI_VDEVICE(DIGI
, PCI_DEVICE_ID_DIGI_DF_M_E
),
2205 (unsigned long) &hfc_map
[19] },
2206 { PCI_VDEVICE(DIGI
, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A
),
2207 (unsigned long) &hfc_map
[20] },
2208 { PCI_VDEVICE(DIGI
, PCI_DEVICE_ID_DIGI_DF_M_A
),
2209 (unsigned long) &hfc_map
[21] },
2210 { PCI_VDEVICE(SITECOM
, PCI_DEVICE_ID_SITECOM_DC105V2
),
2211 (unsigned long) &hfc_map
[22] },
2216 hfc_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2219 struct hfc_pci
*card
;
2220 struct _hfc_map
*m
= (struct _hfc_map
*)ent
->driver_data
;
2222 card
= kzalloc(sizeof(struct hfc_pci
), GFP_ATOMIC
);
2224 printk(KERN_ERR
"No kmem for HFC card\n");
2228 card
->subtype
= m
->subtype
;
2229 err
= pci_enable_device(pdev
);
2235 printk(KERN_INFO
"mISDN_hfcpci: found adapter %s at %s\n",
2236 m
->name
, pci_name(pdev
));
2238 card
->irq
= pdev
->irq
;
2239 pci_set_drvdata(pdev
, card
);
2240 err
= setup_card(card
);
2242 pci_set_drvdata(pdev
, NULL
);
2247 hfc_remove_pci(struct pci_dev
*pdev
)
2249 struct hfc_pci
*card
= pci_get_drvdata(pdev
);
2255 printk(KERN_DEBUG
"%s: drvdata already removed\n",
2260 static struct pci_driver hfc_driver
= {
2263 .remove
= hfc_remove_pci
,
2264 .id_table
= hfc_ids
,
2268 _hfcpci_softirq(struct device
*dev
, void *arg
)
2270 struct hfc_pci
*hc
= dev_get_drvdata(dev
);
2271 struct bchannel
*bch
;
2275 if (hc
->hw
.int_m2
& HFCPCI_IRQ_ENABLE
) {
2276 spin_lock(&hc
->lock
);
2277 bch
= Sel_BCS(hc
, hc
->hw
.bswapped
? 2 : 1);
2278 if (bch
&& bch
->state
== ISDN_P_B_RAW
) { /* B1 rx&tx */
2279 main_rec_hfcpci(bch
);
2282 bch
= Sel_BCS(hc
, hc
->hw
.bswapped
? 1 : 2);
2283 if (bch
&& bch
->state
== ISDN_P_B_RAW
) { /* B2 rx&tx */
2284 main_rec_hfcpci(bch
);
2287 spin_unlock(&hc
->lock
);
2293 hfcpci_softirq(void *arg
)
2295 WARN_ON_ONCE(driver_for_each_device(&hfc_driver
.driver
, NULL
, arg
,
2296 _hfcpci_softirq
) != 0);
2298 /* if next event would be in the past ... */
2299 if ((s32
)(hfc_jiffies
+ tics
- jiffies
) <= 0)
2300 hfc_jiffies
= jiffies
+ 1;
2302 hfc_jiffies
+= tics
;
2303 hfc_tl
.expires
= hfc_jiffies
;
2313 poll
= HFCPCI_BTRANS_THRESHOLD
;
2315 if (poll
!= HFCPCI_BTRANS_THRESHOLD
) {
2316 tics
= (poll
* HZ
) / 8000;
2319 poll
= (tics
* 8000) / HZ
;
2320 if (poll
> 256 || poll
< 8) {
2321 printk(KERN_ERR
"%s: Wrong poll value %d not in range "
2322 "of 8..256.\n", __func__
, poll
);
2327 if (poll
!= HFCPCI_BTRANS_THRESHOLD
) {
2328 printk(KERN_INFO
"%s: Using alternative poll value of %d\n",
2330 hfc_tl
.function
= (void *)hfcpci_softirq
;
2332 init_timer(&hfc_tl
);
2333 hfc_tl
.expires
= jiffies
+ tics
;
2334 hfc_jiffies
= hfc_tl
.expires
;
2337 tics
= 0; /* indicate the use of controller's timer */
2339 err
= pci_register_driver(&hfc_driver
);
2341 if (timer_pending(&hfc_tl
))
2351 if (timer_pending(&hfc_tl
))
2354 pci_unregister_driver(&hfc_driver
);
2357 module_init(HFC_init
);
2358 module_exit(HFC_cleanup
);
2360 MODULE_DEVICE_TABLE(pci
, hfc_ids
);