]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/isdn/hisax/hfc_2bds0.c
1 /* $Id: hfc_2bds0.c,v 1.18.2.6 2004/02/11 13:21:33 keil Exp $
3 * specific routines for CCD's HFC 2BDS0
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
13 #include <linux/init.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
17 #include "hfc_2bds0.h"
19 #include <linux/interrupt.h>
25 #define byteout(addr, val) outb(val, addr)
26 #define bytein(addr) inb(addr)
29 dummyf(struct IsdnCardState
*cs
, u_char
*data
, int size
)
31 printk(KERN_WARNING
"HiSax: hfcd dummy fifo called\n");
35 ReadReg(struct IsdnCardState
*cs
, int data
, u_char reg
)
40 if (cs
->hw
.hfcD
.cip
!= reg
) {
41 cs
->hw
.hfcD
.cip
= reg
;
42 byteout(cs
->hw
.hfcD
.addr
| 1, reg
);
44 ret
= bytein(cs
->hw
.hfcD
.addr
);
46 if (cs
->debug
& L1_DEB_HSCX_FIFO
&& (data
!= 2))
47 debugl1(cs
, "t3c RD %02x %02x", reg
, ret
);
50 ret
= bytein(cs
->hw
.hfcD
.addr
| 1);
55 WriteReg(struct IsdnCardState
*cs
, int data
, u_char reg
, u_char value
)
57 if (cs
->hw
.hfcD
.cip
!= reg
) {
58 cs
->hw
.hfcD
.cip
= reg
;
59 byteout(cs
->hw
.hfcD
.addr
| 1, reg
);
62 byteout(cs
->hw
.hfcD
.addr
, value
);
64 if (cs
->debug
& L1_DEB_HSCX_FIFO
&& (data
!= HFCD_DATA_NODEB
))
65 debugl1(cs
, "t3c W%c %02x %02x", data
? 'D' : 'C', reg
, value
);
69 /* Interface functions */
72 readreghfcd(struct IsdnCardState
*cs
, u_char offset
)
74 return (ReadReg(cs
, HFCD_DATA
, offset
));
78 writereghfcd(struct IsdnCardState
*cs
, u_char offset
, u_char value
)
80 WriteReg(cs
, HFCD_DATA
, offset
, value
);
84 WaitForBusy(struct IsdnCardState
*cs
)
88 while (!(ReadReg(cs
, HFCD_DATA
, HFCD_STAT
) & HFCD_BUSY
) && to
) {
93 printk(KERN_WARNING
"HiSax: WaitForBusy timeout\n");
98 WaitNoBusy(struct IsdnCardState
*cs
)
102 while ((ReadReg(cs
, HFCD_STATUS
, HFCD_STATUS
) & HFCD_BUSY
) && to
) {
107 printk(KERN_WARNING
"HiSax: WaitNoBusy timeout\n");
112 SelFiFo(struct IsdnCardState
*cs
, u_char FiFo
)
116 if (cs
->hw
.hfcD
.fifo
== FiFo
)
119 case 0: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_B1
;
121 case 1: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_B1
;
123 case 2: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_B2
;
125 case 3: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_B2
;
127 case 4: cip
= HFCD_FIFO
| HFCD_Z1
| HFCD_SEND
;
129 case 5: cip
= HFCD_FIFO
| HFCD_Z1
| HFCD_REC
;
132 debugl1(cs
, "SelFiFo Error");
135 cs
->hw
.hfcD
.fifo
= FiFo
;
137 cs
->BC_Write_Reg(cs
, HFCD_DATA
, cip
, 0);
143 GetFreeFifoBytes_B(struct BCState
*bcs
)
147 if (bcs
->hw
.hfc
.f1
== bcs
->hw
.hfc
.f2
)
148 return (bcs
->cs
->hw
.hfcD
.bfifosize
);
149 s
= bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] - bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f2
];
151 s
+= bcs
->cs
->hw
.hfcD
.bfifosize
;
152 s
= bcs
->cs
->hw
.hfcD
.bfifosize
- s
;
157 GetFreeFifoBytes_D(struct IsdnCardState
*cs
)
161 if (cs
->hw
.hfcD
.f1
== cs
->hw
.hfcD
.f2
)
162 return (cs
->hw
.hfcD
.dfifosize
);
163 s
= cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
] - cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f2
];
165 s
+= cs
->hw
.hfcD
.dfifosize
;
166 s
= cs
->hw
.hfcD
.dfifosize
- s
;
171 ReadZReg(struct IsdnCardState
*cs
, u_char reg
)
176 val
= 256 * ReadReg(cs
, HFCD_DATA
, reg
| HFCB_Z_HIGH
);
178 val
+= ReadReg(cs
, HFCD_DATA
, reg
| HFCB_Z_LOW
);
182 static struct sk_buff
183 *hfc_empty_fifo(struct BCState
*bcs
, int count
)
187 struct IsdnCardState
*cs
= bcs
->cs
;
192 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
193 debugl1(cs
, "hfc_empty_fifo");
195 if (count
> HSCX_BUFMAX
+ 3) {
196 if (cs
->debug
& L1_DEB_WARN
)
197 debugl1(cs
, "hfc_empty_fifo: incoming packet too large");
198 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
199 while (idx
++ < count
) {
201 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
204 } else if (count
< 4) {
205 if (cs
->debug
& L1_DEB_WARN
)
206 debugl1(cs
, "hfc_empty_fifo: incoming packet too small");
207 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
208 #ifdef ERROR_STATISTIC
211 while ((idx
++ < count
) && WaitNoBusy(cs
))
212 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
214 } else if (!(skb
= dev_alloc_skb(count
- 3)))
215 printk(KERN_WARNING
"HFC: receive out of memory\n");
217 ptr
= skb_put(skb
, count
- 3);
219 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
220 while (idx
< (count
- 3)) {
223 *ptr
= ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
227 if (idx
!= count
- 3) {
228 debugl1(cs
, "RFIFO BUSY error");
229 printk(KERN_WARNING
"HFC FIFO channel %d BUSY Error\n", bcs
->channel
);
230 dev_kfree_skb_irq(skb
);
234 chksum
= (ReadReg(cs
, HFCD_DATA
, cip
) << 8);
236 chksum
+= ReadReg(cs
, HFCD_DATA
, cip
);
238 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
239 if (cs
->debug
& L1_DEB_HSCX
)
240 debugl1(cs
, "hfc_empty_fifo %d chksum %x stat %x",
241 bcs
->channel
, chksum
, stat
);
243 debugl1(cs
, "FIFO CRC error");
244 dev_kfree_skb_irq(skb
);
246 #ifdef ERROR_STATISTIC
254 stat
= ReadReg(cs
, HFCD_DATA
, HFCB_FIFO
| HFCB_F2_INC
|
255 HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
261 hfc_fill_fifo(struct BCState
*bcs
)
263 struct IsdnCardState
*cs
= bcs
->cs
;
270 if (bcs
->tx_skb
->len
<= 0)
272 SelFiFo(cs
, HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
273 cip
= HFCB_FIFO
| HFCB_F1
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
275 bcs
->hw
.hfc
.f1
= ReadReg(cs
, HFCD_DATA
, cip
);
277 cip
= HFCB_FIFO
| HFCB_F2
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
279 bcs
->hw
.hfc
.f2
= ReadReg(cs
, HFCD_DATA
, cip
);
280 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] = ReadZReg(cs
, HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
281 if (cs
->debug
& L1_DEB_HSCX
)
282 debugl1(cs
, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
283 bcs
->channel
, bcs
->hw
.hfc
.f1
, bcs
->hw
.hfc
.f2
,
284 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
]);
285 fcnt
= bcs
->hw
.hfc
.f1
- bcs
->hw
.hfc
.f2
;
289 if (cs
->debug
& L1_DEB_HSCX
)
290 debugl1(cs
, "hfc_fill_fifo more as 30 frames");
293 count
= GetFreeFifoBytes_B(bcs
);
294 if (cs
->debug
& L1_DEB_HSCX
)
295 debugl1(cs
, "hfc_fill_fifo %d count(%u/%d),%lx",
296 bcs
->channel
, bcs
->tx_skb
->len
,
297 count
, current
->state
);
298 if (count
< bcs
->tx_skb
->len
) {
299 if (cs
->debug
& L1_DEB_HSCX
)
300 debugl1(cs
, "hfc_fill_fifo no fifo mem");
303 cip
= HFCB_FIFO
| HFCB_FIFO_IN
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
307 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
++]);
308 while (idx
< bcs
->tx_skb
->len
) {
311 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
]);
314 if (idx
!= bcs
->tx_skb
->len
) {
315 debugl1(cs
, "FIFO Send BUSY error");
316 printk(KERN_WARNING
"HFC S FIFO channel %d BUSY Error\n", bcs
->channel
);
318 bcs
->tx_cnt
-= bcs
->tx_skb
->len
;
319 if (test_bit(FLG_LLI_L1WAKEUP
, &bcs
->st
->lli
.flag
) &&
320 (PACKET_NOACK
!= bcs
->tx_skb
->pkt_type
)) {
322 spin_lock_irqsave(&bcs
->aclock
, flags
);
323 bcs
->ackcnt
+= bcs
->tx_skb
->len
;
324 spin_unlock_irqrestore(&bcs
->aclock
, flags
);
325 schedule_event(bcs
, B_ACKPENDING
);
327 dev_kfree_skb_any(bcs
->tx_skb
);
332 ReadReg(cs
, HFCD_DATA
, HFCB_FIFO
| HFCB_F1_INC
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
334 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
339 hfc_send_data(struct BCState
*bcs
)
341 struct IsdnCardState
*cs
= bcs
->cs
;
343 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
345 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
347 debugl1(cs
, "send_data %d blocked", bcs
->channel
);
351 main_rec_2bds0(struct BCState
*bcs
)
353 struct IsdnCardState
*cs
= bcs
->cs
;
356 int receive
, count
= 5;
361 if (test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
362 debugl1(cs
, "rec_data %d blocked", bcs
->channel
);
365 SelFiFo(cs
, HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
366 cip
= HFCB_FIFO
| HFCB_F1
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
368 f1
= ReadReg(cs
, HFCD_DATA
, cip
);
369 cip
= HFCB_FIFO
| HFCB_F2
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
371 f2
= ReadReg(cs
, HFCD_DATA
, cip
);
373 if (cs
->debug
& L1_DEB_HSCX
)
374 debugl1(cs
, "hfc rec %d f1(%d) f2(%d)",
375 bcs
->channel
, f1
, f2
);
376 z1
= ReadZReg(cs
, HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
377 z2
= ReadZReg(cs
, HFCB_FIFO
| HFCB_Z2
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
380 rcnt
+= cs
->hw
.hfcD
.bfifosize
;
382 if (cs
->debug
& L1_DEB_HSCX
)
383 debugl1(cs
, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
384 bcs
->channel
, z1
, z2
, rcnt
);
385 if ((skb
= hfc_empty_fifo(bcs
, rcnt
))) {
386 skb_queue_tail(&bcs
->rqueue
, skb
);
387 schedule_event(bcs
, B_RCVBUFREADY
);
398 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
399 if (count
&& receive
)
405 mode_2bs0(struct BCState
*bcs
, int mode
, int bc
)
407 struct IsdnCardState
*cs
= bcs
->cs
;
409 if (cs
->debug
& L1_DEB_HSCX
)
410 debugl1(cs
, "HFCD bchannel mode %d bchan %d/%d",
411 mode
, bc
, bcs
->channel
);
417 cs
->hw
.hfcD
.conn
|= 0x18;
418 cs
->hw
.hfcD
.sctrl
&= ~SCTRL_B2_ENA
;
420 cs
->hw
.hfcD
.conn
|= 0x3;
421 cs
->hw
.hfcD
.sctrl
&= ~SCTRL_B1_ENA
;
424 case (L1_MODE_TRANS
):
426 cs
->hw
.hfcD
.ctmt
|= 2;
427 cs
->hw
.hfcD
.conn
&= ~0x18;
428 cs
->hw
.hfcD
.sctrl
|= SCTRL_B2_ENA
;
430 cs
->hw
.hfcD
.ctmt
|= 1;
431 cs
->hw
.hfcD
.conn
&= ~0x3;
432 cs
->hw
.hfcD
.sctrl
|= SCTRL_B1_ENA
;
437 cs
->hw
.hfcD
.ctmt
&= ~2;
438 cs
->hw
.hfcD
.conn
&= ~0x18;
439 cs
->hw
.hfcD
.sctrl
|= SCTRL_B2_ENA
;
441 cs
->hw
.hfcD
.ctmt
&= ~1;
442 cs
->hw
.hfcD
.conn
&= ~0x3;
443 cs
->hw
.hfcD
.sctrl
|= SCTRL_B1_ENA
;
447 WriteReg(cs
, HFCD_DATA
, HFCD_SCTRL
, cs
->hw
.hfcD
.sctrl
);
448 WriteReg(cs
, HFCD_DATA
, HFCD_CTMT
, cs
->hw
.hfcD
.ctmt
);
449 WriteReg(cs
, HFCD_DATA
, HFCD_CONN
, cs
->hw
.hfcD
.conn
);
453 hfc_l2l1(struct PStack
*st
, int pr
, void *arg
)
455 struct BCState
*bcs
= st
->l1
.bcs
;
456 struct sk_buff
*skb
= arg
;
460 case (PH_DATA
| REQUEST
):
461 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
463 skb_queue_tail(&bcs
->squeue
, skb
);
466 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
467 bcs
->cs
->BC_Send_Data(bcs
);
469 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
471 case (PH_PULL
| INDICATION
):
472 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
474 printk(KERN_WARNING
"hfc_l2l1: this shouldn't happen\n");
476 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
478 bcs
->cs
->BC_Send_Data(bcs
);
480 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
482 case (PH_PULL
| REQUEST
):
484 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
485 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
487 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
489 case (PH_ACTIVATE
| REQUEST
):
490 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
491 test_and_set_bit(BC_FLG_ACTIV
, &bcs
->Flag
);
492 mode_2bs0(bcs
, st
->l1
.mode
, st
->l1
.bc
);
493 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
494 l1_msg_b(st
, pr
, arg
);
496 case (PH_DEACTIVATE
| REQUEST
):
497 l1_msg_b(st
, pr
, arg
);
499 case (PH_DEACTIVATE
| CONFIRM
):
500 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
501 test_and_clear_bit(BC_FLG_ACTIV
, &bcs
->Flag
);
502 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
503 mode_2bs0(bcs
, 0, st
->l1
.bc
);
504 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
505 st
->l1
.l1l2(st
, PH_DEACTIVATE
| CONFIRM
, NULL
);
511 close_2bs0(struct BCState
*bcs
)
513 mode_2bs0(bcs
, 0, bcs
->channel
);
514 if (test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
515 skb_queue_purge(&bcs
->rqueue
);
516 skb_queue_purge(&bcs
->squeue
);
518 dev_kfree_skb_any(bcs
->tx_skb
);
520 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
526 open_hfcstate(struct IsdnCardState
*cs
, struct BCState
*bcs
)
528 if (!test_and_set_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
529 skb_queue_head_init(&bcs
->rqueue
);
530 skb_queue_head_init(&bcs
->squeue
);
533 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
540 setstack_2b(struct PStack
*st
, struct BCState
*bcs
)
542 bcs
->channel
= st
->l1
.bc
;
543 if (open_hfcstate(st
->l1
.hardware
, bcs
))
546 st
->l2
.l2l1
= hfc_l2l1
;
547 setstack_manager(st
);
554 hfcd_bh(struct work_struct
*work
)
556 struct IsdnCardState
*cs
=
557 container_of(work
, struct IsdnCardState
, tqueue
);
559 if (test_and_clear_bit(D_L1STATECHANGE
, &cs
->event
)) {
560 switch (cs
->dc
.hfcd
.ph_state
) {
562 l1_msg(cs
, HW_RESET
| INDICATION
, NULL
);
565 l1_msg(cs
, HW_DEACTIVATE
| INDICATION
, NULL
);
568 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
571 l1_msg(cs
, HW_INFO2
| INDICATION
, NULL
);
574 l1_msg(cs
, HW_INFO4_P8
| INDICATION
, NULL
);
580 if (test_and_clear_bit(D_RCVBUFREADY
, &cs
->event
))
581 DChannel_proc_rcv(cs
);
582 if (test_and_clear_bit(D_XMTBUFREADY
, &cs
->event
))
583 DChannel_proc_xmt(cs
);
587 int receive_dmsg(struct IsdnCardState
*cs
)
592 u_char stat
, cip
, f1
, f2
;
597 if (test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
598 debugl1(cs
, "rec_dmsg blocked");
601 SelFiFo(cs
, 4 | HFCD_REC
);
602 cip
= HFCD_FIFO
| HFCD_F1
| HFCD_REC
;
604 f1
= cs
->readisac(cs
, cip
) & 0xf;
605 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_REC
;
607 f2
= cs
->readisac(cs
, cip
) & 0xf;
608 while ((f1
!= f2
) && count
--) {
609 z1
= ReadZReg(cs
, HFCD_FIFO
| HFCD_Z1
| HFCD_REC
);
610 z2
= ReadZReg(cs
, HFCD_FIFO
| HFCD_Z2
| HFCD_REC
);
613 rcnt
+= cs
->hw
.hfcD
.dfifosize
;
615 if (cs
->debug
& L1_DEB_ISAC
)
616 debugl1(cs
, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
617 f1
, f2
, z1
, z2
, rcnt
);
619 cip
= HFCD_FIFO
| HFCD_FIFO_OUT
| HFCD_REC
;
620 if (rcnt
> MAX_DFRAME_LEN
+ 3) {
621 if (cs
->debug
& L1_DEB_WARN
)
622 debugl1(cs
, "empty_fifo d: incoming packet too large");
624 if (!(WaitNoBusy(cs
)))
626 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
629 } else if (rcnt
< 4) {
630 if (cs
->debug
& L1_DEB_WARN
)
631 debugl1(cs
, "empty_fifo d: incoming packet too small");
632 while ((idx
++ < rcnt
) && WaitNoBusy(cs
))
633 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
634 } else if ((skb
= dev_alloc_skb(rcnt
- 3))) {
635 ptr
= skb_put(skb
, rcnt
- 3);
636 while (idx
< (rcnt
- 3)) {
637 if (!(WaitNoBusy(cs
)))
639 *ptr
= ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
643 if (idx
!= (rcnt
- 3)) {
644 debugl1(cs
, "RFIFO D BUSY error");
645 printk(KERN_WARNING
"HFC DFIFO channel BUSY Error\n");
646 dev_kfree_skb_irq(skb
);
648 #ifdef ERROR_STATISTIC
653 chksum
= (ReadReg(cs
, HFCD_DATA
, cip
) << 8);
655 chksum
+= ReadReg(cs
, HFCD_DATA
, cip
);
657 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
658 if (cs
->debug
& L1_DEB_ISAC
)
659 debugl1(cs
, "empty_dfifo chksum %x stat %x",
662 debugl1(cs
, "FIFO CRC error");
663 dev_kfree_skb_irq(skb
);
665 #ifdef ERROR_STATISTIC
669 skb_queue_tail(&cs
->rq
, skb
);
670 schedule_event(cs
, D_RCVBUFREADY
);
674 printk(KERN_WARNING
"HFC: D receive out of memory\n");
676 cip
= HFCD_FIFO
| HFCD_F2_INC
| HFCD_REC
;
678 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
680 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_REC
;
682 f2
= cs
->readisac(cs
, cip
) & 0xf;
684 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
689 hfc_fill_dfifo(struct IsdnCardState
*cs
)
697 if (cs
->tx_skb
->len
<= 0)
700 SelFiFo(cs
, 4 | HFCD_SEND
);
701 cip
= HFCD_FIFO
| HFCD_F1
| HFCD_SEND
;
703 cs
->hw
.hfcD
.f1
= ReadReg(cs
, HFCD_DATA
, cip
) & 0xf;
705 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_SEND
;
706 cs
->hw
.hfcD
.f2
= ReadReg(cs
, HFCD_DATA
, cip
) & 0xf;
707 cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
] = ReadZReg(cs
, HFCD_FIFO
| HFCD_Z1
| HFCD_SEND
);
708 if (cs
->debug
& L1_DEB_ISAC
)
709 debugl1(cs
, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)",
710 cs
->hw
.hfcD
.f1
, cs
->hw
.hfcD
.f2
,
711 cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
]);
712 fcnt
= cs
->hw
.hfcD
.f1
- cs
->hw
.hfcD
.f2
;
716 if (cs
->debug
& L1_DEB_HSCX
)
717 debugl1(cs
, "hfc_fill_Dfifo more as 14 frames");
720 count
= GetFreeFifoBytes_D(cs
);
721 if (cs
->debug
& L1_DEB_ISAC
)
722 debugl1(cs
, "hfc_fill_Dfifo count(%u/%d)",
723 cs
->tx_skb
->len
, count
);
724 if (count
< cs
->tx_skb
->len
) {
725 if (cs
->debug
& L1_DEB_ISAC
)
726 debugl1(cs
, "hfc_fill_Dfifo no fifo mem");
729 cip
= HFCD_FIFO
| HFCD_FIFO_IN
| HFCD_SEND
;
733 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, cs
->tx_skb
->data
[idx
++]);
734 while (idx
< cs
->tx_skb
->len
) {
735 if (!(WaitNoBusy(cs
)))
737 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, cs
->tx_skb
->data
[idx
]);
740 if (idx
!= cs
->tx_skb
->len
) {
741 debugl1(cs
, "DFIFO Send BUSY error");
742 printk(KERN_WARNING
"HFC S DFIFO channel BUSY Error\n");
746 ReadReg(cs
, HFCD_DATA
, HFCD_FIFO
| HFCD_F1_INC
| HFCD_SEND
);
747 dev_kfree_skb_any(cs
->tx_skb
);
754 struct BCState
*Sel_BCS(struct IsdnCardState
*cs
, int channel
)
756 if (cs
->bcs
[0].mode
&& (cs
->bcs
[0].channel
== channel
))
757 return (&cs
->bcs
[0]);
758 else if (cs
->bcs
[1].mode
&& (cs
->bcs
[1].channel
== channel
))
759 return (&cs
->bcs
[1]);
765 hfc2bds0_interrupt(struct IsdnCardState
*cs
, u_char val
)
771 if (cs
->debug
& L1_DEB_ISAC
)
772 debugl1(cs
, "HFCD irq %x %s", val
,
773 test_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
) ?
774 "locked" : "unlocked");
775 val
&= cs
->hw
.hfcD
.int_m1
;
776 if (val
& 0x40) { /* TE state machine irq */
777 exval
= cs
->readisac(cs
, HFCD_STATES
) & 0xf;
778 if (cs
->debug
& L1_DEB_ISAC
)
779 debugl1(cs
, "ph_state chg %d->%d", cs
->dc
.hfcd
.ph_state
,
781 cs
->dc
.hfcd
.ph_state
= exval
;
782 schedule_event(cs
, D_L1STATECHANGE
);
786 if (test_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
787 cs
->hw
.hfcD
.int_s1
|= val
;
790 if (cs
->hw
.hfcD
.int_s1
& 0x18) {
792 val
= cs
->hw
.hfcD
.int_s1
;
793 cs
->hw
.hfcD
.int_s1
= exval
;
796 if (!(bcs
= Sel_BCS(cs
, 0))) {
798 debugl1(cs
, "hfcd spurious 0x08 IRQ");
803 if (!(bcs
= Sel_BCS(cs
, 1))) {
805 debugl1(cs
, "hfcd spurious 0x10 IRQ");
810 if (!(bcs
= Sel_BCS(cs
, 0))) {
812 debugl1(cs
, "hfcd spurious 0x01 IRQ");
815 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
817 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
819 debugl1(cs
, "fill_data %d blocked", bcs
->channel
);
821 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
822 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
824 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
826 debugl1(cs
, "fill_data %d blocked", bcs
->channel
);
828 schedule_event(bcs
, B_XMTBUFREADY
);
834 if (!(bcs
= Sel_BCS(cs
, 1))) {
836 debugl1(cs
, "hfcd spurious 0x02 IRQ");
839 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
841 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
843 debugl1(cs
, "fill_data %d blocked", bcs
->channel
);
845 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
846 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
848 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
850 debugl1(cs
, "fill_data %d blocked", bcs
->channel
);
852 schedule_event(bcs
, B_XMTBUFREADY
);
857 if (val
& 0x20) { /* receive dframe */
860 if (val
& 0x04) { /* dframe transmitted */
861 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
862 del_timer(&cs
->dbusytimer
);
863 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
864 schedule_event(cs
, D_CLEARBUSY
);
866 if (cs
->tx_skb
->len
) {
867 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
869 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
871 debugl1(cs
, "hfc_fill_dfifo irq blocked");
875 dev_kfree_skb_irq(cs
->tx_skb
);
880 if ((cs
->tx_skb
= skb_dequeue(&cs
->sq
))) {
882 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
884 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
886 debugl1(cs
, "hfc_fill_dfifo irq blocked");
889 schedule_event(cs
, D_XMTBUFREADY
);
892 if (cs
->hw
.hfcD
.int_s1
&& count
--) {
893 val
= cs
->hw
.hfcD
.int_s1
;
894 cs
->hw
.hfcD
.int_s1
= 0;
895 if (cs
->debug
& L1_DEB_ISAC
)
896 debugl1(cs
, "HFCD irq %x loop %d", val
, 15-count
);
903 HFCD_l1hw(struct PStack
*st
, int pr
, void *arg
)
905 struct IsdnCardState
*cs
= (struct IsdnCardState
*) st
->l1
.hardware
;
906 struct sk_buff
*skb
= arg
;
910 case (PH_DATA
| REQUEST
):
911 if (cs
->debug
& DEB_DLOG_HEX
)
912 LogFrame(cs
, skb
->data
, skb
->len
);
913 if (cs
->debug
& DEB_DLOG_VERBOSE
)
914 dlogframe(cs
, skb
, 0);
915 spin_lock_irqsave(&cs
->lock
, flags
);
917 skb_queue_tail(&cs
->sq
, skb
);
918 #ifdef L2FRAME_DEBUG /* psa */
919 if (cs
->debug
& L1_DEB_LAPD
)
920 Logl2Frame(cs
, skb
, "PH_DATA Queued", 0);
925 #ifdef L2FRAME_DEBUG /* psa */
926 if (cs
->debug
& L1_DEB_LAPD
)
927 Logl2Frame(cs
, skb
, "PH_DATA", 0);
929 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
931 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
933 debugl1(cs
, "hfc_fill_dfifo blocked");
936 spin_unlock_irqrestore(&cs
->lock
, flags
);
938 case (PH_PULL
| INDICATION
):
939 spin_lock_irqsave(&cs
->lock
, flags
);
941 if (cs
->debug
& L1_DEB_WARN
)
942 debugl1(cs
, " l2l1 tx_skb exist this shouldn't happen");
943 skb_queue_tail(&cs
->sq
, skb
);
944 spin_unlock_irqrestore(&cs
->lock
, flags
);
947 if (cs
->debug
& DEB_DLOG_HEX
)
948 LogFrame(cs
, skb
->data
, skb
->len
);
949 if (cs
->debug
& DEB_DLOG_VERBOSE
)
950 dlogframe(cs
, skb
, 0);
953 #ifdef L2FRAME_DEBUG /* psa */
954 if (cs
->debug
& L1_DEB_LAPD
)
955 Logl2Frame(cs
, skb
, "PH_DATA_PULLED", 0);
957 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
959 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
961 debugl1(cs
, "hfc_fill_dfifo blocked");
962 spin_unlock_irqrestore(&cs
->lock
, flags
);
964 case (PH_PULL
| REQUEST
):
965 #ifdef L2FRAME_DEBUG /* psa */
966 if (cs
->debug
& L1_DEB_LAPD
)
967 debugl1(cs
, "-> PH_REQUEST_PULL");
970 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
971 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
973 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
975 case (HW_RESET
| REQUEST
):
976 spin_lock_irqsave(&cs
->lock
, flags
);
977 cs
->writeisac(cs
, HFCD_STATES
, HFCD_LOAD_STATE
| 3); /* HFC ST 3 */
979 cs
->writeisac(cs
, HFCD_STATES
, 3); /* HFC ST 2 */
980 cs
->hw
.hfcD
.mst_m
|= HFCD_MASTER
;
981 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
982 cs
->writeisac(cs
, HFCD_STATES
, HFCD_ACTIVATE
| HFCD_DO_ACTION
);
983 spin_unlock_irqrestore(&cs
->lock
, flags
);
984 l1_msg(cs
, HW_POWERUP
| CONFIRM
, NULL
);
986 case (HW_ENABLE
| REQUEST
):
987 spin_lock_irqsave(&cs
->lock
, flags
);
988 cs
->writeisac(cs
, HFCD_STATES
, HFCD_ACTIVATE
| HFCD_DO_ACTION
);
989 spin_unlock_irqrestore(&cs
->lock
, flags
);
991 case (HW_DEACTIVATE
| REQUEST
):
992 spin_lock_irqsave(&cs
->lock
, flags
);
993 cs
->hw
.hfcD
.mst_m
&= ~HFCD_MASTER
;
994 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
995 spin_unlock_irqrestore(&cs
->lock
, flags
);
997 case (HW_INFO3
| REQUEST
):
998 spin_lock_irqsave(&cs
->lock
, flags
);
999 cs
->hw
.hfcD
.mst_m
|= HFCD_MASTER
;
1000 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
1001 spin_unlock_irqrestore(&cs
->lock
, flags
);
1004 if (cs
->debug
& L1_DEB_WARN
)
1005 debugl1(cs
, "hfcd_l1hw unknown pr %4x", pr
);
1011 setstack_hfcd(struct PStack
*st
, struct IsdnCardState
*cs
)
1013 st
->l1
.l1hw
= HFCD_l1hw
;
1017 hfc_dbusy_timer(struct IsdnCardState
*cs
)
1022 *init_send_hfcd(int cnt
)
1027 if (!(send
= kmalloc(cnt
* sizeof(unsigned int), GFP_ATOMIC
))) {
1029 "HiSax: No memory for hfcd.send\n");
1032 for (i
= 0; i
< cnt
; i
++)
1038 init2bds0(struct IsdnCardState
*cs
)
1040 cs
->setstack_d
= setstack_hfcd
;
1041 if (!cs
->hw
.hfcD
.send
)
1042 cs
->hw
.hfcD
.send
= init_send_hfcd(16);
1043 if (!cs
->bcs
[0].hw
.hfc
.send
)
1044 cs
->bcs
[0].hw
.hfc
.send
= init_send_hfcd(32);
1045 if (!cs
->bcs
[1].hw
.hfc
.send
)
1046 cs
->bcs
[1].hw
.hfc
.send
= init_send_hfcd(32);
1047 cs
->BC_Send_Data
= &hfc_send_data
;
1048 cs
->bcs
[0].BC_SetStack
= setstack_2b
;
1049 cs
->bcs
[1].BC_SetStack
= setstack_2b
;
1050 cs
->bcs
[0].BC_Close
= close_2bs0
;
1051 cs
->bcs
[1].BC_Close
= close_2bs0
;
1052 mode_2bs0(cs
->bcs
, 0, 0);
1053 mode_2bs0(cs
->bcs
+ 1, 0, 1);
1057 release2bds0(struct IsdnCardState
*cs
)
1059 kfree(cs
->bcs
[0].hw
.hfc
.send
);
1060 cs
->bcs
[0].hw
.hfc
.send
= NULL
;
1061 kfree(cs
->bcs
[1].hw
.hfc
.send
);
1062 cs
->bcs
[1].hw
.hfc
.send
= NULL
;
1063 kfree(cs
->hw
.hfcD
.send
);
1064 cs
->hw
.hfcD
.send
= NULL
;
1068 set_cs_func(struct IsdnCardState
*cs
)
1070 cs
->readisac
= &readreghfcd
;
1071 cs
->writeisac
= &writereghfcd
;
1072 cs
->readisacfifo
= &dummyf
;
1073 cs
->writeisacfifo
= &dummyf
;
1074 cs
->BC_Read_Reg
= &ReadReg
;
1075 cs
->BC_Write_Reg
= &WriteReg
;
1076 setup_timer(&cs
->dbusytimer
, (void *)hfc_dbusy_timer
, (long)cs
);
1077 INIT_WORK(&cs
->tqueue
, hfcd_bh
);