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1 /* $Id: icc.c,v 1.8.2.3 2004/01/13 14:31:25 keil Exp $
3 * ICC specific routines
5 * Author Matt Henderson & Guy Ellis
6 * Copyright by Traverse Technologies Pty Ltd, www.travers.com.au
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
11 * 1999.6.25 Initial implementation of routines for Siemens ISDN
12 * Communication Controller PEB 2070 based on the ISAC routines
13 * written by Karsten Keil.
17 #include <linux/init.h>
20 // #include "arcofi.h"
22 #include <linux/interrupt.h>
23 #include <linux/slab.h>
25 #define DBUSY_TIMER_VALUE 80
28 static char *ICCVer
[] =
29 {"2070 A1/A3", "2070 B1", "2070 B2/B3", "2070 V2.4"};
32 ICCVersion(struct IsdnCardState
*cs
, char *s
)
36 val
= cs
->readisac(cs
, ICC_RBCH
);
37 printk(KERN_INFO
"%s ICC version (%x): %s\n", s
, val
, ICCVer
[(val
>> 5) & 3]);
41 ph_command(struct IsdnCardState
*cs
, unsigned int command
)
43 if (cs
->debug
& L1_DEB_ISAC
)
44 debugl1(cs
, "ph_command %x", command
);
45 cs
->writeisac(cs
, ICC_CIX0
, (command
<< 2) | 3);
50 icc_new_ph(struct IsdnCardState
*cs
)
52 switch (cs
->dc
.icc
.ph_state
) {
54 ph_command(cs
, ICC_CMD_DI
);
55 l1_msg(cs
, HW_RESET
| INDICATION
, NULL
);
58 l1_msg(cs
, HW_DEACTIVATE
| CONFIRM
, NULL
);
61 l1_msg(cs
, HW_DEACTIVATE
| INDICATION
, NULL
);
64 l1_msg(cs
, HW_POWERUP
| CONFIRM
, NULL
);
67 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
70 l1_msg(cs
, HW_INFO2
| INDICATION
, NULL
);
73 l1_msg(cs
, HW_INFO4
| INDICATION
, NULL
);
81 icc_bh(struct work_struct
*work
)
83 struct IsdnCardState
*cs
=
84 container_of(work
, struct IsdnCardState
, tqueue
);
87 if (test_and_clear_bit(D_CLEARBUSY
, &cs
->event
)) {
89 debugl1(cs
, "D-Channel Busy cleared");
91 while (stptr
!= NULL
) {
92 stptr
->l1
.l1l2(stptr
, PH_PAUSE
| CONFIRM
, NULL
);
96 if (test_and_clear_bit(D_L1STATECHANGE
, &cs
->event
))
98 if (test_and_clear_bit(D_RCVBUFREADY
, &cs
->event
))
99 DChannel_proc_rcv(cs
);
100 if (test_and_clear_bit(D_XMTBUFREADY
, &cs
->event
))
101 DChannel_proc_xmt(cs
);
103 if (!test_bit(HW_ARCOFI
, &cs
->HW_Flags
))
105 if (test_and_clear_bit(D_RX_MON1
, &cs
->event
))
106 arcofi_fsm(cs
, ARCOFI_RX_END
, NULL
);
107 if (test_and_clear_bit(D_TX_MON1
, &cs
->event
))
108 arcofi_fsm(cs
, ARCOFI_TX_END
, NULL
);
113 icc_empty_fifo(struct IsdnCardState
*cs
, int count
)
117 if ((cs
->debug
& L1_DEB_ISAC
) && !(cs
->debug
& L1_DEB_ISAC_FIFO
))
118 debugl1(cs
, "icc_empty_fifo");
120 if ((cs
->rcvidx
+ count
) >= MAX_DFRAME_LEN_L1
) {
121 if (cs
->debug
& L1_DEB_WARN
)
122 debugl1(cs
, "icc_empty_fifo overrun %d",
124 cs
->writeisac(cs
, ICC_CMDR
, 0x80);
128 ptr
= cs
->rcvbuf
+ cs
->rcvidx
;
130 cs
->readisacfifo(cs
, ptr
, count
);
131 cs
->writeisac(cs
, ICC_CMDR
, 0x80);
132 if (cs
->debug
& L1_DEB_ISAC_FIFO
) {
135 t
+= sprintf(t
, "icc_empty_fifo cnt %d", count
);
136 QuickHex(t
, ptr
, count
);
137 debugl1(cs
, "%s", cs
->dlog
);
142 icc_fill_fifo(struct IsdnCardState
*cs
)
147 if ((cs
->debug
& L1_DEB_ISAC
) && !(cs
->debug
& L1_DEB_ISAC_FIFO
))
148 debugl1(cs
, "icc_fill_fifo");
153 count
= cs
->tx_skb
->len
;
162 ptr
= cs
->tx_skb
->data
;
163 skb_pull(cs
->tx_skb
, count
);
165 cs
->writeisacfifo(cs
, ptr
, count
);
166 cs
->writeisac(cs
, ICC_CMDR
, more
? 0x8 : 0xa);
167 if (test_and_set_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
)) {
168 debugl1(cs
, "icc_fill_fifo dbusytimer running");
169 del_timer(&cs
->dbusytimer
);
171 init_timer(&cs
->dbusytimer
);
172 cs
->dbusytimer
.expires
= jiffies
+ ((DBUSY_TIMER_VALUE
* HZ
)/1000);
173 add_timer(&cs
->dbusytimer
);
174 if (cs
->debug
& L1_DEB_ISAC_FIFO
) {
177 t
+= sprintf(t
, "icc_fill_fifo cnt %d", count
);
178 QuickHex(t
, ptr
, count
);
179 debugl1(cs
, "%s", cs
->dlog
);
184 icc_interrupt(struct IsdnCardState
*cs
, u_char val
)
190 if (cs
->debug
& L1_DEB_ISAC
)
191 debugl1(cs
, "ICC interrupt %x", val
);
192 if (val
& 0x80) { /* RME */
193 exval
= cs
->readisac(cs
, ICC_RSTA
);
194 if ((exval
& 0x70) != 0x20) {
196 if (cs
->debug
& L1_DEB_WARN
)
197 debugl1(cs
, "ICC RDO");
198 #ifdef ERROR_STATISTIC
202 if (!(exval
& 0x20)) {
203 if (cs
->debug
& L1_DEB_WARN
)
204 debugl1(cs
, "ICC CRC error");
205 #ifdef ERROR_STATISTIC
209 cs
->writeisac(cs
, ICC_CMDR
, 0x80);
211 count
= cs
->readisac(cs
, ICC_RBCL
) & 0x1f;
214 icc_empty_fifo(cs
, count
);
215 if ((count
= cs
->rcvidx
) > 0) {
217 if (!(skb
= alloc_skb(count
, GFP_ATOMIC
)))
218 printk(KERN_WARNING
"HiSax: D receive out of memory\n");
220 skb_put_data(skb
, cs
->rcvbuf
, count
);
221 skb_queue_tail(&cs
->rq
, skb
);
226 schedule_event(cs
, D_RCVBUFREADY
);
228 if (val
& 0x40) { /* RPF */
229 icc_empty_fifo(cs
, 32);
231 if (val
& 0x20) { /* RSC */
233 if (cs
->debug
& L1_DEB_WARN
)
234 debugl1(cs
, "ICC RSC interrupt");
236 if (val
& 0x10) { /* XPR */
237 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
238 del_timer(&cs
->dbusytimer
);
239 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
240 schedule_event(cs
, D_CLEARBUSY
);
242 if (cs
->tx_skb
->len
) {
246 dev_kfree_skb_irq(cs
->tx_skb
);
251 if ((cs
->tx_skb
= skb_dequeue(&cs
->sq
))) {
255 schedule_event(cs
, D_XMTBUFREADY
);
258 if (val
& 0x04) { /* CISQ */
259 exval
= cs
->readisac(cs
, ICC_CIR0
);
260 if (cs
->debug
& L1_DEB_ISAC
)
261 debugl1(cs
, "ICC CIR0 %02X", exval
);
263 cs
->dc
.icc
.ph_state
= (exval
>> 2) & 0xf;
264 if (cs
->debug
& L1_DEB_ISAC
)
265 debugl1(cs
, "ph_state change %x", cs
->dc
.icc
.ph_state
);
266 schedule_event(cs
, D_L1STATECHANGE
);
269 exval
= cs
->readisac(cs
, ICC_CIR1
);
270 if (cs
->debug
& L1_DEB_ISAC
)
271 debugl1(cs
, "ICC CIR1 %02X", exval
);
274 if (val
& 0x02) { /* SIN */
276 if (cs
->debug
& L1_DEB_WARN
)
277 debugl1(cs
, "ICC SIN interrupt");
279 if (val
& 0x01) { /* EXI */
280 exval
= cs
->readisac(cs
, ICC_EXIR
);
281 if (cs
->debug
& L1_DEB_WARN
)
282 debugl1(cs
, "ICC EXIR %02x", exval
);
283 if (exval
& 0x80) { /* XMR */
284 debugl1(cs
, "ICC XMR");
285 printk(KERN_WARNING
"HiSax: ICC XMR\n");
287 if (exval
& 0x40) { /* XDU */
288 debugl1(cs
, "ICC XDU");
289 printk(KERN_WARNING
"HiSax: ICC XDU\n");
290 #ifdef ERROR_STATISTIC
293 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
294 del_timer(&cs
->dbusytimer
);
295 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
296 schedule_event(cs
, D_CLEARBUSY
);
297 if (cs
->tx_skb
) { /* Restart frame */
298 skb_push(cs
->tx_skb
, cs
->tx_cnt
);
302 printk(KERN_WARNING
"HiSax: ICC XDU no skb\n");
303 debugl1(cs
, "ICC XDU no skb");
306 if (exval
& 0x04) { /* MOS */
307 v1
= cs
->readisac(cs
, ICC_MOSR
);
308 if (cs
->debug
& L1_DEB_MONITOR
)
309 debugl1(cs
, "ICC MOSR %02x", v1
);
312 if (!cs
->dc
.icc
.mon_rx
) {
313 if (!(cs
->dc
.icc
.mon_rx
= kmalloc(MAX_MON_FRAME
, GFP_ATOMIC
))) {
314 if (cs
->debug
& L1_DEB_WARN
)
315 debugl1(cs
, "ICC MON RX out of memory!");
316 cs
->dc
.icc
.mocr
&= 0xf0;
317 cs
->dc
.icc
.mocr
|= 0x0a;
318 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
321 cs
->dc
.icc
.mon_rxp
= 0;
323 if (cs
->dc
.icc
.mon_rxp
>= MAX_MON_FRAME
) {
324 cs
->dc
.icc
.mocr
&= 0xf0;
325 cs
->dc
.icc
.mocr
|= 0x0a;
326 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
327 cs
->dc
.icc
.mon_rxp
= 0;
328 if (cs
->debug
& L1_DEB_WARN
)
329 debugl1(cs
, "ICC MON RX overflow!");
332 cs
->dc
.icc
.mon_rx
[cs
->dc
.icc
.mon_rxp
++] = cs
->readisac(cs
, ICC_MOR0
);
333 if (cs
->debug
& L1_DEB_MONITOR
)
334 debugl1(cs
, "ICC MOR0 %02x", cs
->dc
.icc
.mon_rx
[cs
->dc
.icc
.mon_rxp
- 1]);
335 if (cs
->dc
.icc
.mon_rxp
== 1) {
336 cs
->dc
.icc
.mocr
|= 0x04;
337 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
342 if (!cs
->dc
.icc
.mon_rx
) {
343 if (!(cs
->dc
.icc
.mon_rx
= kmalloc(MAX_MON_FRAME
, GFP_ATOMIC
))) {
344 if (cs
->debug
& L1_DEB_WARN
)
345 debugl1(cs
, "ICC MON RX out of memory!");
346 cs
->dc
.icc
.mocr
&= 0x0f;
347 cs
->dc
.icc
.mocr
|= 0xa0;
348 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
351 cs
->dc
.icc
.mon_rxp
= 0;
353 if (cs
->dc
.icc
.mon_rxp
>= MAX_MON_FRAME
) {
354 cs
->dc
.icc
.mocr
&= 0x0f;
355 cs
->dc
.icc
.mocr
|= 0xa0;
356 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
357 cs
->dc
.icc
.mon_rxp
= 0;
358 if (cs
->debug
& L1_DEB_WARN
)
359 debugl1(cs
, "ICC MON RX overflow!");
362 cs
->dc
.icc
.mon_rx
[cs
->dc
.icc
.mon_rxp
++] = cs
->readisac(cs
, ICC_MOR1
);
363 if (cs
->debug
& L1_DEB_MONITOR
)
364 debugl1(cs
, "ICC MOR1 %02x", cs
->dc
.icc
.mon_rx
[cs
->dc
.icc
.mon_rxp
- 1]);
365 cs
->dc
.icc
.mocr
|= 0x40;
366 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
370 cs
->dc
.icc
.mocr
&= 0xf0;
371 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
372 cs
->dc
.icc
.mocr
|= 0x0a;
373 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
374 schedule_event(cs
, D_RX_MON0
);
377 cs
->dc
.icc
.mocr
&= 0x0f;
378 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
379 cs
->dc
.icc
.mocr
|= 0xa0;
380 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
381 schedule_event(cs
, D_RX_MON1
);
384 if ((!cs
->dc
.icc
.mon_tx
) || (cs
->dc
.icc
.mon_txc
&&
385 (cs
->dc
.icc
.mon_txp
>= cs
->dc
.icc
.mon_txc
) &&
387 cs
->dc
.icc
.mocr
&= 0xf0;
388 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
389 cs
->dc
.icc
.mocr
|= 0x0a;
390 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
391 if (cs
->dc
.icc
.mon_txc
&&
392 (cs
->dc
.icc
.mon_txp
>= cs
->dc
.icc
.mon_txc
))
393 schedule_event(cs
, D_TX_MON0
);
396 if (cs
->dc
.icc
.mon_txc
&& (cs
->dc
.icc
.mon_txp
>= cs
->dc
.icc
.mon_txc
)) {
397 schedule_event(cs
, D_TX_MON0
);
400 cs
->writeisac(cs
, ICC_MOX0
,
401 cs
->dc
.icc
.mon_tx
[cs
->dc
.icc
.mon_txp
++]);
402 if (cs
->debug
& L1_DEB_MONITOR
)
403 debugl1(cs
, "ICC %02x -> MOX0", cs
->dc
.icc
.mon_tx
[cs
->dc
.icc
.mon_txp
- 1]);
407 if ((!cs
->dc
.icc
.mon_tx
) || (cs
->dc
.icc
.mon_txc
&&
408 (cs
->dc
.icc
.mon_txp
>= cs
->dc
.icc
.mon_txc
) &&
410 cs
->dc
.icc
.mocr
&= 0x0f;
411 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
412 cs
->dc
.icc
.mocr
|= 0xa0;
413 cs
->writeisac(cs
, ICC_MOCR
, cs
->dc
.icc
.mocr
);
414 if (cs
->dc
.icc
.mon_txc
&&
415 (cs
->dc
.icc
.mon_txp
>= cs
->dc
.icc
.mon_txc
))
416 schedule_event(cs
, D_TX_MON1
);
419 if (cs
->dc
.icc
.mon_txc
&& (cs
->dc
.icc
.mon_txp
>= cs
->dc
.icc
.mon_txc
)) {
420 schedule_event(cs
, D_TX_MON1
);
423 cs
->writeisac(cs
, ICC_MOX1
,
424 cs
->dc
.icc
.mon_tx
[cs
->dc
.icc
.mon_txp
++]);
425 if (cs
->debug
& L1_DEB_MONITOR
)
426 debugl1(cs
, "ICC %02x -> MOX1", cs
->dc
.icc
.mon_tx
[cs
->dc
.icc
.mon_txp
- 1]);
435 ICC_l1hw(struct PStack
*st
, int pr
, void *arg
)
437 struct IsdnCardState
*cs
= (struct IsdnCardState
*) st
->l1
.hardware
;
438 struct sk_buff
*skb
= arg
;
443 case (PH_DATA
| REQUEST
):
444 if (cs
->debug
& DEB_DLOG_HEX
)
445 LogFrame(cs
, skb
->data
, skb
->len
);
446 if (cs
->debug
& DEB_DLOG_VERBOSE
)
447 dlogframe(cs
, skb
, 0);
448 spin_lock_irqsave(&cs
->lock
, flags
);
450 skb_queue_tail(&cs
->sq
, skb
);
451 #ifdef L2FRAME_DEBUG /* psa */
452 if (cs
->debug
& L1_DEB_LAPD
)
453 Logl2Frame(cs
, skb
, "PH_DATA Queued", 0);
458 #ifdef L2FRAME_DEBUG /* psa */
459 if (cs
->debug
& L1_DEB_LAPD
)
460 Logl2Frame(cs
, skb
, "PH_DATA", 0);
464 spin_unlock_irqrestore(&cs
->lock
, flags
);
466 case (PH_PULL
| INDICATION
):
467 spin_lock_irqsave(&cs
->lock
, flags
);
469 if (cs
->debug
& L1_DEB_WARN
)
470 debugl1(cs
, " l2l1 tx_skb exist this shouldn't happen");
471 skb_queue_tail(&cs
->sq
, skb
);
472 spin_unlock_irqrestore(&cs
->lock
, flags
);
475 if (cs
->debug
& DEB_DLOG_HEX
)
476 LogFrame(cs
, skb
->data
, skb
->len
);
477 if (cs
->debug
& DEB_DLOG_VERBOSE
)
478 dlogframe(cs
, skb
, 0);
481 #ifdef L2FRAME_DEBUG /* psa */
482 if (cs
->debug
& L1_DEB_LAPD
)
483 Logl2Frame(cs
, skb
, "PH_DATA_PULLED", 0);
486 spin_unlock_irqrestore(&cs
->lock
, flags
);
488 case (PH_PULL
| REQUEST
):
489 #ifdef L2FRAME_DEBUG /* psa */
490 if (cs
->debug
& L1_DEB_LAPD
)
491 debugl1(cs
, "-> PH_REQUEST_PULL");
494 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
495 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
497 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
499 case (HW_RESET
| REQUEST
):
500 spin_lock_irqsave(&cs
->lock
, flags
);
501 if ((cs
->dc
.icc
.ph_state
== ICC_IND_EI1
) ||
502 (cs
->dc
.icc
.ph_state
== ICC_IND_DR
))
503 ph_command(cs
, ICC_CMD_DI
);
505 ph_command(cs
, ICC_CMD_RES
);
506 spin_unlock_irqrestore(&cs
->lock
, flags
);
508 case (HW_ENABLE
| REQUEST
):
509 spin_lock_irqsave(&cs
->lock
, flags
);
510 ph_command(cs
, ICC_CMD_DI
);
511 spin_unlock_irqrestore(&cs
->lock
, flags
);
513 case (HW_INFO1
| REQUEST
):
514 spin_lock_irqsave(&cs
->lock
, flags
);
515 ph_command(cs
, ICC_CMD_AR
);
516 spin_unlock_irqrestore(&cs
->lock
, flags
);
518 case (HW_INFO3
| REQUEST
):
519 spin_lock_irqsave(&cs
->lock
, flags
);
520 ph_command(cs
, ICC_CMD_AI
);
521 spin_unlock_irqrestore(&cs
->lock
, flags
);
523 case (HW_TESTLOOP
| REQUEST
):
524 spin_lock_irqsave(&cs
->lock
, flags
);
530 if (test_bit(HW_IOM1
, &cs
->HW_Flags
)) {
533 cs
->writeisac(cs
, ICC_SPCR
, 0xa);
534 cs
->writeisac(cs
, ICC_ADF1
, 0x2);
536 cs
->writeisac(cs
, ICC_SPCR
, val
);
537 cs
->writeisac(cs
, ICC_ADF1
, 0xa);
541 cs
->writeisac(cs
, ICC_SPCR
, val
);
543 cs
->writeisac(cs
, ICC_ADF1
, 0x8);
545 cs
->writeisac(cs
, ICC_ADF1
, 0x0);
547 spin_unlock_irqrestore(&cs
->lock
, flags
);
549 case (HW_DEACTIVATE
| RESPONSE
):
550 skb_queue_purge(&cs
->rq
);
551 skb_queue_purge(&cs
->sq
);
553 dev_kfree_skb_any(cs
->tx_skb
);
556 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
557 del_timer(&cs
->dbusytimer
);
558 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
559 schedule_event(cs
, D_CLEARBUSY
);
562 if (cs
->debug
& L1_DEB_WARN
)
563 debugl1(cs
, "icc_l1hw unknown %04x", pr
);
569 setstack_icc(struct PStack
*st
, struct IsdnCardState
*cs
)
571 st
->l1
.l1hw
= ICC_l1hw
;
575 DC_Close_icc(struct IsdnCardState
*cs
) {
576 kfree(cs
->dc
.icc
.mon_rx
);
577 cs
->dc
.icc
.mon_rx
= NULL
;
578 kfree(cs
->dc
.icc
.mon_tx
);
579 cs
->dc
.icc
.mon_tx
= NULL
;
583 dbusy_timer_handler(struct IsdnCardState
*cs
)
585 struct PStack
*stptr
;
588 if (test_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
)) {
589 rbch
= cs
->readisac(cs
, ICC_RBCH
);
590 star
= cs
->readisac(cs
, ICC_STAR
);
592 debugl1(cs
, "D-Channel Busy RBCH %02x STAR %02x",
594 if (rbch
& ICC_RBCH_XAC
) { /* D-Channel Busy */
595 test_and_set_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
);
597 while (stptr
!= NULL
) {
598 stptr
->l1
.l1l2(stptr
, PH_PAUSE
| INDICATION
, NULL
);
602 /* discard frame; reset transceiver */
603 test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
);
605 dev_kfree_skb_any(cs
->tx_skb
);
609 printk(KERN_WARNING
"HiSax: ICC D-Channel Busy no skb\n");
610 debugl1(cs
, "D-Channel Busy no skb");
612 cs
->writeisac(cs
, ICC_CMDR
, 0x01); /* Transmitter reset */
613 cs
->irq_func(cs
->irq
, cs
);
619 initicc(struct IsdnCardState
*cs
)
621 cs
->setstack_d
= setstack_icc
;
622 cs
->DC_Close
= DC_Close_icc
;
623 cs
->dc
.icc
.mon_tx
= NULL
;
624 cs
->dc
.icc
.mon_rx
= NULL
;
625 cs
->writeisac(cs
, ICC_MASK
, 0xff);
626 cs
->dc
.icc
.mocr
= 0xaa;
627 if (test_bit(HW_IOM1
, &cs
->HW_Flags
)) {
629 cs
->writeisac(cs
, ICC_ADF2
, 0x0);
630 cs
->writeisac(cs
, ICC_SPCR
, 0xa);
631 cs
->writeisac(cs
, ICC_ADF1
, 0x2);
632 cs
->writeisac(cs
, ICC_STCR
, 0x70);
633 cs
->writeisac(cs
, ICC_MODE
, 0xc9);
636 if (!cs
->dc
.icc
.adf2
)
637 cs
->dc
.icc
.adf2
= 0x80;
638 cs
->writeisac(cs
, ICC_ADF2
, cs
->dc
.icc
.adf2
);
639 cs
->writeisac(cs
, ICC_SQXR
, 0xa0);
640 cs
->writeisac(cs
, ICC_SPCR
, 0x20);
641 cs
->writeisac(cs
, ICC_STCR
, 0x70);
642 cs
->writeisac(cs
, ICC_MODE
, 0xca);
643 cs
->writeisac(cs
, ICC_TIMR
, 0x00);
644 cs
->writeisac(cs
, ICC_ADF1
, 0x20);
646 ph_command(cs
, ICC_CMD_RES
);
647 cs
->writeisac(cs
, ICC_MASK
, 0x0);
648 ph_command(cs
, ICC_CMD_DI
);
652 clear_pending_icc_ints(struct IsdnCardState
*cs
)
656 val
= cs
->readisac(cs
, ICC_STAR
);
657 debugl1(cs
, "ICC STAR %x", val
);
658 val
= cs
->readisac(cs
, ICC_MODE
);
659 debugl1(cs
, "ICC MODE %x", val
);
660 val
= cs
->readisac(cs
, ICC_ADF2
);
661 debugl1(cs
, "ICC ADF2 %x", val
);
662 val
= cs
->readisac(cs
, ICC_ISTA
);
663 debugl1(cs
, "ICC ISTA %x", val
);
665 eval
= cs
->readisac(cs
, ICC_EXIR
);
666 debugl1(cs
, "ICC EXIR %x", eval
);
668 val
= cs
->readisac(cs
, ICC_CIR0
);
669 debugl1(cs
, "ICC CIR0 %x", val
);
670 cs
->dc
.icc
.ph_state
= (val
>> 2) & 0xf;
671 schedule_event(cs
, D_L1STATECHANGE
);
672 /* Disable all IRQ */
673 cs
->writeisac(cs
, ICC_MASK
, 0xFF);
676 void setup_icc(struct IsdnCardState
*cs
)
678 INIT_WORK(&cs
->tqueue
, icc_bh
);
679 setup_timer(&cs
->dbusytimer
, (void *)dbusy_timer_handler
, (long)cs
);