]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/isdn/hisax/jade.c
1 /* $Id: jade.c,v 1.9.2.4 2004/01/14 16:04:48 keil Exp $
3 * JADE stuff (derived from original hscx.c)
5 * Author Roland Klabunde
6 * Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
14 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
24 JadeVersion(struct IsdnCardState
*cs
, char *s
)
28 cs
->BC_Write_Reg(cs
, -1, 0x50, 0x19);
31 ver
= cs
->BC_Read_Reg(cs
, -1, 0x60);
36 printk(KERN_INFO
"%s JADE version not obtainable\n", s
);
40 /* Wait for the JADE */
43 ver
= cs
->BC_Read_Reg(cs
, -1, 0x60);
44 printk(KERN_INFO
"%s JADE version: %d\n", s
, ver
);
48 /* Write to indirect accessible jade register set */
50 jade_write_indirect(struct IsdnCardState
*cs
, u_char reg
, u_char value
)
56 cs
->BC_Write_Reg(cs
, -1, COMM_JADE
+ 1, value
);
57 /* Say JADE we wanna write indirect reg 'reg' */
58 cs
->BC_Write_Reg(cs
, -1, COMM_JADE
, reg
);
60 /* Wait for RDY goes high */
63 ret
= cs
->BC_Read_Reg(cs
, -1, COMM_JADE
);
69 printk(KERN_INFO
"Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg
, value
);
78 modejade(struct BCState
*bcs
, int mode
, int bc
)
80 struct IsdnCardState
*cs
= bcs
->cs
;
81 int jade
= bcs
->hw
.hscx
.hscx
;
83 if (cs
->debug
& L1_DEB_HSCX
) {
84 debugl1(cs
, "jade %c mode %d ichan %d", 'A' + jade
, mode
, bc
);
89 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_MODE
, (mode
== L1_MODE_TRANS
? jadeMODE_TMO
: 0x00));
90 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_CCR0
, (jadeCCR0_PU
| jadeCCR0_ITF
));
91 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_CCR1
, 0x00);
93 jade_write_indirect(cs
, jade_HDLC1SERRXPATH
, 0x08);
94 jade_write_indirect(cs
, jade_HDLC2SERRXPATH
, 0x08);
95 jade_write_indirect(cs
, jade_HDLC1SERTXPATH
, 0x00);
96 jade_write_indirect(cs
, jade_HDLC2SERTXPATH
, 0x00);
98 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_XCCR
, 0x07);
99 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_RCCR
, 0x07);
102 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_TSAX
, 0x00);
103 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_TSAR
, 0x00);
105 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_TSAX
, 0x04);
106 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_TSAR
, 0x04);
110 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_MODE
, jadeMODE_TMO
);
112 case (L1_MODE_TRANS
):
113 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_MODE
, (jadeMODE_TMO
| jadeMODE_RAC
| jadeMODE_XAC
));
116 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_MODE
, (jadeMODE_RAC
| jadeMODE_XAC
));
120 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_RCMD
, (jadeRCMD_RRES
| jadeRCMD_RMC
));
121 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_XCMD
, jadeXCMD_XRES
);
123 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_IMR
, 0xF8);
127 cs
->BC_Write_Reg(cs
, jade
, jade_HDLC_IMR
, 0x00);
131 jade_l2l1(struct PStack
*st
, int pr
, void *arg
)
133 struct BCState
*bcs
= st
->l1
.bcs
;
134 struct sk_buff
*skb
= arg
;
138 case (PH_DATA
| REQUEST
):
139 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
141 skb_queue_tail(&bcs
->squeue
, skb
);
144 test_and_set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
145 bcs
->hw
.hscx
.count
= 0;
146 bcs
->cs
->BC_Send_Data(bcs
);
148 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
150 case (PH_PULL
| INDICATION
):
151 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
153 printk(KERN_WARNING
"jade_l2l1: this shouldn't happen\n");
155 test_and_set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
157 bcs
->hw
.hscx
.count
= 0;
158 bcs
->cs
->BC_Send_Data(bcs
);
160 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
162 case (PH_PULL
| REQUEST
):
164 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
165 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
167 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
169 case (PH_ACTIVATE
| REQUEST
):
170 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
171 test_and_set_bit(BC_FLG_ACTIV
, &bcs
->Flag
);
172 modejade(bcs
, st
->l1
.mode
, st
->l1
.bc
);
173 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
174 l1_msg_b(st
, pr
, arg
);
176 case (PH_DEACTIVATE
| REQUEST
):
177 l1_msg_b(st
, pr
, arg
);
179 case (PH_DEACTIVATE
| CONFIRM
):
180 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
181 test_and_clear_bit(BC_FLG_ACTIV
, &bcs
->Flag
);
182 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
183 modejade(bcs
, 0, st
->l1
.bc
);
184 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
185 st
->l1
.l1l2(st
, PH_DEACTIVATE
| CONFIRM
, NULL
);
191 close_jadestate(struct BCState
*bcs
)
193 modejade(bcs
, 0, bcs
->channel
);
194 if (test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
195 kfree(bcs
->hw
.hscx
.rcvbuf
);
196 bcs
->hw
.hscx
.rcvbuf
= NULL
;
199 skb_queue_purge(&bcs
->rqueue
);
200 skb_queue_purge(&bcs
->squeue
);
202 dev_kfree_skb_any(bcs
->tx_skb
);
204 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
210 open_jadestate(struct IsdnCardState
*cs
, struct BCState
*bcs
)
212 if (!test_and_set_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
213 if (!(bcs
->hw
.hscx
.rcvbuf
= kmalloc(HSCX_BUFMAX
, GFP_ATOMIC
))) {
215 "HiSax: No memory for hscx.rcvbuf\n");
216 test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
);
219 if (!(bcs
->blog
= kmalloc(MAX_BLOG_SPACE
, GFP_ATOMIC
))) {
221 "HiSax: No memory for bcs->blog\n");
222 test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
);
223 kfree(bcs
->hw
.hscx
.rcvbuf
);
224 bcs
->hw
.hscx
.rcvbuf
= NULL
;
227 skb_queue_head_init(&bcs
->rqueue
);
228 skb_queue_head_init(&bcs
->squeue
);
231 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
233 bcs
->hw
.hscx
.rcvidx
= 0;
240 setstack_jade(struct PStack
*st
, struct BCState
*bcs
)
242 bcs
->channel
= st
->l1
.bc
;
243 if (open_jadestate(st
->l1
.hardware
, bcs
))
246 st
->l2
.l2l1
= jade_l2l1
;
247 setstack_manager(st
);
254 clear_pending_jade_ints(struct IsdnCardState
*cs
)
258 cs
->BC_Write_Reg(cs
, 0, jade_HDLC_IMR
, 0x00);
259 cs
->BC_Write_Reg(cs
, 1, jade_HDLC_IMR
, 0x00);
261 val
= cs
->BC_Read_Reg(cs
, 1, jade_HDLC_ISR
);
262 debugl1(cs
, "jade B ISTA %x", val
);
263 val
= cs
->BC_Read_Reg(cs
, 0, jade_HDLC_ISR
);
264 debugl1(cs
, "jade A ISTA %x", val
);
265 val
= cs
->BC_Read_Reg(cs
, 1, jade_HDLC_STAR
);
266 debugl1(cs
, "jade B STAR %x", val
);
267 val
= cs
->BC_Read_Reg(cs
, 0, jade_HDLC_STAR
);
268 debugl1(cs
, "jade A STAR %x", val
);
270 cs
->BC_Write_Reg(cs
, 0, jade_HDLC_IMR
, 0xF8);
271 cs
->BC_Write_Reg(cs
, 1, jade_HDLC_IMR
, 0xF8);
275 initjade(struct IsdnCardState
*cs
)
277 cs
->bcs
[0].BC_SetStack
= setstack_jade
;
278 cs
->bcs
[1].BC_SetStack
= setstack_jade
;
279 cs
->bcs
[0].BC_Close
= close_jadestate
;
280 cs
->bcs
[1].BC_Close
= close_jadestate
;
281 cs
->bcs
[0].hw
.hscx
.hscx
= 0;
282 cs
->bcs
[1].hw
.hscx
.hscx
= 1;
284 /* Stop DSP audio tx/rx */
285 jade_write_indirect(cs
, 0x11, 0x0f);
286 jade_write_indirect(cs
, 0x17, 0x2f);
288 /* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */
289 cs
->BC_Write_Reg(cs
, 0, jade_HDLC_MODE
, jadeMODE_TMO
);
290 cs
->BC_Write_Reg(cs
, 1, jade_HDLC_MODE
, jadeMODE_TMO
);
291 /* Power down, 1-Idle, RxTx least significant bit first */
292 cs
->BC_Write_Reg(cs
, 0, jade_HDLC_CCR0
, 0x00);
293 cs
->BC_Write_Reg(cs
, 1, jade_HDLC_CCR0
, 0x00);
294 /* Mask all interrupts */
295 cs
->BC_Write_Reg(cs
, 0, jade_HDLC_IMR
, 0x00);
296 cs
->BC_Write_Reg(cs
, 1, jade_HDLC_IMR
, 0x00);
297 /* Setup host access to hdlc controller */
298 jade_write_indirect(cs
, jade_HDLCCNTRACCESS
, (jadeINDIRECT_HAH1
| jadeINDIRECT_HAH2
));
299 /* Unmask HDLC int (don't forget DSP int later on)*/
300 cs
->BC_Write_Reg(cs
, -1, jade_INT
, (jadeINT_HDLC1
| jadeINT_HDLC2
));
302 /* once again TRANSPARENT */
303 modejade(cs
->bcs
, 0, 0);
304 modejade(cs
->bcs
+ 1, 0, 0);