3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <asm/processor.h>
31 #include <asm/current.h>
32 #include <asm/apicdef.h>
33 #include <asm/atomic.h>
34 #include <asm/div64.h>
42 #define APIC_BUS_CYCLE_NS 1
44 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
45 #define apic_debug(fmt, arg...)
47 #define APIC_LVT_NUM 6
48 /* 14 is the version for Xeon and Pentium 8.4.8*/
49 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
50 #define LAPIC_MMIO_LENGTH (1 << 12)
51 /* followed define is not in apicdef.h */
52 #define APIC_SHORT_MASK 0xc0000
53 #define APIC_DEST_NOSHORT 0x0
54 #define APIC_DEST_MASK 0x800
55 #define MAX_APIC_VECTOR 256
57 #define VEC_POS(v) ((v) & (32 - 1))
58 #define REG_POS(v) (((v) >> 5) << 4)
59 static inline u32
apic_get_reg(struct kvm_lapic
*apic
, int reg_off
)
61 return *((u32
*) (apic
->regs
+ reg_off
));
64 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
66 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
69 static inline int apic_test_and_set_vector(int vec
, void *bitmap
)
71 return test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
74 static inline int apic_test_and_clear_vector(int vec
, void *bitmap
)
76 return test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
79 static inline void apic_set_vector(int vec
, void *bitmap
)
81 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
84 static inline void apic_clear_vector(int vec
, void *bitmap
)
86 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
89 static inline int apic_hw_enabled(struct kvm_lapic
*apic
)
91 return (apic
)->vcpu
->apic_base
& MSR_IA32_APICBASE_ENABLE
;
94 static inline int apic_sw_enabled(struct kvm_lapic
*apic
)
96 return apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_APIC_ENABLED
;
99 static inline int apic_enabled(struct kvm_lapic
*apic
)
101 return apic_sw_enabled(apic
) && apic_hw_enabled(apic
);
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
111 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
113 return (apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
116 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
118 return !(apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
121 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
123 return apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
126 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
128 return apic_get_reg(apic
, APIC_LVTT
) & APIC_LVT_TIMER_PERIODIC
;
131 static unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
132 LVT_MASK
| APIC_LVT_TIMER_PERIODIC
, /* LVTT */
133 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
134 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
135 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
136 LVT_MASK
/* LVTERR */
139 static int find_highest_vector(void *bitmap
)
142 int word_offset
= MAX_APIC_VECTOR
>> 5;
144 while ((word_offset
!= 0) && (word
[(--word_offset
) << 2] == 0))
147 if (likely(!word_offset
&& !word
[0]))
150 return fls(word
[word_offset
<< 2]) - 1 + (word_offset
<< 5);
153 static inline int apic_test_and_set_irr(int vec
, struct kvm_lapic
*apic
)
155 return apic_test_and_set_vector(vec
, apic
->regs
+ APIC_IRR
);
158 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
160 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
163 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
167 result
= find_highest_vector(apic
->regs
+ APIC_IRR
);
168 ASSERT(result
== -1 || result
>= 16);
173 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
175 struct kvm_lapic
*apic
= (struct kvm_lapic
*)vcpu
->apic
;
180 highest_irr
= apic_find_highest_irr(apic
);
184 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr
);
186 int kvm_apic_set_irq(struct kvm_lapic
*apic
, u8 vec
, u8 trig
)
188 if (!apic_test_and_set_irr(vec
, apic
)) {
189 /* a new pending irq is set in IRR */
191 apic_set_vector(vec
, apic
->regs
+ APIC_TMR
);
193 apic_clear_vector(vec
, apic
->regs
+ APIC_TMR
);
194 kvm_vcpu_kick(apic
->vcpu
);
200 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
204 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
205 ASSERT(result
== -1 || result
>= 16);
210 static void apic_update_ppr(struct kvm_lapic
*apic
)
215 tpr
= apic_get_reg(apic
, APIC_TASKPRI
);
216 isr
= apic_find_highest_isr(apic
);
217 isrv
= (isr
!= -1) ? isr
: 0;
219 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
224 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
225 apic
, ppr
, isr
, isrv
);
227 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
230 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
232 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
233 apic_update_ppr(apic
);
236 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u16 dest
)
238 return kvm_apic_id(apic
) == dest
;
241 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u8 mda
)
246 logical_id
= GET_APIC_LOGICAL_ID(apic_get_reg(apic
, APIC_LDR
));
248 switch (apic_get_reg(apic
, APIC_DFR
)) {
250 if (logical_id
& mda
)
253 case APIC_DFR_CLUSTER
:
254 if (((logical_id
>> 4) == (mda
>> 0x4))
255 && (logical_id
& mda
& 0xf))
259 printk(KERN_WARNING
"Bad DFR vcpu %d: %08x\n",
260 apic
->vcpu
->vcpu_id
, apic_get_reg(apic
, APIC_DFR
));
267 static int apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
268 int short_hand
, int dest
, int dest_mode
)
271 struct kvm_lapic
*target
= vcpu
->apic
;
273 apic_debug("target %p, source %p, dest 0x%x, "
274 "dest_mode 0x%x, short_hand 0x%x",
275 target
, source
, dest
, dest_mode
, short_hand
);
278 switch (short_hand
) {
279 case APIC_DEST_NOSHORT
:
280 if (dest_mode
== 0) {
282 if ((dest
== 0xFF) || (dest
== kvm_apic_id(target
)))
286 result
= kvm_apic_match_logical_addr(target
, dest
);
289 if (target
== source
)
292 case APIC_DEST_ALLINC
:
295 case APIC_DEST_ALLBUT
:
296 if (target
!= source
)
300 printk(KERN_WARNING
"Bad dest shorthand value %x\n",
309 * Add a pending IRQ into lapic.
310 * Return 1 if successfully added and 0 if discarded.
312 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
313 int vector
, int level
, int trig_mode
)
318 switch (delivery_mode
) {
321 /* FIXME add logic for vcpu on reset */
322 if (unlikely(!apic_enabled(apic
)))
325 orig_irr
= apic_test_and_set_irr(vector
, apic
);
326 if (orig_irr
&& trig_mode
) {
327 apic_debug("level trig mode repeatedly for vector %d",
333 apic_debug("level trig mode for vector %d", vector
);
334 apic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
336 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
338 kvm_vcpu_kick(apic
->vcpu
);
340 result
= (orig_irr
== 0);
344 printk(KERN_DEBUG
"Ignoring delivery mode 3\n");
348 printk(KERN_DEBUG
"Ignoring guest SMI\n");
351 printk(KERN_DEBUG
"Ignoring guest NMI\n");
355 printk(KERN_DEBUG
"Ignoring guest INIT\n");
358 case APIC_DM_STARTUP
:
359 printk(KERN_DEBUG
"Ignoring guest STARTUP\n");
363 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
370 struct kvm_lapic
*kvm_apic_round_robin(struct kvm
*kvm
, u8 vector
,
371 unsigned long bitmap
)
376 struct kvm_lapic
*apic
;
378 last
= kvm
->round_robin_prev_vcpu
;
382 if (++next
== KVM_MAX_VCPUS
)
384 if (kvm
->vcpus
[next
] == NULL
|| !test_bit(next
, &bitmap
))
386 apic
= kvm
->vcpus
[next
]->apic
;
387 if (apic
&& apic_enabled(apic
))
390 } while (next
!= last
);
391 kvm
->round_robin_prev_vcpu
= next
;
394 vcpu_id
= ffs(bitmap
) - 1;
397 printk(KERN_DEBUG
"vcpu not ready for apic_round_robin\n");
399 apic
= kvm
->vcpus
[vcpu_id
]->apic
;
405 static void apic_set_eoi(struct kvm_lapic
*apic
)
407 int vector
= apic_find_highest_isr(apic
);
410 * Not every write EOI will has corresponding ISR,
411 * one example is when Kernel check timer on setup_IO_APIC
416 apic_clear_vector(vector
, apic
->regs
+ APIC_ISR
);
417 apic_update_ppr(apic
);
419 if (apic_test_and_clear_vector(vector
, apic
->regs
+ APIC_TMR
))
420 kvm_ioapic_update_eoi(apic
->vcpu
->kvm
, vector
);
423 static void apic_send_ipi(struct kvm_lapic
*apic
)
425 u32 icr_low
= apic_get_reg(apic
, APIC_ICR
);
426 u32 icr_high
= apic_get_reg(apic
, APIC_ICR2
);
428 unsigned int dest
= GET_APIC_DEST_FIELD(icr_high
);
429 unsigned int short_hand
= icr_low
& APIC_SHORT_MASK
;
430 unsigned int trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
431 unsigned int level
= icr_low
& APIC_INT_ASSERT
;
432 unsigned int dest_mode
= icr_low
& APIC_DEST_MASK
;
433 unsigned int delivery_mode
= icr_low
& APIC_MODE_MASK
;
434 unsigned int vector
= icr_low
& APIC_VECTOR_MASK
;
436 struct kvm_lapic
*target
;
437 struct kvm_vcpu
*vcpu
;
438 unsigned long lpr_map
= 0;
441 apic_debug("icr_high 0x%x, icr_low 0x%x, "
442 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
443 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
444 icr_high
, icr_low
, short_hand
, dest
,
445 trig_mode
, level
, dest_mode
, delivery_mode
, vector
);
447 for (i
= 0; i
< KVM_MAX_VCPUS
; i
++) {
448 vcpu
= apic
->vcpu
->kvm
->vcpus
[i
];
453 apic_match_dest(vcpu
, apic
, short_hand
, dest
, dest_mode
)) {
454 if (delivery_mode
== APIC_DM_LOWEST
)
455 set_bit(vcpu
->vcpu_id
, &lpr_map
);
457 __apic_accept_irq(vcpu
->apic
, delivery_mode
,
458 vector
, level
, trig_mode
);
462 if (delivery_mode
== APIC_DM_LOWEST
) {
463 target
= kvm_apic_round_robin(vcpu
->kvm
, vector
, lpr_map
);
465 __apic_accept_irq(target
, delivery_mode
,
466 vector
, level
, trig_mode
);
470 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
473 ktime_t passed
, now
= apic
->timer
.dev
.base
->get_time();
474 u32 tmcct
= apic_get_reg(apic
, APIC_TMICT
);
476 ASSERT(apic
!= NULL
);
478 if (unlikely(ktime_to_ns(now
) <=
479 ktime_to_ns(apic
->timer
.last_update
))) {
481 passed
= ktime_add(( {
484 (apic
->timer
.last_update
).tv64
}; }
486 apic_debug("time elapsed\n");
488 passed
= ktime_sub(now
, apic
->timer
.last_update
);
490 counter_passed
= div64_64(ktime_to_ns(passed
),
491 (APIC_BUS_CYCLE_NS
* apic
->timer
.divide_count
));
492 tmcct
-= counter_passed
;
495 if (unlikely(!apic_lvtt_period(apic
)))
499 tmcct
+= apic_get_reg(apic
, APIC_TMICT
);
500 } while (tmcct
<= 0);
506 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
510 if (offset
>= LAPIC_MMIO_LENGTH
)
515 printk(KERN_WARNING
"Access APIC ARBPRI register "
516 "which is for P6\n");
519 case APIC_TMCCT
: /* Timer CCR */
520 val
= apic_get_tmcct(apic
);
524 apic_update_ppr(apic
);
525 val
= apic_get_reg(apic
, offset
);
532 static void apic_mmio_read(struct kvm_io_device
*this,
533 gpa_t address
, int len
, void *data
)
535 struct kvm_lapic
*apic
= (struct kvm_lapic
*)this->private;
536 unsigned int offset
= address
- apic
->base_address
;
537 unsigned char alignment
= offset
& 0xf;
540 if ((alignment
+ len
) > 4) {
541 printk(KERN_ERR
"KVM_APIC_READ: alignment error %lx %d",
542 (unsigned long)address
, len
);
545 result
= __apic_read(apic
, offset
& ~0xf);
551 memcpy(data
, (char *)&result
+ alignment
, len
);
554 printk(KERN_ERR
"Local APIC read with len = %x, "
555 "should be 1,2, or 4 instead\n", len
);
560 static void update_divide_count(struct kvm_lapic
*apic
)
562 u32 tmp1
, tmp2
, tdcr
;
564 tdcr
= apic_get_reg(apic
, APIC_TDCR
);
566 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
567 apic
->timer
.divide_count
= 0x1 << (tmp2
& 0x7);
569 apic_debug("timer divide count is 0x%x\n",
570 apic
->timer
.divide_count
);
573 static void start_apic_timer(struct kvm_lapic
*apic
)
575 ktime_t now
= apic
->timer
.dev
.base
->get_time();
577 apic
->timer
.last_update
= now
;
579 apic
->timer
.period
= apic_get_reg(apic
, APIC_TMICT
) *
580 APIC_BUS_CYCLE_NS
* apic
->timer
.divide_count
;
581 atomic_set(&apic
->timer
.pending
, 0);
582 hrtimer_start(&apic
->timer
.dev
,
583 ktime_add_ns(now
, apic
->timer
.period
),
586 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
588 "timer initial count 0x%x, period %lldns, "
589 "expire @ 0x%016" PRIx64
".\n", __FUNCTION__
,
590 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
591 apic_get_reg(apic
, APIC_TMICT
),
593 ktime_to_ns(ktime_add_ns(now
,
594 apic
->timer
.period
)));
597 static void apic_mmio_write(struct kvm_io_device
*this,
598 gpa_t address
, int len
, const void *data
)
600 struct kvm_lapic
*apic
= (struct kvm_lapic
*)this->private;
601 unsigned int offset
= address
- apic
->base_address
;
602 unsigned char alignment
= offset
& 0xf;
606 * APIC register must be aligned on 128-bits boundary.
607 * 32/64/128 bits registers must be accessed thru 32 bits.
610 if (len
!= 4 || alignment
) {
611 if (printk_ratelimit())
612 printk(KERN_ERR
"apic write: bad size=%d %lx\n",
619 /* too common printing */
620 if (offset
!= APIC_EOI
)
621 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
622 "0x%x\n", __FUNCTION__
, offset
, len
, val
);
627 case APIC_ID
: /* Local APIC ID */
628 apic_set_reg(apic
, APIC_ID
, val
);
632 apic_set_tpr(apic
, val
& 0xff);
640 apic_set_reg(apic
, APIC_LDR
, val
& APIC_LDR_MASK
);
644 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
648 apic_set_reg(apic
, APIC_SPIV
, val
& 0x3ff);
649 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
653 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
654 lvt_val
= apic_get_reg(apic
,
655 APIC_LVTT
+ 0x10 * i
);
656 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
657 lvt_val
| APIC_LVT_MASKED
);
659 atomic_set(&apic
->timer
.pending
, 0);
665 /* No delay here, so we always clear the pending bit */
666 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
671 apic_set_reg(apic
, APIC_ICR2
, val
& 0xff000000);
680 /* TODO: Check vector */
681 if (!apic_sw_enabled(apic
))
682 val
|= APIC_LVT_MASKED
;
684 val
&= apic_lvt_mask
[(offset
- APIC_LVTT
) >> 4];
685 apic_set_reg(apic
, offset
, val
);
690 hrtimer_cancel(&apic
->timer
.dev
);
691 apic_set_reg(apic
, APIC_TMICT
, val
);
692 start_apic_timer(apic
);
697 printk(KERN_ERR
"KVM_WRITE:TDCR %x\n", val
);
698 apic_set_reg(apic
, APIC_TDCR
, val
);
699 update_divide_count(apic
);
703 apic_debug("Local APIC Write to read-only register %x\n",
710 static int apic_mmio_range(struct kvm_io_device
*this, gpa_t addr
)
712 struct kvm_lapic
*apic
= (struct kvm_lapic
*)this->private;
716 if (apic_hw_enabled(apic
) &&
717 (addr
>= apic
->base_address
) &&
718 (addr
< (apic
->base_address
+ LAPIC_MMIO_LENGTH
)))
724 void kvm_free_apic(struct kvm_lapic
*apic
)
729 hrtimer_cancel(&apic
->timer
.dev
);
731 if (apic
->regs_page
) {
732 __free_page(apic
->regs_page
);
740 *----------------------------------------------------------------------
742 *----------------------------------------------------------------------
745 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
747 struct kvm_lapic
*apic
= (struct kvm_lapic
*)vcpu
->apic
;
751 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4));
754 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
756 struct kvm_lapic
*apic
= (struct kvm_lapic
*)vcpu
->apic
;
761 tpr
= (u64
) apic_get_reg(apic
, APIC_TASKPRI
);
763 return (tpr
& 0xf0) >> 4;
765 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8
);
767 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
769 struct kvm_lapic
*apic
= (struct kvm_lapic
*)vcpu
->apic
;
772 value
|= MSR_IA32_APICBASE_BSP
;
773 vcpu
->apic_base
= value
;
776 if (apic
->vcpu
->vcpu_id
)
777 value
&= ~MSR_IA32_APICBASE_BSP
;
779 vcpu
->apic_base
= value
;
780 apic
->base_address
= apic
->vcpu
->apic_base
&
781 MSR_IA32_APICBASE_BASE
;
783 /* with FSB delivery interrupt, we can restart APIC functionality */
784 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
785 "0x%lx.\n", apic
->apic_base
, apic
->base_address
);
789 u64
kvm_lapic_get_base(struct kvm_vcpu
*vcpu
)
791 return vcpu
->apic_base
;
793 EXPORT_SYMBOL_GPL(kvm_lapic_get_base
);
795 static void lapic_reset(struct kvm_vcpu
*vcpu
)
797 struct kvm_lapic
*apic
;
800 apic_debug("%s\n", __FUNCTION__
);
804 ASSERT(apic
!= NULL
);
806 /* Stop the timer in case it's a reset to an active apic */
807 hrtimer_cancel(&apic
->timer
.dev
);
809 apic_set_reg(apic
, APIC_ID
, vcpu
->vcpu_id
<< 24);
810 apic_set_reg(apic
, APIC_LVR
, APIC_VERSION
);
812 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
813 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
814 apic_set_reg(apic
, APIC_LVT0
,
815 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
817 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
818 apic_set_reg(apic
, APIC_SPIV
, 0xff);
819 apic_set_reg(apic
, APIC_TASKPRI
, 0);
820 apic_set_reg(apic
, APIC_LDR
, 0);
821 apic_set_reg(apic
, APIC_ESR
, 0);
822 apic_set_reg(apic
, APIC_ICR
, 0);
823 apic_set_reg(apic
, APIC_ICR2
, 0);
824 apic_set_reg(apic
, APIC_TDCR
, 0);
825 apic_set_reg(apic
, APIC_TMICT
, 0);
826 for (i
= 0; i
< 8; i
++) {
827 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
828 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
829 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
831 apic
->timer
.divide_count
= 0;
832 atomic_set(&apic
->timer
.pending
, 0);
833 if (vcpu
->vcpu_id
== 0)
834 vcpu
->apic_base
|= MSR_IA32_APICBASE_BSP
;
835 apic_update_ppr(apic
);
837 apic_debug(KERN_INFO
"%s: vcpu=%p, id=%d, base_msr="
838 "0x%016" PRIx64
", base_address=0x%0lx.\n", __FUNCTION__
,
839 vcpu
, kvm_apic_id(apic
),
840 vcpu
->apic_base
, apic
->base_address
);
843 int kvm_lapic_enabled(struct kvm_vcpu
*vcpu
)
845 struct kvm_lapic
*apic
= (struct kvm_lapic
*)vcpu
->apic
;
850 ret
= apic_enabled(apic
);
854 EXPORT_SYMBOL_GPL(kvm_lapic_enabled
);
857 *----------------------------------------------------------------------
859 *----------------------------------------------------------------------
862 /* TODO: make sure __apic_timer_fn runs in current pCPU */
863 static int __apic_timer_fn(struct kvm_lapic
*apic
)
866 wait_queue_head_t
*q
= &apic
->vcpu
->wq
;
868 atomic_inc(&apic
->timer
.pending
);
869 if (waitqueue_active(q
))
870 wake_up_interruptible(q
);
871 if (apic_lvtt_period(apic
)) {
873 apic
->timer
.dev
.expires
= ktime_add_ns(
874 apic
->timer
.dev
.expires
,
880 static int __inject_apic_timer_irq(struct kvm_lapic
*apic
)
884 vector
= apic_lvt_vector(apic
, APIC_LVTT
);
885 return __apic_accept_irq(apic
, APIC_DM_FIXED
, vector
, 1, 0);
888 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
890 struct kvm_lapic
*apic
;
891 int restart_timer
= 0;
893 apic
= container_of(data
, struct kvm_lapic
, timer
.dev
);
895 restart_timer
= __apic_timer_fn(apic
);
898 return HRTIMER_RESTART
;
900 return HRTIMER_NORESTART
;
903 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
905 struct kvm_lapic
*apic
;
907 ASSERT(vcpu
!= NULL
);
908 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
910 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
916 apic
->regs_page
= alloc_page(GFP_KERNEL
);
917 if (apic
->regs_page
== NULL
) {
918 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
922 apic
->regs
= page_address(apic
->regs_page
);
923 memset(apic
->regs
, 0, PAGE_SIZE
);
926 hrtimer_init(&apic
->timer
.dev
, CLOCK_MONOTONIC
, HRTIMER_MODE_ABS
);
927 apic
->timer
.dev
.function
= apic_timer_fn
;
928 apic
->base_address
= APIC_DEFAULT_PHYS_BASE
;
929 vcpu
->apic_base
= APIC_DEFAULT_PHYS_BASE
;
932 apic
->dev
.read
= apic_mmio_read
;
933 apic
->dev
.write
= apic_mmio_write
;
934 apic
->dev
.in_range
= apic_mmio_range
;
935 apic
->dev
.private = apic
;
942 EXPORT_SYMBOL_GPL(kvm_create_lapic
);
944 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
946 struct kvm_lapic
*apic
= vcpu
->apic
;
949 if (!apic
|| !apic_enabled(apic
))
952 apic_update_ppr(apic
);
953 highest_irr
= apic_find_highest_irr(apic
);
954 if ((highest_irr
== -1) ||
955 ((highest_irr
& 0xF0) <= apic_get_reg(apic
, APIC_PROCPRI
)))
960 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
962 u32 lvt0
= apic_get_reg(vcpu
->apic
, APIC_LVT0
);
965 if (vcpu
->vcpu_id
== 0) {
966 if (!apic_hw_enabled(vcpu
->apic
))
968 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
969 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
975 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
977 struct kvm_lapic
*apic
= vcpu
->apic
;
979 if (apic
&& apic_lvt_enabled(apic
, APIC_LVTT
) &&
980 atomic_read(&apic
->timer
.pending
) > 0) {
981 if (__inject_apic_timer_irq(apic
))
982 atomic_dec(&apic
->timer
.pending
);
986 void kvm_apic_timer_intr_post(struct kvm_vcpu
*vcpu
, int vec
)
988 struct kvm_lapic
*apic
= vcpu
->apic
;
990 if (apic
&& apic_lvt_vector(apic
, APIC_LVTT
) == vec
)
991 apic
->timer
.last_update
= ktime_add_ns(
992 apic
->timer
.last_update
,
996 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
998 int vector
= kvm_apic_has_interrupt(vcpu
);
999 struct kvm_lapic
*apic
= vcpu
->apic
;
1004 apic_set_vector(vector
, apic
->regs
+ APIC_ISR
);
1005 apic_update_ppr(apic
);
1006 apic_clear_irr(vector
, apic
);
1010 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
)
1012 struct kvm_lapic
*apic
= vcpu
->apic
;
1014 apic
->base_address
= vcpu
->apic_base
&
1015 MSR_IA32_APICBASE_BASE
;
1016 apic_set_reg(apic
, APIC_LVR
, APIC_VERSION
);
1017 apic_update_ppr(apic
);
1018 hrtimer_cancel(&apic
->timer
.dev
);
1019 update_divide_count(apic
);
1020 start_apic_timer(apic
);
1023 void kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1025 struct kvm_lapic
*apic
= vcpu
->apic
;
1026 struct hrtimer
*timer
;
1031 timer
= &apic
->timer
.dev
;
1032 if (hrtimer_cancel(timer
))
1033 hrtimer_start(timer
, timer
->expires
, HRTIMER_MODE_ABS
);
1035 EXPORT_SYMBOL_GPL(kvm_migrate_apic_timer
);