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[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "kvm.h"
19 #include "x86_emulate.h"
20 #include "irq.h"
21 #include "vmx.h"
22 #include "segment_descriptor.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/profile.h>
29 #include <linux/sched.h>
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33
34 MODULE_AUTHOR("Qumranet");
35 MODULE_LICENSE("GPL");
36
37 struct vmcs {
38 u32 revision_id;
39 u32 abort;
40 char data[0];
41 };
42
43 struct vcpu_vmx {
44 struct kvm_vcpu vcpu;
45 int launched;
46 struct kvm_msr_entry *guest_msrs;
47 struct kvm_msr_entry *host_msrs;
48 int nmsrs;
49 int save_nmsrs;
50 int msr_offset_efer;
51 #ifdef CONFIG_X86_64
52 int msr_offset_kernel_gs_base;
53 #endif
54 struct vmcs *vmcs;
55 struct {
56 int loaded;
57 u16 fs_sel, gs_sel, ldt_sel;
58 int gs_ldt_reload_needed;
59 int fs_reload_needed;
60 }host_state;
61
62 };
63
64 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
65 {
66 return container_of(vcpu, struct vcpu_vmx, vcpu);
67 }
68
69 static int init_rmode_tss(struct kvm *kvm);
70
71 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
72 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
73
74 static struct page *vmx_io_bitmap_a;
75 static struct page *vmx_io_bitmap_b;
76
77 #define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
78
79 static struct vmcs_config {
80 int size;
81 int order;
82 u32 revision_id;
83 u32 pin_based_exec_ctrl;
84 u32 cpu_based_exec_ctrl;
85 u32 vmexit_ctrl;
86 u32 vmentry_ctrl;
87 } vmcs_config;
88
89 #define VMX_SEGMENT_FIELD(seg) \
90 [VCPU_SREG_##seg] = { \
91 .selector = GUEST_##seg##_SELECTOR, \
92 .base = GUEST_##seg##_BASE, \
93 .limit = GUEST_##seg##_LIMIT, \
94 .ar_bytes = GUEST_##seg##_AR_BYTES, \
95 }
96
97 static struct kvm_vmx_segment_field {
98 unsigned selector;
99 unsigned base;
100 unsigned limit;
101 unsigned ar_bytes;
102 } kvm_vmx_segment_fields[] = {
103 VMX_SEGMENT_FIELD(CS),
104 VMX_SEGMENT_FIELD(DS),
105 VMX_SEGMENT_FIELD(ES),
106 VMX_SEGMENT_FIELD(FS),
107 VMX_SEGMENT_FIELD(GS),
108 VMX_SEGMENT_FIELD(SS),
109 VMX_SEGMENT_FIELD(TR),
110 VMX_SEGMENT_FIELD(LDTR),
111 };
112
113 /*
114 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
115 * away by decrementing the array size.
116 */
117 static const u32 vmx_msr_index[] = {
118 #ifdef CONFIG_X86_64
119 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
120 #endif
121 MSR_EFER, MSR_K6_STAR,
122 };
123 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
124
125 static void load_msrs(struct kvm_msr_entry *e, int n)
126 {
127 int i;
128
129 for (i = 0; i < n; ++i)
130 wrmsrl(e[i].index, e[i].data);
131 }
132
133 static void save_msrs(struct kvm_msr_entry *e, int n)
134 {
135 int i;
136
137 for (i = 0; i < n; ++i)
138 rdmsrl(e[i].index, e[i].data);
139 }
140
141 static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr)
142 {
143 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
144 }
145
146 static inline int msr_efer_need_save_restore(struct vcpu_vmx *vmx)
147 {
148 int efer_offset = vmx->msr_offset_efer;
149 return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) !=
150 msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
151 }
152
153 static inline int is_page_fault(u32 intr_info)
154 {
155 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
156 INTR_INFO_VALID_MASK)) ==
157 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
158 }
159
160 static inline int is_no_device(u32 intr_info)
161 {
162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
163 INTR_INFO_VALID_MASK)) ==
164 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
165 }
166
167 static inline int is_external_interrupt(u32 intr_info)
168 {
169 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
170 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
171 }
172
173 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
174 {
175 int i;
176
177 for (i = 0; i < vmx->nmsrs; ++i)
178 if (vmx->guest_msrs[i].index == msr)
179 return i;
180 return -1;
181 }
182
183 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
184 {
185 int i;
186
187 i = __find_msr_index(vmx, msr);
188 if (i >= 0)
189 return &vmx->guest_msrs[i];
190 return NULL;
191 }
192
193 static void vmcs_clear(struct vmcs *vmcs)
194 {
195 u64 phys_addr = __pa(vmcs);
196 u8 error;
197
198 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
199 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
200 : "cc", "memory");
201 if (error)
202 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
203 vmcs, phys_addr);
204 }
205
206 static void __vcpu_clear(void *arg)
207 {
208 struct vcpu_vmx *vmx = arg;
209 int cpu = raw_smp_processor_id();
210
211 if (vmx->vcpu.cpu == cpu)
212 vmcs_clear(vmx->vmcs);
213 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
214 per_cpu(current_vmcs, cpu) = NULL;
215 rdtscll(vmx->vcpu.host_tsc);
216 }
217
218 static void vcpu_clear(struct vcpu_vmx *vmx)
219 {
220 if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1)
221 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear,
222 vmx, 0, 1);
223 else
224 __vcpu_clear(vmx);
225 vmx->launched = 0;
226 }
227
228 static unsigned long vmcs_readl(unsigned long field)
229 {
230 unsigned long value;
231
232 asm volatile (ASM_VMX_VMREAD_RDX_RAX
233 : "=a"(value) : "d"(field) : "cc");
234 return value;
235 }
236
237 static u16 vmcs_read16(unsigned long field)
238 {
239 return vmcs_readl(field);
240 }
241
242 static u32 vmcs_read32(unsigned long field)
243 {
244 return vmcs_readl(field);
245 }
246
247 static u64 vmcs_read64(unsigned long field)
248 {
249 #ifdef CONFIG_X86_64
250 return vmcs_readl(field);
251 #else
252 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
253 #endif
254 }
255
256 static noinline void vmwrite_error(unsigned long field, unsigned long value)
257 {
258 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
259 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
260 dump_stack();
261 }
262
263 static void vmcs_writel(unsigned long field, unsigned long value)
264 {
265 u8 error;
266
267 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
268 : "=q"(error) : "a"(value), "d"(field) : "cc" );
269 if (unlikely(error))
270 vmwrite_error(field, value);
271 }
272
273 static void vmcs_write16(unsigned long field, u16 value)
274 {
275 vmcs_writel(field, value);
276 }
277
278 static void vmcs_write32(unsigned long field, u32 value)
279 {
280 vmcs_writel(field, value);
281 }
282
283 static void vmcs_write64(unsigned long field, u64 value)
284 {
285 #ifdef CONFIG_X86_64
286 vmcs_writel(field, value);
287 #else
288 vmcs_writel(field, value);
289 asm volatile ("");
290 vmcs_writel(field+1, value >> 32);
291 #endif
292 }
293
294 static void vmcs_clear_bits(unsigned long field, u32 mask)
295 {
296 vmcs_writel(field, vmcs_readl(field) & ~mask);
297 }
298
299 static void vmcs_set_bits(unsigned long field, u32 mask)
300 {
301 vmcs_writel(field, vmcs_readl(field) | mask);
302 }
303
304 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
305 {
306 u32 eb;
307
308 eb = 1u << PF_VECTOR;
309 if (!vcpu->fpu_active)
310 eb |= 1u << NM_VECTOR;
311 if (vcpu->guest_debug.enabled)
312 eb |= 1u << 1;
313 if (vcpu->rmode.active)
314 eb = ~0;
315 vmcs_write32(EXCEPTION_BITMAP, eb);
316 }
317
318 static void reload_tss(void)
319 {
320 #ifndef CONFIG_X86_64
321
322 /*
323 * VT restores TR but not its size. Useless.
324 */
325 struct descriptor_table gdt;
326 struct segment_descriptor *descs;
327
328 get_gdt(&gdt);
329 descs = (void *)gdt.base;
330 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
331 load_TR_desc();
332 #endif
333 }
334
335 static void load_transition_efer(struct vcpu_vmx *vmx)
336 {
337 u64 trans_efer;
338 int efer_offset = vmx->msr_offset_efer;
339
340 trans_efer = vmx->host_msrs[efer_offset].data;
341 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
342 trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
343 wrmsrl(MSR_EFER, trans_efer);
344 vmx->vcpu.stat.efer_reload++;
345 }
346
347 static void vmx_save_host_state(struct vcpu_vmx *vmx)
348 {
349 if (vmx->host_state.loaded)
350 return;
351
352 vmx->host_state.loaded = 1;
353 /*
354 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
355 * allow segment selectors with cpl > 0 or ti == 1.
356 */
357 vmx->host_state.ldt_sel = read_ldt();
358 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
359 vmx->host_state.fs_sel = read_fs();
360 if (!(vmx->host_state.fs_sel & 7)) {
361 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
362 vmx->host_state.fs_reload_needed = 0;
363 } else {
364 vmcs_write16(HOST_FS_SELECTOR, 0);
365 vmx->host_state.fs_reload_needed = 1;
366 }
367 vmx->host_state.gs_sel = read_gs();
368 if (!(vmx->host_state.gs_sel & 7))
369 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
370 else {
371 vmcs_write16(HOST_GS_SELECTOR, 0);
372 vmx->host_state.gs_ldt_reload_needed = 1;
373 }
374
375 #ifdef CONFIG_X86_64
376 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
377 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
378 #else
379 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
380 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
381 #endif
382
383 #ifdef CONFIG_X86_64
384 if (is_long_mode(&vmx->vcpu)) {
385 save_msrs(vmx->host_msrs +
386 vmx->msr_offset_kernel_gs_base, 1);
387 }
388 #endif
389 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
390 if (msr_efer_need_save_restore(vmx))
391 load_transition_efer(vmx);
392 }
393
394 static void vmx_load_host_state(struct vcpu_vmx *vmx)
395 {
396 unsigned long flags;
397
398 if (!vmx->host_state.loaded)
399 return;
400
401 vmx->host_state.loaded = 0;
402 if (vmx->host_state.fs_reload_needed)
403 load_fs(vmx->host_state.fs_sel);
404 if (vmx->host_state.gs_ldt_reload_needed) {
405 load_ldt(vmx->host_state.ldt_sel);
406 /*
407 * If we have to reload gs, we must take care to
408 * preserve our gs base.
409 */
410 local_irq_save(flags);
411 load_gs(vmx->host_state.gs_sel);
412 #ifdef CONFIG_X86_64
413 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
414 #endif
415 local_irq_restore(flags);
416 }
417 reload_tss();
418 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
419 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
420 if (msr_efer_need_save_restore(vmx))
421 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
422 }
423
424 /*
425 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
426 * vcpu mutex is already taken.
427 */
428 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
429 {
430 struct vcpu_vmx *vmx = to_vmx(vcpu);
431 u64 phys_addr = __pa(vmx->vmcs);
432 u64 tsc_this, delta;
433
434 if (vcpu->cpu != cpu)
435 vcpu_clear(vmx);
436
437 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
438 u8 error;
439
440 per_cpu(current_vmcs, cpu) = vmx->vmcs;
441 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
442 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
443 : "cc");
444 if (error)
445 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
446 vmx->vmcs, phys_addr);
447 }
448
449 if (vcpu->cpu != cpu) {
450 struct descriptor_table dt;
451 unsigned long sysenter_esp;
452
453 vcpu->cpu = cpu;
454 /*
455 * Linux uses per-cpu TSS and GDT, so set these when switching
456 * processors.
457 */
458 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
459 get_gdt(&dt);
460 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
461
462 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
463 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
464
465 /*
466 * Make sure the time stamp counter is monotonous.
467 */
468 rdtscll(tsc_this);
469 delta = vcpu->host_tsc - tsc_this;
470 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
471 }
472 }
473
474 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
475 {
476 vmx_load_host_state(to_vmx(vcpu));
477 kvm_put_guest_fpu(vcpu);
478 }
479
480 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
481 {
482 if (vcpu->fpu_active)
483 return;
484 vcpu->fpu_active = 1;
485 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
486 if (vcpu->cr0 & X86_CR0_TS)
487 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
488 update_exception_bitmap(vcpu);
489 }
490
491 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
492 {
493 if (!vcpu->fpu_active)
494 return;
495 vcpu->fpu_active = 0;
496 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
497 update_exception_bitmap(vcpu);
498 }
499
500 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
501 {
502 vcpu_clear(to_vmx(vcpu));
503 }
504
505 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
506 {
507 return vmcs_readl(GUEST_RFLAGS);
508 }
509
510 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
511 {
512 vmcs_writel(GUEST_RFLAGS, rflags);
513 }
514
515 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
516 {
517 unsigned long rip;
518 u32 interruptibility;
519
520 rip = vmcs_readl(GUEST_RIP);
521 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
522 vmcs_writel(GUEST_RIP, rip);
523
524 /*
525 * We emulated an instruction, so temporary interrupt blocking
526 * should be removed, if set.
527 */
528 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
529 if (interruptibility & 3)
530 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
531 interruptibility & ~3);
532 vcpu->interrupt_window_open = 1;
533 }
534
535 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
536 {
537 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
538 vmcs_readl(GUEST_RIP));
539 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
540 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
541 GP_VECTOR |
542 INTR_TYPE_EXCEPTION |
543 INTR_INFO_DELIEVER_CODE_MASK |
544 INTR_INFO_VALID_MASK);
545 }
546
547 /*
548 * Swap MSR entry in host/guest MSR entry array.
549 */
550 #ifdef CONFIG_X86_64
551 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
552 {
553 struct kvm_msr_entry tmp;
554
555 tmp = vmx->guest_msrs[to];
556 vmx->guest_msrs[to] = vmx->guest_msrs[from];
557 vmx->guest_msrs[from] = tmp;
558 tmp = vmx->host_msrs[to];
559 vmx->host_msrs[to] = vmx->host_msrs[from];
560 vmx->host_msrs[from] = tmp;
561 }
562 #endif
563
564 /*
565 * Set up the vmcs to automatically save and restore system
566 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
567 * mode, as fiddling with msrs is very expensive.
568 */
569 static void setup_msrs(struct vcpu_vmx *vmx)
570 {
571 int save_nmsrs;
572
573 save_nmsrs = 0;
574 #ifdef CONFIG_X86_64
575 if (is_long_mode(&vmx->vcpu)) {
576 int index;
577
578 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
579 if (index >= 0)
580 move_msr_up(vmx, index, save_nmsrs++);
581 index = __find_msr_index(vmx, MSR_LSTAR);
582 if (index >= 0)
583 move_msr_up(vmx, index, save_nmsrs++);
584 index = __find_msr_index(vmx, MSR_CSTAR);
585 if (index >= 0)
586 move_msr_up(vmx, index, save_nmsrs++);
587 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
588 if (index >= 0)
589 move_msr_up(vmx, index, save_nmsrs++);
590 /*
591 * MSR_K6_STAR is only needed on long mode guests, and only
592 * if efer.sce is enabled.
593 */
594 index = __find_msr_index(vmx, MSR_K6_STAR);
595 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
596 move_msr_up(vmx, index, save_nmsrs++);
597 }
598 #endif
599 vmx->save_nmsrs = save_nmsrs;
600
601 #ifdef CONFIG_X86_64
602 vmx->msr_offset_kernel_gs_base =
603 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
604 #endif
605 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
606 }
607
608 /*
609 * reads and returns guest's timestamp counter "register"
610 * guest_tsc = host_tsc + tsc_offset -- 21.3
611 */
612 static u64 guest_read_tsc(void)
613 {
614 u64 host_tsc, tsc_offset;
615
616 rdtscll(host_tsc);
617 tsc_offset = vmcs_read64(TSC_OFFSET);
618 return host_tsc + tsc_offset;
619 }
620
621 /*
622 * writes 'guest_tsc' into guest's timestamp counter "register"
623 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
624 */
625 static void guest_write_tsc(u64 guest_tsc)
626 {
627 u64 host_tsc;
628
629 rdtscll(host_tsc);
630 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
631 }
632
633 /*
634 * Reads an msr value (of 'msr_index') into 'pdata'.
635 * Returns 0 on success, non-0 otherwise.
636 * Assumes vcpu_load() was already called.
637 */
638 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
639 {
640 u64 data;
641 struct kvm_msr_entry *msr;
642
643 if (!pdata) {
644 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
645 return -EINVAL;
646 }
647
648 switch (msr_index) {
649 #ifdef CONFIG_X86_64
650 case MSR_FS_BASE:
651 data = vmcs_readl(GUEST_FS_BASE);
652 break;
653 case MSR_GS_BASE:
654 data = vmcs_readl(GUEST_GS_BASE);
655 break;
656 case MSR_EFER:
657 return kvm_get_msr_common(vcpu, msr_index, pdata);
658 #endif
659 case MSR_IA32_TIME_STAMP_COUNTER:
660 data = guest_read_tsc();
661 break;
662 case MSR_IA32_SYSENTER_CS:
663 data = vmcs_read32(GUEST_SYSENTER_CS);
664 break;
665 case MSR_IA32_SYSENTER_EIP:
666 data = vmcs_readl(GUEST_SYSENTER_EIP);
667 break;
668 case MSR_IA32_SYSENTER_ESP:
669 data = vmcs_readl(GUEST_SYSENTER_ESP);
670 break;
671 default:
672 msr = find_msr_entry(to_vmx(vcpu), msr_index);
673 if (msr) {
674 data = msr->data;
675 break;
676 }
677 return kvm_get_msr_common(vcpu, msr_index, pdata);
678 }
679
680 *pdata = data;
681 return 0;
682 }
683
684 /*
685 * Writes msr value into into the appropriate "register".
686 * Returns 0 on success, non-0 otherwise.
687 * Assumes vcpu_load() was already called.
688 */
689 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
690 {
691 struct vcpu_vmx *vmx = to_vmx(vcpu);
692 struct kvm_msr_entry *msr;
693 int ret = 0;
694
695 switch (msr_index) {
696 #ifdef CONFIG_X86_64
697 case MSR_EFER:
698 ret = kvm_set_msr_common(vcpu, msr_index, data);
699 if (vmx->host_state.loaded)
700 load_transition_efer(vmx);
701 break;
702 case MSR_FS_BASE:
703 vmcs_writel(GUEST_FS_BASE, data);
704 break;
705 case MSR_GS_BASE:
706 vmcs_writel(GUEST_GS_BASE, data);
707 break;
708 #endif
709 case MSR_IA32_SYSENTER_CS:
710 vmcs_write32(GUEST_SYSENTER_CS, data);
711 break;
712 case MSR_IA32_SYSENTER_EIP:
713 vmcs_writel(GUEST_SYSENTER_EIP, data);
714 break;
715 case MSR_IA32_SYSENTER_ESP:
716 vmcs_writel(GUEST_SYSENTER_ESP, data);
717 break;
718 case MSR_IA32_TIME_STAMP_COUNTER:
719 guest_write_tsc(data);
720 break;
721 default:
722 msr = find_msr_entry(vmx, msr_index);
723 if (msr) {
724 msr->data = data;
725 if (vmx->host_state.loaded)
726 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
727 break;
728 }
729 ret = kvm_set_msr_common(vcpu, msr_index, data);
730 }
731
732 return ret;
733 }
734
735 /*
736 * Sync the rsp and rip registers into the vcpu structure. This allows
737 * registers to be accessed by indexing vcpu->regs.
738 */
739 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
740 {
741 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
742 vcpu->rip = vmcs_readl(GUEST_RIP);
743 }
744
745 /*
746 * Syncs rsp and rip back into the vmcs. Should be called after possible
747 * modification.
748 */
749 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
750 {
751 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
752 vmcs_writel(GUEST_RIP, vcpu->rip);
753 }
754
755 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
756 {
757 unsigned long dr7 = 0x400;
758 int old_singlestep;
759
760 old_singlestep = vcpu->guest_debug.singlestep;
761
762 vcpu->guest_debug.enabled = dbg->enabled;
763 if (vcpu->guest_debug.enabled) {
764 int i;
765
766 dr7 |= 0x200; /* exact */
767 for (i = 0; i < 4; ++i) {
768 if (!dbg->breakpoints[i].enabled)
769 continue;
770 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
771 dr7 |= 2 << (i*2); /* global enable */
772 dr7 |= 0 << (i*4+16); /* execution breakpoint */
773 }
774
775 vcpu->guest_debug.singlestep = dbg->singlestep;
776 } else
777 vcpu->guest_debug.singlestep = 0;
778
779 if (old_singlestep && !vcpu->guest_debug.singlestep) {
780 unsigned long flags;
781
782 flags = vmcs_readl(GUEST_RFLAGS);
783 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
784 vmcs_writel(GUEST_RFLAGS, flags);
785 }
786
787 update_exception_bitmap(vcpu);
788 vmcs_writel(GUEST_DR7, dr7);
789
790 return 0;
791 }
792
793 static __init int cpu_has_kvm_support(void)
794 {
795 unsigned long ecx = cpuid_ecx(1);
796 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
797 }
798
799 static __init int vmx_disabled_by_bios(void)
800 {
801 u64 msr;
802
803 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
804 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
805 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
806 == MSR_IA32_FEATURE_CONTROL_LOCKED;
807 /* locked but not enabled */
808 }
809
810 static void hardware_enable(void *garbage)
811 {
812 int cpu = raw_smp_processor_id();
813 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
814 u64 old;
815
816 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
817 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
818 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
819 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
820 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
821 /* enable and lock */
822 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
823 MSR_IA32_FEATURE_CONTROL_LOCKED |
824 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
825 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
826 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
827 : "memory", "cc");
828 }
829
830 static void hardware_disable(void *garbage)
831 {
832 asm volatile (ASM_VMX_VMXOFF : : : "cc");
833 }
834
835 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
836 u32 msr, u32* result)
837 {
838 u32 vmx_msr_low, vmx_msr_high;
839 u32 ctl = ctl_min | ctl_opt;
840
841 rdmsr(msr, vmx_msr_low, vmx_msr_high);
842
843 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
844 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
845
846 /* Ensure minimum (required) set of control bits are supported. */
847 if (ctl_min & ~ctl)
848 return -EIO;
849
850 *result = ctl;
851 return 0;
852 }
853
854 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
855 {
856 u32 vmx_msr_low, vmx_msr_high;
857 u32 min, opt;
858 u32 _pin_based_exec_control = 0;
859 u32 _cpu_based_exec_control = 0;
860 u32 _vmexit_control = 0;
861 u32 _vmentry_control = 0;
862
863 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
864 opt = 0;
865 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
866 &_pin_based_exec_control) < 0)
867 return -EIO;
868
869 min = CPU_BASED_HLT_EXITING |
870 #ifdef CONFIG_X86_64
871 CPU_BASED_CR8_LOAD_EXITING |
872 CPU_BASED_CR8_STORE_EXITING |
873 #endif
874 CPU_BASED_USE_IO_BITMAPS |
875 CPU_BASED_MOV_DR_EXITING |
876 CPU_BASED_USE_TSC_OFFSETING;
877 opt = 0;
878 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
879 &_cpu_based_exec_control) < 0)
880 return -EIO;
881
882 min = 0;
883 #ifdef CONFIG_X86_64
884 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
885 #endif
886 opt = 0;
887 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
888 &_vmexit_control) < 0)
889 return -EIO;
890
891 min = opt = 0;
892 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
893 &_vmentry_control) < 0)
894 return -EIO;
895
896 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
897
898 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
899 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
900 return -EIO;
901
902 #ifdef CONFIG_X86_64
903 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
904 if (vmx_msr_high & (1u<<16))
905 return -EIO;
906 #endif
907
908 /* Require Write-Back (WB) memory type for VMCS accesses. */
909 if (((vmx_msr_high >> 18) & 15) != 6)
910 return -EIO;
911
912 vmcs_conf->size = vmx_msr_high & 0x1fff;
913 vmcs_conf->order = get_order(vmcs_config.size);
914 vmcs_conf->revision_id = vmx_msr_low;
915
916 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
917 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
918 vmcs_conf->vmexit_ctrl = _vmexit_control;
919 vmcs_conf->vmentry_ctrl = _vmentry_control;
920
921 return 0;
922 }
923
924 static struct vmcs *alloc_vmcs_cpu(int cpu)
925 {
926 int node = cpu_to_node(cpu);
927 struct page *pages;
928 struct vmcs *vmcs;
929
930 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
931 if (!pages)
932 return NULL;
933 vmcs = page_address(pages);
934 memset(vmcs, 0, vmcs_config.size);
935 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
936 return vmcs;
937 }
938
939 static struct vmcs *alloc_vmcs(void)
940 {
941 return alloc_vmcs_cpu(raw_smp_processor_id());
942 }
943
944 static void free_vmcs(struct vmcs *vmcs)
945 {
946 free_pages((unsigned long)vmcs, vmcs_config.order);
947 }
948
949 static void free_kvm_area(void)
950 {
951 int cpu;
952
953 for_each_online_cpu(cpu)
954 free_vmcs(per_cpu(vmxarea, cpu));
955 }
956
957 static __init int alloc_kvm_area(void)
958 {
959 int cpu;
960
961 for_each_online_cpu(cpu) {
962 struct vmcs *vmcs;
963
964 vmcs = alloc_vmcs_cpu(cpu);
965 if (!vmcs) {
966 free_kvm_area();
967 return -ENOMEM;
968 }
969
970 per_cpu(vmxarea, cpu) = vmcs;
971 }
972 return 0;
973 }
974
975 static __init int hardware_setup(void)
976 {
977 if (setup_vmcs_config(&vmcs_config) < 0)
978 return -EIO;
979 return alloc_kvm_area();
980 }
981
982 static __exit void hardware_unsetup(void)
983 {
984 free_kvm_area();
985 }
986
987 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
988 {
989 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
990
991 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
992 vmcs_write16(sf->selector, save->selector);
993 vmcs_writel(sf->base, save->base);
994 vmcs_write32(sf->limit, save->limit);
995 vmcs_write32(sf->ar_bytes, save->ar);
996 } else {
997 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
998 << AR_DPL_SHIFT;
999 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1000 }
1001 }
1002
1003 static void enter_pmode(struct kvm_vcpu *vcpu)
1004 {
1005 unsigned long flags;
1006
1007 vcpu->rmode.active = 0;
1008
1009 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1010 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1011 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1012
1013 flags = vmcs_readl(GUEST_RFLAGS);
1014 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
1015 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1016 vmcs_writel(GUEST_RFLAGS, flags);
1017
1018 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1019 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1020
1021 update_exception_bitmap(vcpu);
1022
1023 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1024 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1025 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1026 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1027
1028 vmcs_write16(GUEST_SS_SELECTOR, 0);
1029 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1030
1031 vmcs_write16(GUEST_CS_SELECTOR,
1032 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1033 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1034 }
1035
1036 static gva_t rmode_tss_base(struct kvm* kvm)
1037 {
1038 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1039 return base_gfn << PAGE_SHIFT;
1040 }
1041
1042 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1043 {
1044 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1045
1046 save->selector = vmcs_read16(sf->selector);
1047 save->base = vmcs_readl(sf->base);
1048 save->limit = vmcs_read32(sf->limit);
1049 save->ar = vmcs_read32(sf->ar_bytes);
1050 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1051 vmcs_write32(sf->limit, 0xffff);
1052 vmcs_write32(sf->ar_bytes, 0xf3);
1053 }
1054
1055 static void enter_rmode(struct kvm_vcpu *vcpu)
1056 {
1057 unsigned long flags;
1058
1059 vcpu->rmode.active = 1;
1060
1061 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1062 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1063
1064 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1065 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1066
1067 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1068 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1069
1070 flags = vmcs_readl(GUEST_RFLAGS);
1071 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
1072
1073 flags |= IOPL_MASK | X86_EFLAGS_VM;
1074
1075 vmcs_writel(GUEST_RFLAGS, flags);
1076 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1077 update_exception_bitmap(vcpu);
1078
1079 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1080 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1081 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1082
1083 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1084 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1085 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1086 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1087 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1088
1089 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1090 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1091 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1092 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1093
1094 init_rmode_tss(vcpu->kvm);
1095 }
1096
1097 #ifdef CONFIG_X86_64
1098
1099 static void enter_lmode(struct kvm_vcpu *vcpu)
1100 {
1101 u32 guest_tr_ar;
1102
1103 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1104 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1105 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1106 __FUNCTION__);
1107 vmcs_write32(GUEST_TR_AR_BYTES,
1108 (guest_tr_ar & ~AR_TYPE_MASK)
1109 | AR_TYPE_BUSY_64_TSS);
1110 }
1111
1112 vcpu->shadow_efer |= EFER_LMA;
1113
1114 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1115 vmcs_write32(VM_ENTRY_CONTROLS,
1116 vmcs_read32(VM_ENTRY_CONTROLS)
1117 | VM_ENTRY_IA32E_MODE);
1118 }
1119
1120 static void exit_lmode(struct kvm_vcpu *vcpu)
1121 {
1122 vcpu->shadow_efer &= ~EFER_LMA;
1123
1124 vmcs_write32(VM_ENTRY_CONTROLS,
1125 vmcs_read32(VM_ENTRY_CONTROLS)
1126 & ~VM_ENTRY_IA32E_MODE);
1127 }
1128
1129 #endif
1130
1131 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1132 {
1133 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1134 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1135 }
1136
1137 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1138 {
1139 vmx_fpu_deactivate(vcpu);
1140
1141 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1142 enter_pmode(vcpu);
1143
1144 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1145 enter_rmode(vcpu);
1146
1147 #ifdef CONFIG_X86_64
1148 if (vcpu->shadow_efer & EFER_LME) {
1149 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1150 enter_lmode(vcpu);
1151 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1152 exit_lmode(vcpu);
1153 }
1154 #endif
1155
1156 vmcs_writel(CR0_READ_SHADOW, cr0);
1157 vmcs_writel(GUEST_CR0,
1158 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1159 vcpu->cr0 = cr0;
1160
1161 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1162 vmx_fpu_activate(vcpu);
1163 }
1164
1165 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1166 {
1167 vmcs_writel(GUEST_CR3, cr3);
1168 if (vcpu->cr0 & X86_CR0_PE)
1169 vmx_fpu_deactivate(vcpu);
1170 }
1171
1172 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1173 {
1174 vmcs_writel(CR4_READ_SHADOW, cr4);
1175 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1176 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1177 vcpu->cr4 = cr4;
1178 }
1179
1180 #ifdef CONFIG_X86_64
1181
1182 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1183 {
1184 struct vcpu_vmx *vmx = to_vmx(vcpu);
1185 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1186
1187 vcpu->shadow_efer = efer;
1188 if (efer & EFER_LMA) {
1189 vmcs_write32(VM_ENTRY_CONTROLS,
1190 vmcs_read32(VM_ENTRY_CONTROLS) |
1191 VM_ENTRY_IA32E_MODE);
1192 msr->data = efer;
1193
1194 } else {
1195 vmcs_write32(VM_ENTRY_CONTROLS,
1196 vmcs_read32(VM_ENTRY_CONTROLS) &
1197 ~VM_ENTRY_IA32E_MODE);
1198
1199 msr->data = efer & ~EFER_LME;
1200 }
1201 setup_msrs(vmx);
1202 }
1203
1204 #endif
1205
1206 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1207 {
1208 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1209
1210 return vmcs_readl(sf->base);
1211 }
1212
1213 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1214 struct kvm_segment *var, int seg)
1215 {
1216 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1217 u32 ar;
1218
1219 var->base = vmcs_readl(sf->base);
1220 var->limit = vmcs_read32(sf->limit);
1221 var->selector = vmcs_read16(sf->selector);
1222 ar = vmcs_read32(sf->ar_bytes);
1223 if (ar & AR_UNUSABLE_MASK)
1224 ar = 0;
1225 var->type = ar & 15;
1226 var->s = (ar >> 4) & 1;
1227 var->dpl = (ar >> 5) & 3;
1228 var->present = (ar >> 7) & 1;
1229 var->avl = (ar >> 12) & 1;
1230 var->l = (ar >> 13) & 1;
1231 var->db = (ar >> 14) & 1;
1232 var->g = (ar >> 15) & 1;
1233 var->unusable = (ar >> 16) & 1;
1234 }
1235
1236 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1237 {
1238 u32 ar;
1239
1240 if (var->unusable)
1241 ar = 1 << 16;
1242 else {
1243 ar = var->type & 15;
1244 ar |= (var->s & 1) << 4;
1245 ar |= (var->dpl & 3) << 5;
1246 ar |= (var->present & 1) << 7;
1247 ar |= (var->avl & 1) << 12;
1248 ar |= (var->l & 1) << 13;
1249 ar |= (var->db & 1) << 14;
1250 ar |= (var->g & 1) << 15;
1251 }
1252 if (ar == 0) /* a 0 value means unusable */
1253 ar = AR_UNUSABLE_MASK;
1254
1255 return ar;
1256 }
1257
1258 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1259 struct kvm_segment *var, int seg)
1260 {
1261 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1262 u32 ar;
1263
1264 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1265 vcpu->rmode.tr.selector = var->selector;
1266 vcpu->rmode.tr.base = var->base;
1267 vcpu->rmode.tr.limit = var->limit;
1268 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1269 return;
1270 }
1271 vmcs_writel(sf->base, var->base);
1272 vmcs_write32(sf->limit, var->limit);
1273 vmcs_write16(sf->selector, var->selector);
1274 if (vcpu->rmode.active && var->s) {
1275 /*
1276 * Hack real-mode segments into vm86 compatibility.
1277 */
1278 if (var->base == 0xffff0000 && var->selector == 0xf000)
1279 vmcs_writel(sf->base, 0xf0000);
1280 ar = 0xf3;
1281 } else
1282 ar = vmx_segment_access_rights(var);
1283 vmcs_write32(sf->ar_bytes, ar);
1284 }
1285
1286 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1287 {
1288 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1289
1290 *db = (ar >> 14) & 1;
1291 *l = (ar >> 13) & 1;
1292 }
1293
1294 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1295 {
1296 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1297 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1298 }
1299
1300 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1301 {
1302 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1303 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1304 }
1305
1306 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1307 {
1308 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1309 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1310 }
1311
1312 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1313 {
1314 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1315 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1316 }
1317
1318 static int init_rmode_tss(struct kvm* kvm)
1319 {
1320 struct page *p1, *p2, *p3;
1321 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1322 char *page;
1323
1324 p1 = gfn_to_page(kvm, fn++);
1325 p2 = gfn_to_page(kvm, fn++);
1326 p3 = gfn_to_page(kvm, fn);
1327
1328 if (!p1 || !p2 || !p3) {
1329 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1330 return 0;
1331 }
1332
1333 page = kmap_atomic(p1, KM_USER0);
1334 clear_page(page);
1335 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1336 kunmap_atomic(page, KM_USER0);
1337
1338 page = kmap_atomic(p2, KM_USER0);
1339 clear_page(page);
1340 kunmap_atomic(page, KM_USER0);
1341
1342 page = kmap_atomic(p3, KM_USER0);
1343 clear_page(page);
1344 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1345 kunmap_atomic(page, KM_USER0);
1346
1347 return 1;
1348 }
1349
1350 static void seg_setup(int seg)
1351 {
1352 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1353
1354 vmcs_write16(sf->selector, 0);
1355 vmcs_writel(sf->base, 0);
1356 vmcs_write32(sf->limit, 0xffff);
1357 vmcs_write32(sf->ar_bytes, 0x93);
1358 }
1359
1360 /*
1361 * Sets up the vmcs for emulated real mode.
1362 */
1363 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1364 {
1365 u32 host_sysenter_cs;
1366 u32 junk;
1367 unsigned long a;
1368 struct descriptor_table dt;
1369 int i;
1370 int ret = 0;
1371 unsigned long kvm_vmx_return;
1372 u64 msr;
1373
1374 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1375 ret = -ENOMEM;
1376 goto out;
1377 }
1378
1379 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1380 set_cr8(&vmx->vcpu, 0);
1381 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1382 if (vmx->vcpu.vcpu_id == 0)
1383 msr |= MSR_IA32_APICBASE_BSP;
1384 kvm_set_apic_base(&vmx->vcpu, msr);
1385
1386 fx_init(&vmx->vcpu);
1387
1388 /*
1389 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1390 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1391 */
1392 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1393 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1394 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1395 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1396
1397 seg_setup(VCPU_SREG_DS);
1398 seg_setup(VCPU_SREG_ES);
1399 seg_setup(VCPU_SREG_FS);
1400 seg_setup(VCPU_SREG_GS);
1401 seg_setup(VCPU_SREG_SS);
1402
1403 vmcs_write16(GUEST_TR_SELECTOR, 0);
1404 vmcs_writel(GUEST_TR_BASE, 0);
1405 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1406 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1407
1408 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1409 vmcs_writel(GUEST_LDTR_BASE, 0);
1410 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1411 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1412
1413 vmcs_write32(GUEST_SYSENTER_CS, 0);
1414 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1415 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1416
1417 vmcs_writel(GUEST_RFLAGS, 0x02);
1418 vmcs_writel(GUEST_RIP, 0xfff0);
1419 vmcs_writel(GUEST_RSP, 0);
1420
1421 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1422 vmcs_writel(GUEST_DR7, 0x400);
1423
1424 vmcs_writel(GUEST_GDTR_BASE, 0);
1425 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1426
1427 vmcs_writel(GUEST_IDTR_BASE, 0);
1428 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1429
1430 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1431 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1432 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1433
1434 /* I/O */
1435 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1436 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1437
1438 guest_write_tsc(0);
1439
1440 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1441
1442 /* Special registers */
1443 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1444
1445 /* Control */
1446 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1447 vmcs_config.pin_based_exec_ctrl);
1448 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1449 vmcs_config.cpu_based_exec_ctrl);
1450
1451 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1452 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1453 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1454
1455 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1456 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1457 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1458
1459 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1460 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1461 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1462 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1463 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1464 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1465 #ifdef CONFIG_X86_64
1466 rdmsrl(MSR_FS_BASE, a);
1467 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1468 rdmsrl(MSR_GS_BASE, a);
1469 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1470 #else
1471 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1472 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1473 #endif
1474
1475 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1476
1477 get_idt(&dt);
1478 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1479
1480 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1481 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1482 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1483 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1484 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1485
1486 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1487 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1488 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1489 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1490 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1491 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1492
1493 for (i = 0; i < NR_VMX_MSR; ++i) {
1494 u32 index = vmx_msr_index[i];
1495 u32 data_low, data_high;
1496 u64 data;
1497 int j = vmx->nmsrs;
1498
1499 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1500 continue;
1501 if (wrmsr_safe(index, data_low, data_high) < 0)
1502 continue;
1503 data = data_low | ((u64)data_high << 32);
1504 vmx->host_msrs[j].index = index;
1505 vmx->host_msrs[j].reserved = 0;
1506 vmx->host_msrs[j].data = data;
1507 vmx->guest_msrs[j] = vmx->host_msrs[j];
1508 ++vmx->nmsrs;
1509 }
1510
1511 setup_msrs(vmx);
1512
1513 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1514
1515 /* 22.2.1, 20.8.1 */
1516 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1517
1518 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1519
1520 #ifdef CONFIG_X86_64
1521 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1522 vmcs_writel(TPR_THRESHOLD, 0);
1523 #endif
1524
1525 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1526 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1527
1528 vmx->vcpu.cr0 = 0x60000010;
1529 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1530 vmx_set_cr4(&vmx->vcpu, 0);
1531 #ifdef CONFIG_X86_64
1532 vmx_set_efer(&vmx->vcpu, 0);
1533 #endif
1534 vmx_fpu_activate(&vmx->vcpu);
1535 update_exception_bitmap(&vmx->vcpu);
1536
1537 return 0;
1538
1539 out:
1540 return ret;
1541 }
1542
1543 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1544 {
1545 u16 ent[2];
1546 u16 cs;
1547 u16 ip;
1548 unsigned long flags;
1549 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1550 u16 sp = vmcs_readl(GUEST_RSP);
1551 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1552
1553 if (sp > ss_limit || sp < 6 ) {
1554 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1555 __FUNCTION__,
1556 vmcs_readl(GUEST_RSP),
1557 vmcs_readl(GUEST_SS_BASE),
1558 vmcs_read32(GUEST_SS_LIMIT));
1559 return;
1560 }
1561
1562 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1563 X86EMUL_CONTINUE) {
1564 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1565 return;
1566 }
1567
1568 flags = vmcs_readl(GUEST_RFLAGS);
1569 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1570 ip = vmcs_readl(GUEST_RIP);
1571
1572
1573 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1574 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1575 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
1576 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1577 return;
1578 }
1579
1580 vmcs_writel(GUEST_RFLAGS, flags &
1581 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1582 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1583 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1584 vmcs_writel(GUEST_RIP, ent[0]);
1585 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1586 }
1587
1588 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1589 {
1590 if (vcpu->rmode.active) {
1591 inject_rmode_irq(vcpu, irq);
1592 return;
1593 }
1594 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1595 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1596 }
1597
1598 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1599 {
1600 int word_index = __ffs(vcpu->irq_summary);
1601 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1602 int irq = word_index * BITS_PER_LONG + bit_index;
1603
1604 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1605 if (!vcpu->irq_pending[word_index])
1606 clear_bit(word_index, &vcpu->irq_summary);
1607 vmx_inject_irq(vcpu, irq);
1608 }
1609
1610
1611 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1612 struct kvm_run *kvm_run)
1613 {
1614 u32 cpu_based_vm_exec_control;
1615
1616 vcpu->interrupt_window_open =
1617 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1618 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1619
1620 if (vcpu->interrupt_window_open &&
1621 vcpu->irq_summary &&
1622 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1623 /*
1624 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1625 */
1626 kvm_do_inject_irq(vcpu);
1627
1628 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1629 if (!vcpu->interrupt_window_open &&
1630 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1631 /*
1632 * Interrupts blocked. Wait for unblock.
1633 */
1634 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1635 else
1636 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1637 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1638 }
1639
1640 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1641 {
1642 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1643
1644 set_debugreg(dbg->bp[0], 0);
1645 set_debugreg(dbg->bp[1], 1);
1646 set_debugreg(dbg->bp[2], 2);
1647 set_debugreg(dbg->bp[3], 3);
1648
1649 if (dbg->singlestep) {
1650 unsigned long flags;
1651
1652 flags = vmcs_readl(GUEST_RFLAGS);
1653 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1654 vmcs_writel(GUEST_RFLAGS, flags);
1655 }
1656 }
1657
1658 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1659 int vec, u32 err_code)
1660 {
1661 if (!vcpu->rmode.active)
1662 return 0;
1663
1664 /*
1665 * Instruction with address size override prefix opcode 0x67
1666 * Cause the #SS fault with 0 error code in VM86 mode.
1667 */
1668 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1669 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1670 return 1;
1671 return 0;
1672 }
1673
1674 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1675 {
1676 u32 intr_info, error_code;
1677 unsigned long cr2, rip;
1678 u32 vect_info;
1679 enum emulation_result er;
1680 int r;
1681
1682 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1683 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1684
1685 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1686 !is_page_fault(intr_info)) {
1687 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1688 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1689 }
1690
1691 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1692 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1693 set_bit(irq, vcpu->irq_pending);
1694 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1695 }
1696
1697 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1698 asm ("int $2");
1699 return 1;
1700 }
1701
1702 if (is_no_device(intr_info)) {
1703 vmx_fpu_activate(vcpu);
1704 return 1;
1705 }
1706
1707 error_code = 0;
1708 rip = vmcs_readl(GUEST_RIP);
1709 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1710 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1711 if (is_page_fault(intr_info)) {
1712 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1713
1714 mutex_lock(&vcpu->kvm->lock);
1715 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1716 if (r < 0) {
1717 mutex_unlock(&vcpu->kvm->lock);
1718 return r;
1719 }
1720 if (!r) {
1721 mutex_unlock(&vcpu->kvm->lock);
1722 return 1;
1723 }
1724
1725 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1726 mutex_unlock(&vcpu->kvm->lock);
1727
1728 switch (er) {
1729 case EMULATE_DONE:
1730 return 1;
1731 case EMULATE_DO_MMIO:
1732 ++vcpu->stat.mmio_exits;
1733 return 0;
1734 case EMULATE_FAIL:
1735 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1736 break;
1737 default:
1738 BUG();
1739 }
1740 }
1741
1742 if (vcpu->rmode.active &&
1743 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1744 error_code)) {
1745 if (vcpu->halt_request) {
1746 vcpu->halt_request = 0;
1747 return kvm_emulate_halt(vcpu);
1748 }
1749 return 1;
1750 }
1751
1752 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1753 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1754 return 0;
1755 }
1756 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1757 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1758 kvm_run->ex.error_code = error_code;
1759 return 0;
1760 }
1761
1762 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1763 struct kvm_run *kvm_run)
1764 {
1765 ++vcpu->stat.irq_exits;
1766 return 1;
1767 }
1768
1769 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1770 {
1771 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1772 return 0;
1773 }
1774
1775 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1776 {
1777 u64 exit_qualification;
1778 int size, down, in, string, rep;
1779 unsigned port;
1780
1781 ++vcpu->stat.io_exits;
1782 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1783 string = (exit_qualification & 16) != 0;
1784
1785 if (string) {
1786 if (emulate_instruction(vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1787 return 0;
1788 return 1;
1789 }
1790
1791 size = (exit_qualification & 7) + 1;
1792 in = (exit_qualification & 8) != 0;
1793 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1794 rep = (exit_qualification & 32) != 0;
1795 port = exit_qualification >> 16;
1796
1797 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1798 }
1799
1800 static void
1801 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1802 {
1803 /*
1804 * Patch in the VMCALL instruction:
1805 */
1806 hypercall[0] = 0x0f;
1807 hypercall[1] = 0x01;
1808 hypercall[2] = 0xc1;
1809 hypercall[3] = 0xc3;
1810 }
1811
1812 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1813 {
1814 u64 exit_qualification;
1815 int cr;
1816 int reg;
1817
1818 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1819 cr = exit_qualification & 15;
1820 reg = (exit_qualification >> 8) & 15;
1821 switch ((exit_qualification >> 4) & 3) {
1822 case 0: /* mov to cr */
1823 switch (cr) {
1824 case 0:
1825 vcpu_load_rsp_rip(vcpu);
1826 set_cr0(vcpu, vcpu->regs[reg]);
1827 skip_emulated_instruction(vcpu);
1828 return 1;
1829 case 3:
1830 vcpu_load_rsp_rip(vcpu);
1831 set_cr3(vcpu, vcpu->regs[reg]);
1832 skip_emulated_instruction(vcpu);
1833 return 1;
1834 case 4:
1835 vcpu_load_rsp_rip(vcpu);
1836 set_cr4(vcpu, vcpu->regs[reg]);
1837 skip_emulated_instruction(vcpu);
1838 return 1;
1839 case 8:
1840 vcpu_load_rsp_rip(vcpu);
1841 set_cr8(vcpu, vcpu->regs[reg]);
1842 skip_emulated_instruction(vcpu);
1843 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1844 return 0;
1845 };
1846 break;
1847 case 2: /* clts */
1848 vcpu_load_rsp_rip(vcpu);
1849 vmx_fpu_deactivate(vcpu);
1850 vcpu->cr0 &= ~X86_CR0_TS;
1851 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1852 vmx_fpu_activate(vcpu);
1853 skip_emulated_instruction(vcpu);
1854 return 1;
1855 case 1: /*mov from cr*/
1856 switch (cr) {
1857 case 3:
1858 vcpu_load_rsp_rip(vcpu);
1859 vcpu->regs[reg] = vcpu->cr3;
1860 vcpu_put_rsp_rip(vcpu);
1861 skip_emulated_instruction(vcpu);
1862 return 1;
1863 case 8:
1864 vcpu_load_rsp_rip(vcpu);
1865 vcpu->regs[reg] = get_cr8(vcpu);
1866 vcpu_put_rsp_rip(vcpu);
1867 skip_emulated_instruction(vcpu);
1868 return 1;
1869 }
1870 break;
1871 case 3: /* lmsw */
1872 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1873
1874 skip_emulated_instruction(vcpu);
1875 return 1;
1876 default:
1877 break;
1878 }
1879 kvm_run->exit_reason = 0;
1880 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
1881 (int)(exit_qualification >> 4) & 3, cr);
1882 return 0;
1883 }
1884
1885 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1886 {
1887 u64 exit_qualification;
1888 unsigned long val;
1889 int dr, reg;
1890
1891 /*
1892 * FIXME: this code assumes the host is debugging the guest.
1893 * need to deal with guest debugging itself too.
1894 */
1895 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1896 dr = exit_qualification & 7;
1897 reg = (exit_qualification >> 8) & 15;
1898 vcpu_load_rsp_rip(vcpu);
1899 if (exit_qualification & 16) {
1900 /* mov from dr */
1901 switch (dr) {
1902 case 6:
1903 val = 0xffff0ff0;
1904 break;
1905 case 7:
1906 val = 0x400;
1907 break;
1908 default:
1909 val = 0;
1910 }
1911 vcpu->regs[reg] = val;
1912 } else {
1913 /* mov to dr */
1914 }
1915 vcpu_put_rsp_rip(vcpu);
1916 skip_emulated_instruction(vcpu);
1917 return 1;
1918 }
1919
1920 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1921 {
1922 kvm_emulate_cpuid(vcpu);
1923 return 1;
1924 }
1925
1926 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1927 {
1928 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1929 u64 data;
1930
1931 if (vmx_get_msr(vcpu, ecx, &data)) {
1932 vmx_inject_gp(vcpu, 0);
1933 return 1;
1934 }
1935
1936 /* FIXME: handling of bits 32:63 of rax, rdx */
1937 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1938 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1939 skip_emulated_instruction(vcpu);
1940 return 1;
1941 }
1942
1943 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1944 {
1945 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1946 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1947 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1948
1949 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1950 vmx_inject_gp(vcpu, 0);
1951 return 1;
1952 }
1953
1954 skip_emulated_instruction(vcpu);
1955 return 1;
1956 }
1957
1958 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1959 struct kvm_run *kvm_run)
1960 {
1961 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1962 kvm_run->cr8 = get_cr8(vcpu);
1963 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1964 if (irqchip_in_kernel(vcpu->kvm))
1965 kvm_run->ready_for_interrupt_injection = 1;
1966 else
1967 kvm_run->ready_for_interrupt_injection =
1968 (vcpu->interrupt_window_open &&
1969 vcpu->irq_summary == 0);
1970 }
1971
1972 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1973 struct kvm_run *kvm_run)
1974 {
1975 u32 cpu_based_vm_exec_control;
1976
1977 /* clear pending irq */
1978 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1979 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1980 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1981 /*
1982 * If the user space waits to inject interrupts, exit as soon as
1983 * possible
1984 */
1985 if (kvm_run->request_interrupt_window &&
1986 !vcpu->irq_summary) {
1987 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1988 ++vcpu->stat.irq_window_exits;
1989 return 0;
1990 }
1991 return 1;
1992 }
1993
1994 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1995 {
1996 skip_emulated_instruction(vcpu);
1997 return kvm_emulate_halt(vcpu);
1998 }
1999
2000 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2001 {
2002 skip_emulated_instruction(vcpu);
2003 return kvm_hypercall(vcpu, kvm_run);
2004 }
2005
2006 /*
2007 * The exit handlers return 1 if the exit was handled fully and guest execution
2008 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2009 * to be done to userspace and return 0.
2010 */
2011 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2012 struct kvm_run *kvm_run) = {
2013 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2014 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2015 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2016 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2017 [EXIT_REASON_CR_ACCESS] = handle_cr,
2018 [EXIT_REASON_DR_ACCESS] = handle_dr,
2019 [EXIT_REASON_CPUID] = handle_cpuid,
2020 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2021 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2022 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2023 [EXIT_REASON_HLT] = handle_halt,
2024 [EXIT_REASON_VMCALL] = handle_vmcall,
2025 };
2026
2027 static const int kvm_vmx_max_exit_handlers =
2028 ARRAY_SIZE(kvm_vmx_exit_handlers);
2029
2030 /*
2031 * The guest has exited. See if we can fix it or if we need userspace
2032 * assistance.
2033 */
2034 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2035 {
2036 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2037 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2038
2039 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2040 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2041 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2042 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2043 if (exit_reason < kvm_vmx_max_exit_handlers
2044 && kvm_vmx_exit_handlers[exit_reason])
2045 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2046 else {
2047 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2048 kvm_run->hw.hardware_exit_reason = exit_reason;
2049 }
2050 return 0;
2051 }
2052
2053 /*
2054 * Check if userspace requested an interrupt window, and that the
2055 * interrupt window is open.
2056 *
2057 * No need to exit to userspace if we already have an interrupt queued.
2058 */
2059 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2060 struct kvm_run *kvm_run)
2061 {
2062 return (!vcpu->irq_summary &&
2063 kvm_run->request_interrupt_window &&
2064 vcpu->interrupt_window_open &&
2065 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2066 }
2067
2068 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2069 {
2070 }
2071
2072 static void enable_irq_window(struct kvm_vcpu *vcpu)
2073 {
2074 u32 cpu_based_vm_exec_control;
2075
2076 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2077 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2078 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2079 }
2080
2081 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2082 {
2083 u32 idtv_info_field, intr_info_field;
2084 int has_ext_irq, interrupt_window_open;
2085
2086 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2087 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2088 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2089 if (intr_info_field & INTR_INFO_VALID_MASK) {
2090 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2091 /* TODO: fault when IDT_Vectoring */
2092 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2093 }
2094 if (has_ext_irq)
2095 enable_irq_window(vcpu);
2096 return;
2097 }
2098 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2099 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2100 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2101 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2102
2103 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2104 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2105 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2106 if (unlikely(has_ext_irq))
2107 enable_irq_window(vcpu);
2108 return;
2109 }
2110 if (!has_ext_irq)
2111 return;
2112 interrupt_window_open =
2113 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2114 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2115 if (interrupt_window_open)
2116 vmx_inject_irq(vcpu, kvm_cpu_get_interrupt(vcpu));
2117 else
2118 enable_irq_window(vcpu);
2119 }
2120
2121 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2122 {
2123 struct vcpu_vmx *vmx = to_vmx(vcpu);
2124 u8 fail;
2125 int r;
2126
2127 preempted:
2128 if (vcpu->guest_debug.enabled)
2129 kvm_guest_debug_pre(vcpu);
2130
2131 again:
2132 r = kvm_mmu_reload(vcpu);
2133 if (unlikely(r))
2134 goto out;
2135
2136 preempt_disable();
2137
2138 vmx_save_host_state(vmx);
2139 kvm_load_guest_fpu(vcpu);
2140
2141 /*
2142 * Loading guest fpu may have cleared host cr0.ts
2143 */
2144 vmcs_writel(HOST_CR0, read_cr0());
2145
2146 local_irq_disable();
2147
2148 if (signal_pending(current)) {
2149 local_irq_enable();
2150 preempt_enable();
2151 r = -EINTR;
2152 kvm_run->exit_reason = KVM_EXIT_INTR;
2153 ++vcpu->stat.signal_exits;
2154 goto out;
2155 }
2156
2157 if (irqchip_in_kernel(vcpu->kvm))
2158 vmx_intr_assist(vcpu);
2159 else if (!vcpu->mmio_read_completed)
2160 do_interrupt_requests(vcpu, kvm_run);
2161
2162 vcpu->guest_mode = 1;
2163 if (vcpu->requests)
2164 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
2165 vmx_flush_tlb(vcpu);
2166
2167 asm (
2168 /* Store host registers */
2169 #ifdef CONFIG_X86_64
2170 "push %%rax; push %%rbx; push %%rdx;"
2171 "push %%rsi; push %%rdi; push %%rbp;"
2172 "push %%r8; push %%r9; push %%r10; push %%r11;"
2173 "push %%r12; push %%r13; push %%r14; push %%r15;"
2174 "push %%rcx \n\t"
2175 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2176 #else
2177 "pusha; push %%ecx \n\t"
2178 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2179 #endif
2180 /* Check if vmlaunch of vmresume is needed */
2181 "cmp $0, %1 \n\t"
2182 /* Load guest registers. Don't clobber flags. */
2183 #ifdef CONFIG_X86_64
2184 "mov %c[cr2](%3), %%rax \n\t"
2185 "mov %%rax, %%cr2 \n\t"
2186 "mov %c[rax](%3), %%rax \n\t"
2187 "mov %c[rbx](%3), %%rbx \n\t"
2188 "mov %c[rdx](%3), %%rdx \n\t"
2189 "mov %c[rsi](%3), %%rsi \n\t"
2190 "mov %c[rdi](%3), %%rdi \n\t"
2191 "mov %c[rbp](%3), %%rbp \n\t"
2192 "mov %c[r8](%3), %%r8 \n\t"
2193 "mov %c[r9](%3), %%r9 \n\t"
2194 "mov %c[r10](%3), %%r10 \n\t"
2195 "mov %c[r11](%3), %%r11 \n\t"
2196 "mov %c[r12](%3), %%r12 \n\t"
2197 "mov %c[r13](%3), %%r13 \n\t"
2198 "mov %c[r14](%3), %%r14 \n\t"
2199 "mov %c[r15](%3), %%r15 \n\t"
2200 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2201 #else
2202 "mov %c[cr2](%3), %%eax \n\t"
2203 "mov %%eax, %%cr2 \n\t"
2204 "mov %c[rax](%3), %%eax \n\t"
2205 "mov %c[rbx](%3), %%ebx \n\t"
2206 "mov %c[rdx](%3), %%edx \n\t"
2207 "mov %c[rsi](%3), %%esi \n\t"
2208 "mov %c[rdi](%3), %%edi \n\t"
2209 "mov %c[rbp](%3), %%ebp \n\t"
2210 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2211 #endif
2212 /* Enter guest mode */
2213 "jne .Llaunched \n\t"
2214 ASM_VMX_VMLAUNCH "\n\t"
2215 "jmp .Lkvm_vmx_return \n\t"
2216 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2217 ".Lkvm_vmx_return: "
2218 /* Save guest registers, load host registers, keep flags */
2219 #ifdef CONFIG_X86_64
2220 "xchg %3, (%%rsp) \n\t"
2221 "mov %%rax, %c[rax](%3) \n\t"
2222 "mov %%rbx, %c[rbx](%3) \n\t"
2223 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2224 "mov %%rdx, %c[rdx](%3) \n\t"
2225 "mov %%rsi, %c[rsi](%3) \n\t"
2226 "mov %%rdi, %c[rdi](%3) \n\t"
2227 "mov %%rbp, %c[rbp](%3) \n\t"
2228 "mov %%r8, %c[r8](%3) \n\t"
2229 "mov %%r9, %c[r9](%3) \n\t"
2230 "mov %%r10, %c[r10](%3) \n\t"
2231 "mov %%r11, %c[r11](%3) \n\t"
2232 "mov %%r12, %c[r12](%3) \n\t"
2233 "mov %%r13, %c[r13](%3) \n\t"
2234 "mov %%r14, %c[r14](%3) \n\t"
2235 "mov %%r15, %c[r15](%3) \n\t"
2236 "mov %%cr2, %%rax \n\t"
2237 "mov %%rax, %c[cr2](%3) \n\t"
2238 "mov (%%rsp), %3 \n\t"
2239
2240 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2241 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2242 "pop %%rbp; pop %%rdi; pop %%rsi;"
2243 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2244 #else
2245 "xchg %3, (%%esp) \n\t"
2246 "mov %%eax, %c[rax](%3) \n\t"
2247 "mov %%ebx, %c[rbx](%3) \n\t"
2248 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2249 "mov %%edx, %c[rdx](%3) \n\t"
2250 "mov %%esi, %c[rsi](%3) \n\t"
2251 "mov %%edi, %c[rdi](%3) \n\t"
2252 "mov %%ebp, %c[rbp](%3) \n\t"
2253 "mov %%cr2, %%eax \n\t"
2254 "mov %%eax, %c[cr2](%3) \n\t"
2255 "mov (%%esp), %3 \n\t"
2256
2257 "pop %%ecx; popa \n\t"
2258 #endif
2259 "setbe %0 \n\t"
2260 : "=q" (fail)
2261 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2262 "c"(vcpu),
2263 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2264 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2265 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2266 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2267 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2268 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2269 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2270 #ifdef CONFIG_X86_64
2271 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2272 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2273 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2274 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2275 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2276 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2277 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2278 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2279 #endif
2280 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2281 : "cc", "memory" );
2282
2283 vcpu->guest_mode = 0;
2284 local_irq_enable();
2285
2286 ++vcpu->stat.exits;
2287
2288 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2289
2290 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2291 vmx->launched = 1;
2292
2293 preempt_enable();
2294
2295 if (unlikely(fail)) {
2296 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2297 kvm_run->fail_entry.hardware_entry_failure_reason
2298 = vmcs_read32(VM_INSTRUCTION_ERROR);
2299 r = 0;
2300 goto out;
2301 }
2302 /*
2303 * Profile KVM exit RIPs:
2304 */
2305 if (unlikely(prof_on == KVM_PROFILING))
2306 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2307
2308 r = kvm_handle_exit(kvm_run, vcpu);
2309 if (r > 0) {
2310 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2311 r = -EINTR;
2312 kvm_run->exit_reason = KVM_EXIT_INTR;
2313 ++vcpu->stat.request_irq_exits;
2314 goto out;
2315 }
2316 if (!need_resched()) {
2317 ++vcpu->stat.light_exits;
2318 goto again;
2319 }
2320 }
2321
2322 out:
2323 if (r > 0) {
2324 kvm_resched(vcpu);
2325 goto preempted;
2326 }
2327
2328 post_kvm_run_save(vcpu, kvm_run);
2329 return r;
2330 }
2331
2332 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2333 unsigned long addr,
2334 u32 err_code)
2335 {
2336 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2337
2338 ++vcpu->stat.pf_guest;
2339
2340 if (is_page_fault(vect_info)) {
2341 printk(KERN_DEBUG "inject_page_fault: "
2342 "double fault 0x%lx @ 0x%lx\n",
2343 addr, vmcs_readl(GUEST_RIP));
2344 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2345 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2346 DF_VECTOR |
2347 INTR_TYPE_EXCEPTION |
2348 INTR_INFO_DELIEVER_CODE_MASK |
2349 INTR_INFO_VALID_MASK);
2350 return;
2351 }
2352 vcpu->cr2 = addr;
2353 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2354 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2355 PF_VECTOR |
2356 INTR_TYPE_EXCEPTION |
2357 INTR_INFO_DELIEVER_CODE_MASK |
2358 INTR_INFO_VALID_MASK);
2359
2360 }
2361
2362 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2363 {
2364 struct vcpu_vmx *vmx = to_vmx(vcpu);
2365
2366 if (vmx->vmcs) {
2367 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2368 free_vmcs(vmx->vmcs);
2369 vmx->vmcs = NULL;
2370 }
2371 }
2372
2373 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2374 {
2375 struct vcpu_vmx *vmx = to_vmx(vcpu);
2376
2377 vmx_free_vmcs(vcpu);
2378 kfree(vmx->host_msrs);
2379 kfree(vmx->guest_msrs);
2380 kvm_vcpu_uninit(vcpu);
2381 kmem_cache_free(kvm_vcpu_cache, vmx);
2382 }
2383
2384 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2385 {
2386 int err;
2387 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2388 int cpu;
2389
2390 if (!vmx)
2391 return ERR_PTR(-ENOMEM);
2392
2393 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2394 if (err)
2395 goto free_vcpu;
2396
2397 if (irqchip_in_kernel(kvm)) {
2398 err = kvm_create_lapic(&vmx->vcpu);
2399 if (err < 0)
2400 goto free_vcpu;
2401 }
2402
2403 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2404 if (!vmx->guest_msrs) {
2405 err = -ENOMEM;
2406 goto uninit_vcpu;
2407 }
2408
2409 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2410 if (!vmx->host_msrs)
2411 goto free_guest_msrs;
2412
2413 vmx->vmcs = alloc_vmcs();
2414 if (!vmx->vmcs)
2415 goto free_msrs;
2416
2417 vmcs_clear(vmx->vmcs);
2418
2419 cpu = get_cpu();
2420 vmx_vcpu_load(&vmx->vcpu, cpu);
2421 err = vmx_vcpu_setup(vmx);
2422 vmx_vcpu_put(&vmx->vcpu);
2423 put_cpu();
2424 if (err)
2425 goto free_vmcs;
2426
2427 return &vmx->vcpu;
2428
2429 free_vmcs:
2430 free_vmcs(vmx->vmcs);
2431 free_msrs:
2432 kfree(vmx->host_msrs);
2433 free_guest_msrs:
2434 kfree(vmx->guest_msrs);
2435 uninit_vcpu:
2436 kvm_vcpu_uninit(&vmx->vcpu);
2437 free_vcpu:
2438 kmem_cache_free(kvm_vcpu_cache, vmx);
2439 return ERR_PTR(err);
2440 }
2441
2442 static void __init vmx_check_processor_compat(void *rtn)
2443 {
2444 struct vmcs_config vmcs_conf;
2445
2446 *(int *)rtn = 0;
2447 if (setup_vmcs_config(&vmcs_conf) < 0)
2448 *(int *)rtn = -EIO;
2449 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2450 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2451 smp_processor_id());
2452 *(int *)rtn = -EIO;
2453 }
2454 }
2455
2456 static struct kvm_arch_ops vmx_arch_ops = {
2457 .cpu_has_kvm_support = cpu_has_kvm_support,
2458 .disabled_by_bios = vmx_disabled_by_bios,
2459 .hardware_setup = hardware_setup,
2460 .hardware_unsetup = hardware_unsetup,
2461 .check_processor_compatibility = vmx_check_processor_compat,
2462 .hardware_enable = hardware_enable,
2463 .hardware_disable = hardware_disable,
2464
2465 .vcpu_create = vmx_create_vcpu,
2466 .vcpu_free = vmx_free_vcpu,
2467
2468 .vcpu_load = vmx_vcpu_load,
2469 .vcpu_put = vmx_vcpu_put,
2470 .vcpu_decache = vmx_vcpu_decache,
2471
2472 .set_guest_debug = set_guest_debug,
2473 .get_msr = vmx_get_msr,
2474 .set_msr = vmx_set_msr,
2475 .get_segment_base = vmx_get_segment_base,
2476 .get_segment = vmx_get_segment,
2477 .set_segment = vmx_set_segment,
2478 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2479 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2480 .set_cr0 = vmx_set_cr0,
2481 .set_cr3 = vmx_set_cr3,
2482 .set_cr4 = vmx_set_cr4,
2483 #ifdef CONFIG_X86_64
2484 .set_efer = vmx_set_efer,
2485 #endif
2486 .get_idt = vmx_get_idt,
2487 .set_idt = vmx_set_idt,
2488 .get_gdt = vmx_get_gdt,
2489 .set_gdt = vmx_set_gdt,
2490 .cache_regs = vcpu_load_rsp_rip,
2491 .decache_regs = vcpu_put_rsp_rip,
2492 .get_rflags = vmx_get_rflags,
2493 .set_rflags = vmx_set_rflags,
2494
2495 .tlb_flush = vmx_flush_tlb,
2496 .inject_page_fault = vmx_inject_page_fault,
2497
2498 .inject_gp = vmx_inject_gp,
2499
2500 .run = vmx_vcpu_run,
2501 .skip_emulated_instruction = skip_emulated_instruction,
2502 .patch_hypercall = vmx_patch_hypercall,
2503 };
2504
2505 static int __init vmx_init(void)
2506 {
2507 void *iova;
2508 int r;
2509
2510 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2511 if (!vmx_io_bitmap_a)
2512 return -ENOMEM;
2513
2514 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2515 if (!vmx_io_bitmap_b) {
2516 r = -ENOMEM;
2517 goto out;
2518 }
2519
2520 /*
2521 * Allow direct access to the PC debug port (it is often used for I/O
2522 * delays, but the vmexits simply slow things down).
2523 */
2524 iova = kmap(vmx_io_bitmap_a);
2525 memset(iova, 0xff, PAGE_SIZE);
2526 clear_bit(0x80, iova);
2527 kunmap(vmx_io_bitmap_a);
2528
2529 iova = kmap(vmx_io_bitmap_b);
2530 memset(iova, 0xff, PAGE_SIZE);
2531 kunmap(vmx_io_bitmap_b);
2532
2533 r = kvm_init_arch(&vmx_arch_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2534 if (r)
2535 goto out1;
2536
2537 return 0;
2538
2539 out1:
2540 __free_page(vmx_io_bitmap_b);
2541 out:
2542 __free_page(vmx_io_bitmap_a);
2543 return r;
2544 }
2545
2546 static void __exit vmx_exit(void)
2547 {
2548 __free_page(vmx_io_bitmap_b);
2549 __free_page(vmx_io_bitmap_a);
2550
2551 kvm_exit_arch();
2552 }
2553
2554 module_init(vmx_init)
2555 module_exit(vmx_exit)
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