drivers/mailbox/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 menuconfig MAILBOX
   3         bool "Mailbox Hardware Support"
   4         help
   5           Mailbox is a framework to control hardware communication between
   6           on-chip processors through queued messages and interrupt driven
   7           signals. Say Y if your platform supports hardware mailboxes.
   8
   9 if MAILBOX
  10
  11 config ARM_MHU
  12         tristate "ARM MHU Mailbox"
  13         depends on ARM_AMBA
  14         help
  15           Say Y here if you want to build the ARM MHU controller driver.
  16           The controller has 3 mailbox channels, the last of which can be
  17           used in Secure mode only.
  18
  19 config ARM_MHU_V2
  20         tristate "ARM MHUv2 Mailbox"
  21         depends on ARM_AMBA
  22         help
  23           Say Y here if you want to build the ARM MHUv2 controller driver,
  24           which provides unidirectional mailboxes between processing elements.
  25
  26 config IMX_MBOX
  27         tristate "i.MX Mailbox"
  28         depends on ARCH_MXC || COMPILE_TEST
  29         help
  30           Mailbox implementation for i.MX Messaging Unit (MU).
  31
  32 config PLATFORM_MHU
  33         tristate "Platform MHU Mailbox"
  34         depends on OF
  35         depends on HAS_IOMEM
  36         help
  37           Say Y here if you want to build a platform specific variant MHU
  38           controller driver.
  39           The controller has a maximum of 3 mailbox channels, the last of
  40           which can be used in Secure mode only.
  41
  42 config PL320_MBOX
  43         bool "ARM PL320 Mailbox"
  44         depends on ARM_AMBA
  45         help
  46           An implementation of the ARM PL320 Interprocessor Communication
  47           Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
  48           send short messages between Highbank's A9 cores and the EnergyCore
  49           Management Engine, primarily for cpufreq. Say Y here if you want
  50           to use the PL320 IPCM support.
  51
  52 config ARMADA_37XX_RWTM_MBOX
  53         tristate "Armada 37xx rWTM BIU Mailbox"
  54         depends on ARCH_MVEBU || COMPILE_TEST
  55         depends on OF
  56         help
  57           Mailbox implementation for communication with the the firmware
  58           running on the Cortex-M3 rWTM secure processor of the Armada 37xx
  59           SOC. Say Y here if you are building for such a device (for example
  60           the Turris Mox router).
  61
  62 config OMAP2PLUS_MBOX
  63         tristate "OMAP2+ Mailbox framework support"
  64         depends on ARCH_OMAP2PLUS || ARCH_K3
  65         help
  66           Mailbox implementation for OMAP family chips with hardware for
  67           interprocessor communication involving DSP, IVA1.0 and IVA2 in
  68           OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
  69           want to use OMAP2+ Mailbox framework support.
  70
  71 config OMAP_MBOX_KFIFO_SIZE
  72         int "Mailbox kfifo default buffer size (bytes)"
  73         depends on OMAP2PLUS_MBOX
  74         default 256
  75         help
  76           Specify the default size of mailbox's kfifo buffers (bytes).
  77           This can also be changed at runtime (via the mbox_kfifo_size
  78           module parameter).
  79
  80 config ROCKCHIP_MBOX
  81         bool "Rockchip Soc Integrated Mailbox Support"
  82         depends on ARCH_ROCKCHIP || COMPILE_TEST
  83         help
  84           This driver provides support for inter-processor communication
  85           between CPU cores and MCU processor on Some Rockchip SOCs.
  86           Please check it that the Soc you use have Mailbox hardware.
  87           Say Y here if you want to use the Rockchip Mailbox support.
  88
  89 config PCC
  90         bool "Platform Communication Channel Driver"
  91         depends on ACPI
  92         default n
  93         help
  94           ACPI 5.0+ spec defines a generic mode of communication
  95           between the OS and a platform such as the BMC. This medium
  96           (PCC) is typically used by CPPC (ACPI CPU Performance management),
  97           RAS (ACPI reliability protocol) and MPST (ACPI Memory power
  98           states). Select this driver if your platform implements the
  99           PCC clients mentioned above.
 100
 101 config ALTERA_MBOX
 102         tristate "Altera Mailbox"
 103         depends on HAS_IOMEM
 104         help
 105           An implementation of the Altera Mailbox soft core. It is used
 106           to send message between processors. Say Y here if you want to use the
 107           Altera mailbox support.
 108
 109 config BCM2835_MBOX
 110         tristate "BCM2835 Mailbox"
 111         depends on ARCH_BCM2835
 112         help
 113           An implementation of the BCM2385 Mailbox.  It is used to invoke
 114           the services of the Videocore. Say Y here if you want to use the
 115           BCM2835 Mailbox.
 116
 117 config STI_MBOX
 118         tristate "STI Mailbox framework support"
 119         depends on ARCH_STI && OF
 120         help
 121           Mailbox implementation for STMicroelectonics family chips with
 122           hardware for interprocessor communication.
 123
 124 config TI_MESSAGE_MANAGER
 125         tristate "Texas Instruments Message Manager Driver"
 126         depends on ARCH_KEYSTONE || ARCH_K3
 127         help
 128           An implementation of Message Manager slave driver for Keystone
 129           and K3 architecture SoCs from Texas Instruments. Message Manager
 130           is a communication entity found on few of Texas Instrument's keystone
 131           and K3 architecture SoCs. These may be used for communication between
 132           multiple processors within the SoC. Select this driver if your
 133           platform has support for the hardware block.
 134
 135 config HI3660_MBOX
 136         tristate "Hi3660 Mailbox" if EXPERT
 137         depends on (ARCH_HISI || COMPILE_TEST)
 138         depends on OF
 139         default ARCH_HISI
 140         help
 141           An implementation of the hi3660 mailbox. It is used to send message
 142           between application processors and other processors/MCU/DSP. Select
 143           Y here if you want to use Hi3660 mailbox controller.
 144
 145 config HI6220_MBOX
 146         tristate "Hi6220 Mailbox" if EXPERT
 147         depends on (ARCH_HISI || COMPILE_TEST)
 148         depends on OF
 149         default ARCH_HISI
 150         help
 151           An implementation of the hi6220 mailbox. It is used to send message
 152           between application processors and MCU. Say Y here if you want to
 153           build Hi6220 mailbox controller driver.
 154
 155 config MAILBOX_TEST
 156         tristate "Mailbox Test Client"
 157         depends on OF
 158         depends on HAS_IOMEM
 159         help
 160           Test client to help with testing new Controller driver
 161           implementations.
 162
 163 config POLARFIRE_SOC_MAILBOX
 164         tristate "PolarFire SoC (MPFS) Mailbox"
 165         depends on HAS_IOMEM
 166         depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
 167         help
 168           This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
 169
 170           To compile this driver as a module, choose M here. the
 171           module will be called mailbox-mpfs.
 172
 173           If unsure, say N.
 174
 175 config QCOM_APCS_IPC
 176         tristate "Qualcomm APCS IPC driver"
 177         depends on ARCH_QCOM || COMPILE_TEST
 178         help
 179           Say y here to enable support for the APCS IPC mailbox driver,
 180           providing an interface for invoking the inter-process communication
 181           signals from the application processor to other masters.
 182
 183 config TEGRA_HSP_MBOX
 184         bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
 185         depends on ARCH_TEGRA
 186         help
 187           The Tegra HSP driver is used for the interprocessor communication
 188           between different remote processors and host processors on Tegra186
 189           and later SoCs. Say Y here if you want to have this support.
 190           If unsure say N.
 191
 192 config XGENE_SLIMPRO_MBOX
 193         tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
 194         depends on ARCH_XGENE
 195         help
 196           An implementation of the APM X-Gene Interprocessor Communication
 197           Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
 198           It is used to send short messages between ARM64-bit cores and
 199           the SLIMpro Management Engine, primarily for PM. Say Y here if you
 200           want to use the APM X-Gene SLIMpro IPCM support.
 201
 202 config BCM_PDC_MBOX
 203         tristate "Broadcom FlexSparx DMA Mailbox"
 204         depends on ARCH_BCM_IPROC || COMPILE_TEST
 205         help
 206           Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
 207           which provides access to various offload engines on Broadcom
 208           SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
 209
 210 config BCM_FLEXRM_MBOX
 211         tristate "Broadcom FlexRM Mailbox"
 212         depends on ARM64
 213         depends on ARCH_BCM_IPROC || COMPILE_TEST
 214         select GENERIC_MSI_IRQ_DOMAIN
 215         default m if ARCH_BCM_IPROC
 216         help
 217           Mailbox implementation of the Broadcom FlexRM ring manager,
 218           which provides access to various offload engines on Broadcom
 219           SoCs. Say Y here if you want to use the Broadcom FlexRM.
 220
 221 config STM32_IPCC
 222         tristate "STM32 IPCC Mailbox"
 223         depends on MACH_STM32MP157 || COMPILE_TEST
 224         help
 225           Mailbox implementation for STMicroelectonics STM32 family chips
 226           with hardware for Inter-Processor Communication Controller (IPCC)
 227           between processors. Say Y here if you want to have this support.
 228
 229 config MTK_CMDQ_MBOX
 230         tristate "MediaTek CMDQ Mailbox Support"
 231         depends on ARCH_MEDIATEK || COMPILE_TEST
 232         select MTK_INFRACFG
 233         help
 234           Say yes here to add support for the MediaTek Command Queue (CMDQ)
 235           mailbox driver. The CMDQ is used to help read/write registers with
 236           critical time limitation, such as updating display configuration
 237           during the vblank.
 238
 239 config ZYNQMP_IPI_MBOX
 240         bool "Xilinx ZynqMP IPI Mailbox"
 241         depends on ARCH_ZYNQMP && OF
 242         help
 243           Say yes here to add support for Xilinx IPI mailbox driver.
 244           This mailbox driver is used to send notification or short message
 245           between processors with Xilinx ZynqMP IPI. It will place the
 246           message to the IPI buffer and will access the IPI control
 247           registers to kick the other processor or enquire status.
 248
 249 config SUN6I_MSGBOX
 250         tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
 251         depends on ARCH_SUNXI || COMPILE_TEST
 252         default ARCH_SUNXI
 253         help
 254           Mailbox implementation for the hardware message box present in
 255           various Allwinner SoCs. This mailbox is used for communication
 256           between the application CPUs and the power management coprocessor.
 257
 258 config SPRD_MBOX
 259         tristate "Spreadtrum Mailbox"
 260         depends on ARCH_SPRD || COMPILE_TEST
 261         help
 262           Mailbox driver implementation for the Spreadtrum platform. It is used
 263           to send message between application processors and MCU. Say Y here if
 264           you want to build the Spreatrum mailbox controller driver.
 265
 266 config QCOM_IPCC
 267         tristate "Qualcomm Technologies, Inc. IPCC driver"
 268         depends on ARCH_QCOM || COMPILE_TEST
 269         help
 270           Qualcomm Technologies, Inc. Inter-Processor Communication Controller
 271           (IPCC) driver for MSM devices. The driver provides mailbox support for
 272           sending interrupts to the clients. On the other hand, the driver also
 273           acts as an interrupt controller for receiving interrupts from clients.
 274           Say Y here if you want to build this driver.
 275
 276 endif