1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
7 #include <linux/firmware/imx/ipc.h>
8 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/mailbox_controller.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/slab.h>
17 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
18 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
19 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
20 #define IMX_MU_xSR_BRDIP BIT(9)
22 /* General Purpose Interrupt Enable */
23 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
24 /* Receive Interrupt Enable */
25 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
26 /* Transmit Interrupt Enable */
27 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
28 /* General Purpose Interrupt Request */
29 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
31 #define IMX_MU_CHANS 16
32 /* TX0/RX0/RXDB[0-3] */
33 #define IMX_MU_SCU_CHANS 6
34 #define IMX_MU_CHAN_NAME_SIZE 20
36 enum imx_mu_chan_type
{
37 IMX_MU_TYPE_TX
, /* Tx */
38 IMX_MU_TYPE_RX
, /* Rx */
39 IMX_MU_TYPE_TXDB
, /* Tx doorbell */
40 IMX_MU_TYPE_RXDB
, /* Rx doorbell */
43 struct imx_sc_rpc_msg_max
{
44 struct imx_sc_rpc_msg hdr
;
48 struct imx_mu_con_priv
{
50 char irq_desc
[IMX_MU_CHAN_NAME_SIZE
];
51 enum imx_mu_chan_type type
;
52 struct mbox_chan
*chan
;
53 struct tasklet_struct txdb_tasklet
;
59 spinlock_t xcr_lock
; /* control register lock */
61 struct mbox_controller mbox
;
62 struct mbox_chan mbox_chans
[IMX_MU_CHANS
];
64 struct imx_mu_con_priv con_priv
[IMX_MU_CHANS
];
65 const struct imx_mu_dcfg
*dcfg
;
73 int (*tx
)(struct imx_mu_priv
*priv
, struct imx_mu_con_priv
*cp
, void *data
);
74 int (*rx
)(struct imx_mu_priv
*priv
, struct imx_mu_con_priv
*cp
);
75 void (*init
)(struct imx_mu_priv
*priv
);
76 u32 xTR
[4]; /* Transmit Registers */
77 u32 xRR
[4]; /* Receive Registers */
78 u32 xSR
; /* Status Register */
79 u32 xCR
; /* Control Register */
82 static struct imx_mu_priv
*to_imx_mu_priv(struct mbox_controller
*mbox
)
84 return container_of(mbox
, struct imx_mu_priv
, mbox
);
87 static void imx_mu_write(struct imx_mu_priv
*priv
, u32 val
, u32 offs
)
89 iowrite32(val
, priv
->base
+ offs
);
92 static u32
imx_mu_read(struct imx_mu_priv
*priv
, u32 offs
)
94 return ioread32(priv
->base
+ offs
);
97 static u32
imx_mu_xcr_rmw(struct imx_mu_priv
*priv
, u32 set
, u32 clr
)
102 spin_lock_irqsave(&priv
->xcr_lock
, flags
);
103 val
= imx_mu_read(priv
, priv
->dcfg
->xCR
);
106 imx_mu_write(priv
, val
, priv
->dcfg
->xCR
);
107 spin_unlock_irqrestore(&priv
->xcr_lock
, flags
);
112 static int imx_mu_generic_tx(struct imx_mu_priv
*priv
,
113 struct imx_mu_con_priv
*cp
,
120 imx_mu_write(priv
, *arg
, priv
->dcfg
->xTR
[cp
->idx
]);
121 imx_mu_xcr_rmw(priv
, IMX_MU_xCR_TIEn(cp
->idx
), 0);
123 case IMX_MU_TYPE_TXDB
:
124 imx_mu_xcr_rmw(priv
, IMX_MU_xCR_GIRn(cp
->idx
), 0);
125 tasklet_schedule(&cp
->txdb_tasklet
);
128 dev_warn_ratelimited(priv
->dev
, "Send data on wrong channel type: %d\n", cp
->type
);
135 static int imx_mu_generic_rx(struct imx_mu_priv
*priv
,
136 struct imx_mu_con_priv
*cp
)
140 dat
= imx_mu_read(priv
, priv
->dcfg
->xRR
[cp
->idx
]);
141 mbox_chan_received_data(cp
->chan
, (void *)&dat
);
146 static int imx_mu_scu_tx(struct imx_mu_priv
*priv
,
147 struct imx_mu_con_priv
*cp
,
150 struct imx_sc_rpc_msg_max
*msg
= data
;
157 if (msg
->hdr
.size
> sizeof(*msg
)) {
159 * The real message size can be different to
160 * struct imx_sc_rpc_msg_max size
162 dev_err(priv
->dev
, "Exceed max msg size (%zu) on TX, got: %i\n", sizeof(*msg
), msg
->hdr
.size
);
166 for (i
= 0; i
< 4 && i
< msg
->hdr
.size
; i
++)
167 imx_mu_write(priv
, *arg
++, priv
->dcfg
->xTR
[i
% 4]);
168 for (; i
< msg
->hdr
.size
; i
++) {
169 ret
= readl_poll_timeout(priv
->base
+ priv
->dcfg
->xSR
,
171 xsr
& IMX_MU_xSR_TEn(i
% 4),
174 dev_err(priv
->dev
, "Send data index: %d timeout\n", i
);
177 imx_mu_write(priv
, *arg
++, priv
->dcfg
->xTR
[i
% 4]);
180 imx_mu_xcr_rmw(priv
, IMX_MU_xCR_TIEn(cp
->idx
), 0);
183 dev_warn_ratelimited(priv
->dev
, "Send data on wrong channel type: %d\n", cp
->type
);
190 static int imx_mu_scu_rx(struct imx_mu_priv
*priv
,
191 struct imx_mu_con_priv
*cp
)
193 struct imx_sc_rpc_msg_max msg
;
194 u32
*data
= (u32
*)&msg
;
198 imx_mu_xcr_rmw(priv
, 0, IMX_MU_xCR_RIEn(0));
199 *data
++ = imx_mu_read(priv
, priv
->dcfg
->xRR
[0]);
201 if (msg
.hdr
.size
> sizeof(msg
)) {
202 dev_err(priv
->dev
, "Exceed max msg size (%zu) on RX, got: %i\n",
203 sizeof(msg
), msg
.hdr
.size
);
207 for (i
= 1; i
< msg
.hdr
.size
; i
++) {
208 ret
= readl_poll_timeout(priv
->base
+ priv
->dcfg
->xSR
, xsr
,
209 xsr
& IMX_MU_xSR_RFn(i
% 4), 0, 100);
211 dev_err(priv
->dev
, "timeout read idx %d\n", i
);
214 *data
++ = imx_mu_read(priv
, priv
->dcfg
->xRR
[i
% 4]);
217 imx_mu_xcr_rmw(priv
, IMX_MU_xCR_RIEn(0), 0);
218 mbox_chan_received_data(cp
->chan
, (void *)&msg
);
223 static void imx_mu_txdb_tasklet(unsigned long data
)
225 struct imx_mu_con_priv
*cp
= (struct imx_mu_con_priv
*)data
;
227 mbox_chan_txdone(cp
->chan
, 0);
230 static irqreturn_t
imx_mu_isr(int irq
, void *p
)
232 struct mbox_chan
*chan
= p
;
233 struct imx_mu_priv
*priv
= to_imx_mu_priv(chan
->mbox
);
234 struct imx_mu_con_priv
*cp
= chan
->con_priv
;
237 ctrl
= imx_mu_read(priv
, priv
->dcfg
->xCR
);
238 val
= imx_mu_read(priv
, priv
->dcfg
->xSR
);
242 val
&= IMX_MU_xSR_TEn(cp
->idx
) &
243 (ctrl
& IMX_MU_xCR_TIEn(cp
->idx
));
246 val
&= IMX_MU_xSR_RFn(cp
->idx
) &
247 (ctrl
& IMX_MU_xCR_RIEn(cp
->idx
));
249 case IMX_MU_TYPE_RXDB
:
250 val
&= IMX_MU_xSR_GIPn(cp
->idx
) &
251 (ctrl
& IMX_MU_xCR_GIEn(cp
->idx
));
260 if (val
== IMX_MU_xSR_TEn(cp
->idx
)) {
261 imx_mu_xcr_rmw(priv
, 0, IMX_MU_xCR_TIEn(cp
->idx
));
262 mbox_chan_txdone(chan
, 0);
263 } else if (val
== IMX_MU_xSR_RFn(cp
->idx
)) {
264 priv
->dcfg
->rx(priv
, cp
);
265 } else if (val
== IMX_MU_xSR_GIPn(cp
->idx
)) {
266 imx_mu_write(priv
, IMX_MU_xSR_GIPn(cp
->idx
), priv
->dcfg
->xSR
);
267 mbox_chan_received_data(chan
, NULL
);
269 dev_warn_ratelimited(priv
->dev
, "Not handled interrupt\n");
276 static int imx_mu_send_data(struct mbox_chan
*chan
, void *data
)
278 struct imx_mu_priv
*priv
= to_imx_mu_priv(chan
->mbox
);
279 struct imx_mu_con_priv
*cp
= chan
->con_priv
;
281 return priv
->dcfg
->tx(priv
, cp
, data
);
284 static int imx_mu_startup(struct mbox_chan
*chan
)
286 struct imx_mu_priv
*priv
= to_imx_mu_priv(chan
->mbox
);
287 struct imx_mu_con_priv
*cp
= chan
->con_priv
;
290 if (cp
->type
== IMX_MU_TYPE_TXDB
) {
291 /* Tx doorbell don't have ACK support */
292 tasklet_init(&cp
->txdb_tasklet
, imx_mu_txdb_tasklet
,
297 ret
= request_irq(priv
->irq
, imx_mu_isr
, IRQF_SHARED
|
298 IRQF_NO_SUSPEND
, cp
->irq_desc
, chan
);
301 "Unable to acquire IRQ %d\n", priv
->irq
);
307 imx_mu_xcr_rmw(priv
, IMX_MU_xCR_RIEn(cp
->idx
), 0);
309 case IMX_MU_TYPE_RXDB
:
310 imx_mu_xcr_rmw(priv
, IMX_MU_xCR_GIEn(cp
->idx
), 0);
319 static void imx_mu_shutdown(struct mbox_chan
*chan
)
321 struct imx_mu_priv
*priv
= to_imx_mu_priv(chan
->mbox
);
322 struct imx_mu_con_priv
*cp
= chan
->con_priv
;
324 if (cp
->type
== IMX_MU_TYPE_TXDB
) {
325 tasklet_kill(&cp
->txdb_tasklet
);
331 imx_mu_xcr_rmw(priv
, 0, IMX_MU_xCR_TIEn(cp
->idx
));
334 imx_mu_xcr_rmw(priv
, 0, IMX_MU_xCR_RIEn(cp
->idx
));
336 case IMX_MU_TYPE_RXDB
:
337 imx_mu_xcr_rmw(priv
, 0, IMX_MU_xCR_GIEn(cp
->idx
));
343 free_irq(priv
->irq
, chan
);
346 static const struct mbox_chan_ops imx_mu_ops
= {
347 .send_data
= imx_mu_send_data
,
348 .startup
= imx_mu_startup
,
349 .shutdown
= imx_mu_shutdown
,
352 static struct mbox_chan
*imx_mu_scu_xlate(struct mbox_controller
*mbox
,
353 const struct of_phandle_args
*sp
)
357 if (sp
->args_count
!= 2) {
358 dev_err(mbox
->dev
, "Invalid argument count %d\n", sp
->args_count
);
359 return ERR_PTR(-EINVAL
);
362 type
= sp
->args
[0]; /* channel type */
363 idx
= sp
->args
[1]; /* index */
369 dev_err(mbox
->dev
, "Invalid chan idx: %d\n", idx
);
372 case IMX_MU_TYPE_RXDB
:
376 dev_err(mbox
->dev
, "Invalid chan type: %d\n", type
);
380 if (chan
>= mbox
->num_chans
) {
381 dev_err(mbox
->dev
, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan
, type
, idx
);
382 return ERR_PTR(-EINVAL
);
385 return &mbox
->chans
[chan
];
388 static struct mbox_chan
* imx_mu_xlate(struct mbox_controller
*mbox
,
389 const struct of_phandle_args
*sp
)
393 if (sp
->args_count
!= 2) {
394 dev_err(mbox
->dev
, "Invalid argument count %d\n", sp
->args_count
);
395 return ERR_PTR(-EINVAL
);
398 type
= sp
->args
[0]; /* channel type */
399 idx
= sp
->args
[1]; /* index */
400 chan
= type
* 4 + idx
;
402 if (chan
>= mbox
->num_chans
) {
403 dev_err(mbox
->dev
, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan
, type
, idx
);
404 return ERR_PTR(-EINVAL
);
407 return &mbox
->chans
[chan
];
410 static void imx_mu_init_generic(struct imx_mu_priv
*priv
)
414 for (i
= 0; i
< IMX_MU_CHANS
; i
++) {
415 struct imx_mu_con_priv
*cp
= &priv
->con_priv
[i
];
419 cp
->chan
= &priv
->mbox_chans
[i
];
420 priv
->mbox_chans
[i
].con_priv
= cp
;
421 snprintf(cp
->irq_desc
, sizeof(cp
->irq_desc
),
422 "imx_mu_chan[%i-%i]", cp
->type
, cp
->idx
);
425 priv
->mbox
.num_chans
= IMX_MU_CHANS
;
426 priv
->mbox
.of_xlate
= imx_mu_xlate
;
431 /* Set default MU configuration */
432 imx_mu_write(priv
, 0, priv
->dcfg
->xCR
);
435 static void imx_mu_init_scu(struct imx_mu_priv
*priv
)
439 for (i
= 0; i
< IMX_MU_SCU_CHANS
; i
++) {
440 struct imx_mu_con_priv
*cp
= &priv
->con_priv
[i
];
442 cp
->idx
= i
< 2 ? 0 : i
- 2;
443 cp
->type
= i
< 2 ? i
: IMX_MU_TYPE_RXDB
;
444 cp
->chan
= &priv
->mbox_chans
[i
];
445 priv
->mbox_chans
[i
].con_priv
= cp
;
446 snprintf(cp
->irq_desc
, sizeof(cp
->irq_desc
),
447 "imx_mu_chan[%i-%i]", cp
->type
, cp
->idx
);
450 priv
->mbox
.num_chans
= IMX_MU_SCU_CHANS
;
451 priv
->mbox
.of_xlate
= imx_mu_scu_xlate
;
453 /* Set default MU configuration */
454 imx_mu_write(priv
, 0, priv
->dcfg
->xCR
);
457 static int imx_mu_probe(struct platform_device
*pdev
)
459 struct device
*dev
= &pdev
->dev
;
460 struct device_node
*np
= dev
->of_node
;
461 struct imx_mu_priv
*priv
;
462 const struct imx_mu_dcfg
*dcfg
;
465 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
471 priv
->base
= devm_platform_ioremap_resource(pdev
, 0);
472 if (IS_ERR(priv
->base
))
473 return PTR_ERR(priv
->base
);
475 priv
->irq
= platform_get_irq(pdev
, 0);
479 dcfg
= of_device_get_match_data(dev
);
484 priv
->clk
= devm_clk_get(dev
, NULL
);
485 if (IS_ERR(priv
->clk
)) {
486 if (PTR_ERR(priv
->clk
) != -ENOENT
)
487 return PTR_ERR(priv
->clk
);
492 ret
= clk_prepare_enable(priv
->clk
);
494 dev_err(dev
, "Failed to enable clock\n");
498 priv
->side_b
= of_property_read_bool(np
, "fsl,mu-side-b");
500 priv
->dcfg
->init(priv
);
502 spin_lock_init(&priv
->xcr_lock
);
504 priv
->mbox
.dev
= dev
;
505 priv
->mbox
.ops
= &imx_mu_ops
;
506 priv
->mbox
.chans
= priv
->mbox_chans
;
507 priv
->mbox
.txdone_irq
= true;
509 platform_set_drvdata(pdev
, priv
);
511 return devm_mbox_controller_register(dev
, &priv
->mbox
);
514 static int imx_mu_remove(struct platform_device
*pdev
)
516 struct imx_mu_priv
*priv
= platform_get_drvdata(pdev
);
518 clk_disable_unprepare(priv
->clk
);
523 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx
= {
524 .tx
= imx_mu_generic_tx
,
525 .rx
= imx_mu_generic_rx
,
526 .init
= imx_mu_init_generic
,
527 .xTR
= {0x0, 0x4, 0x8, 0xc},
528 .xRR
= {0x10, 0x14, 0x18, 0x1c},
533 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp
= {
534 .tx
= imx_mu_generic_tx
,
535 .rx
= imx_mu_generic_rx
,
536 .init
= imx_mu_init_generic
,
537 .xTR
= {0x20, 0x24, 0x28, 0x2c},
538 .xRR
= {0x40, 0x44, 0x48, 0x4c},
543 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu
= {
546 .init
= imx_mu_init_scu
,
547 .xTR
= {0x0, 0x4, 0x8, 0xc},
548 .xRR
= {0x10, 0x14, 0x18, 0x1c},
553 static const struct of_device_id imx_mu_dt_ids
[] = {
554 { .compatible
= "fsl,imx7ulp-mu", .data
= &imx_mu_cfg_imx7ulp
},
555 { .compatible
= "fsl,imx6sx-mu", .data
= &imx_mu_cfg_imx6sx
},
556 { .compatible
= "fsl,imx8-mu-scu", .data
= &imx_mu_cfg_imx8_scu
},
559 MODULE_DEVICE_TABLE(of
, imx_mu_dt_ids
);
561 static struct platform_driver imx_mu_driver
= {
562 .probe
= imx_mu_probe
,
563 .remove
= imx_mu_remove
,
566 .of_match_table
= imx_mu_dt_ids
,
569 module_platform_driver(imx_mu_driver
);
571 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
572 MODULE_DESCRIPTION("Message Unit driver for i.MX");
573 MODULE_LICENSE("GPL v2");