drivers/mailbox/tegra-hsp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/delay.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/io.h>
   9 #include <linux/mailbox_controller.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm.h>
  14 #include <linux/slab.h>
  15
  16 #include <soc/tegra/fuse.h>
  17
  18 #include <dt-bindings/mailbox/tegra186-hsp.h>
  19
  20 #include "mailbox.h"
  21
  22 #define HSP_INT_IE(x)           (0x100 + ((x) * 4))
  23 #define HSP_INT_IV              0x300
  24 #define HSP_INT_IR              0x304
  25
  26 #define HSP_INT_EMPTY_SHIFT     0
  27 #define HSP_INT_EMPTY_MASK      0xff
  28 #define HSP_INT_FULL_SHIFT      8
  29 #define HSP_INT_FULL_MASK       0xff
  30
  31 #define HSP_INT_DIMENSIONING    0x380
  32 #define HSP_nSM_SHIFT           0
  33 #define HSP_nSS_SHIFT           4
  34 #define HSP_nAS_SHIFT           8
  35 #define HSP_nDB_SHIFT           12
  36 #define HSP_nSI_SHIFT           16
  37 #define HSP_nINT_MASK           0xf
  38
  39 #define HSP_DB_TRIGGER  0x0
  40 #define HSP_DB_ENABLE   0x4
  41 #define HSP_DB_RAW      0x8
  42 #define HSP_DB_PENDING  0xc
  43
  44 #define HSP_SM_SHRD_MBOX        0x0
  45 #define HSP_SM_SHRD_MBOX_FULL   BIT(31)
  46 #define HSP_SM_SHRD_MBOX_FULL_INT_IE    0x04
  47 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE   0x08
  48
  49 #define HSP_DB_CCPLEX           1
  50 #define HSP_DB_BPMP             3
  51 #define HSP_DB_MAX              7
  52
  53 struct tegra_hsp_channel;
  54 struct tegra_hsp;
  55
  56 struct tegra_hsp_channel {
  57         struct tegra_hsp *hsp;
  58         struct mbox_chan *chan;
  59         void __iomem *regs;
  60 };
  61
  62 struct tegra_hsp_doorbell {
  63         struct tegra_hsp_channel channel;
  64         struct list_head list;
  65         const char *name;
  66         unsigned int master;
  67         unsigned int index;
  68 };
  69
  70 struct tegra_hsp_mailbox {
  71         struct tegra_hsp_channel channel;
  72         unsigned int index;
  73         bool producer;
  74 };
  75
  76 struct tegra_hsp_db_map {
  77         const char *name;
  78         unsigned int master;
  79         unsigned int index;
  80 };
  81
  82 struct tegra_hsp_soc {
  83         const struct tegra_hsp_db_map *map;
  84         bool has_per_mb_ie;
  85 };
  86
  87 struct tegra_hsp {
  88         struct device *dev;
  89         const struct tegra_hsp_soc *soc;
  90         struct mbox_controller mbox_db;
  91         struct mbox_controller mbox_sm;
  92         void __iomem *regs;
  93         unsigned int doorbell_irq;
  94         unsigned int *shared_irqs;
  95         unsigned int shared_irq;
  96         unsigned int num_sm;
  97         unsigned int num_as;
  98         unsigned int num_ss;
  99         unsigned int num_db;
 100         unsigned int num_si;
 101         spinlock_t lock;
 102
 103         struct list_head doorbells;
 104         struct tegra_hsp_mailbox *mailboxes;
 105
 106         unsigned long mask;
 107 };
 108
 109 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
 110 {
 111         return readl(hsp->regs + offset);
 112 }
 113
 114 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
 115                                     unsigned int offset)
 116 {
 117         writel(value, hsp->regs + offset);
 118 }
 119
 120 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
 121                                           unsigned int offset)
 122 {
 123         return readl(channel->regs + offset);
 124 }
 125
 126 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
 127                                             u32 value, unsigned int offset)
 128 {
 129         writel(value, channel->regs + offset);
 130 }
 131
 132 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
 133 {
 134         u32 value;
 135
 136         value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
 137
 138         return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
 139 }
 140
 141 static struct tegra_hsp_doorbell *
 142 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
 143 {
 144         struct tegra_hsp_doorbell *entry;
 145
 146         list_for_each_entry(entry, &hsp->doorbells, list)
 147                 if (entry->master == master)
 148                         return entry;
 149
 150         return NULL;
 151 }
 152
 153 static struct tegra_hsp_doorbell *
 154 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
 155 {
 156         struct tegra_hsp_doorbell *db;
 157         unsigned long flags;
 158
 159         spin_lock_irqsave(&hsp->lock, flags);
 160         db = __tegra_hsp_doorbell_get(hsp, master);
 161         spin_unlock_irqrestore(&hsp->lock, flags);
 162
 163         return db;
 164 }
 165
 166 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
 167 {
 168         struct tegra_hsp *hsp = data;
 169         struct tegra_hsp_doorbell *db;
 170         unsigned long master, value;
 171
 172         db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
 173         if (!db)
 174                 return IRQ_NONE;
 175
 176         value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
 177         tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
 178
 179         spin_lock(&hsp->lock);
 180
 181         for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
 182                 struct tegra_hsp_doorbell *db;
 183
 184                 db = __tegra_hsp_doorbell_get(hsp, master);
 185                 /*
 186                  * Depending on the bootloader chain, the CCPLEX doorbell will
 187                  * have some doorbells enabled, which means that requesting an
 188                  * interrupt will immediately fire.
 189                  *
 190                  * In that case, db->channel.chan will still be NULL here and
 191                  * cause a crash if not properly guarded.
 192                  *
 193                  * It remains to be seen if ignoring the doorbell in that case
 194                  * is the correct solution.
 195                  */
 196                 if (db && db->channel.chan)
 197                         mbox_chan_received_data(db->channel.chan, NULL);
 198         }
 199
 200         spin_unlock(&hsp->lock);
 201
 202         return IRQ_HANDLED;
 203 }
 204
 205 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
 206 {
 207         struct tegra_hsp *hsp = data;
 208         unsigned long bit, mask;
 209         u32 status, value;
 210         void *msg;
 211
 212         status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
 213
 214         /* process EMPTY interrupts first */
 215         mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
 216
 217         for_each_set_bit(bit, &mask, hsp->num_sm) {
 218                 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
 219
 220                 if (mb->producer) {
 221                         /*
 222                          * Disable EMPTY interrupts until data is sent with
 223                          * the next message. These interrupts are level-
 224                          * triggered, so if we kept them enabled they would
 225                          * constantly trigger until we next write data into
 226                          * the message.
 227                          */
 228                         spin_lock(&hsp->lock);
 229
 230                         hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 231                         tegra_hsp_writel(hsp, hsp->mask,
 232                                          HSP_INT_IE(hsp->shared_irq));
 233
 234                         spin_unlock(&hsp->lock);
 235
 236                         mbox_chan_txdone(mb->channel.chan, 0);
 237                 }
 238         }
 239
 240         /* process FULL interrupts */
 241         mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
 242
 243         for_each_set_bit(bit, &mask, hsp->num_sm) {
 244                 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
 245
 246                 if (!mb->producer) {
 247                         value = tegra_hsp_channel_readl(&mb->channel,
 248                                                         HSP_SM_SHRD_MBOX);
 249                         value &= ~HSP_SM_SHRD_MBOX_FULL;
 250                         msg = (void *)(unsigned long)value;
 251                         mbox_chan_received_data(mb->channel.chan, msg);
 252
 253                         /*
 254                          * Need to clear all bits here since some producers,
 255                          * such as TCU, depend on fields in the register
 256                          * getting cleared by the consumer.
 257                          *
 258                          * The mailbox API doesn't give the consumers a way
 259                          * of doing that explicitly, so we have to make sure
 260                          * we cover all possible cases.
 261                          */
 262                         tegra_hsp_channel_writel(&mb->channel, 0x0,
 263                                                  HSP_SM_SHRD_MBOX);
 264                 }
 265         }
 266
 267         return IRQ_HANDLED;
 268 }
 269
 270 static struct tegra_hsp_channel *
 271 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
 272                           unsigned int master, unsigned int index)
 273 {
 274         struct tegra_hsp_doorbell *db;
 275         unsigned int offset;
 276         unsigned long flags;
 277
 278         db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
 279         if (!db)
 280                 return ERR_PTR(-ENOMEM);
 281
 282         offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
 283         offset += index * 0x100;
 284
 285         db->channel.regs = hsp->regs + offset;
 286         db->channel.hsp = hsp;
 287
 288         db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
 289         db->master = master;
 290         db->index = index;
 291
 292         spin_lock_irqsave(&hsp->lock, flags);
 293         list_add_tail(&db->list, &hsp->doorbells);
 294         spin_unlock_irqrestore(&hsp->lock, flags);
 295
 296         return &db->channel;
 297 }
 298
 299 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
 300 {
 301         struct tegra_hsp_doorbell *db = chan->con_priv;
 302
 303         tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
 304
 305         return 0;
 306 }
 307
 308 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
 309 {
 310         struct tegra_hsp_doorbell *db = chan->con_priv;
 311         struct tegra_hsp *hsp = db->channel.hsp;
 312         struct tegra_hsp_doorbell *ccplex;
 313         unsigned long flags;
 314         u32 value;
 315
 316         if (db->master >= chan->mbox->num_chans) {
 317                 dev_err(chan->mbox->dev,
 318                         "invalid master ID %u for HSP channel\n",
 319                         db->master);
 320                 return -EINVAL;
 321         }
 322
 323         ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
 324         if (!ccplex)
 325                 return -ENODEV;
 326
 327         /*
 328          * On simulation platforms the BPMP hasn't had a chance yet to mark
 329          * the doorbell as ringable by the CCPLEX, so we want to skip extra
 330          * checks here.
 331          */
 332         if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
 333                 return -ENODEV;
 334
 335         spin_lock_irqsave(&hsp->lock, flags);
 336
 337         value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
 338         value |= BIT(db->master);
 339         tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
 340
 341         spin_unlock_irqrestore(&hsp->lock, flags);
 342
 343         return 0;
 344 }
 345
 346 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
 347 {
 348         struct tegra_hsp_doorbell *db = chan->con_priv;
 349         struct tegra_hsp *hsp = db->channel.hsp;
 350         struct tegra_hsp_doorbell *ccplex;
 351         unsigned long flags;
 352         u32 value;
 353
 354         ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
 355         if (!ccplex)
 356                 return;
 357
 358         spin_lock_irqsave(&hsp->lock, flags);
 359
 360         value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
 361         value &= ~BIT(db->master);
 362         tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
 363
 364         spin_unlock_irqrestore(&hsp->lock, flags);
 365 }
 366
 367 static const struct mbox_chan_ops tegra_hsp_db_ops = {
 368         .send_data = tegra_hsp_doorbell_send_data,
 369         .startup = tegra_hsp_doorbell_startup,
 370         .shutdown = tegra_hsp_doorbell_shutdown,
 371 };
 372
 373 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
 374 {
 375         struct tegra_hsp_mailbox *mb = chan->con_priv;
 376         struct tegra_hsp *hsp = mb->channel.hsp;
 377         unsigned long flags;
 378         u32 value;
 379
 380         if (WARN_ON(!mb->producer))
 381                 return -EPERM;
 382
 383         /* copy data and mark mailbox full */
 384         value = (u32)(unsigned long)data;
 385         value |= HSP_SM_SHRD_MBOX_FULL;
 386
 387         tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
 388
 389         /* enable EMPTY interrupt for the shared mailbox */
 390         spin_lock_irqsave(&hsp->lock, flags);
 391
 392         hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 393         tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
 394
 395         spin_unlock_irqrestore(&hsp->lock, flags);
 396
 397         return 0;
 398 }
 399
 400 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
 401                                    unsigned long timeout)
 402 {
 403         struct tegra_hsp_mailbox *mb = chan->con_priv;
 404         struct tegra_hsp_channel *ch = &mb->channel;
 405         u32 value;
 406
 407         timeout = jiffies + msecs_to_jiffies(timeout);
 408
 409         while (time_before(jiffies, timeout)) {
 410                 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
 411                 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
 412                         mbox_chan_txdone(chan, 0);
 413                         return 0;
 414                 }
 415
 416                 udelay(1);
 417         }
 418
 419         return -ETIME;
 420 }
 421
 422 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
 423 {
 424         struct tegra_hsp_mailbox *mb = chan->con_priv;
 425         struct tegra_hsp_channel *ch = &mb->channel;
 426         struct tegra_hsp *hsp = mb->channel.hsp;
 427         unsigned long flags;
 428
 429         chan->txdone_method = TXDONE_BY_IRQ;
 430
 431         /*
 432          * Shared mailboxes start out as consumers by default. FULL and EMPTY
 433          * interrupts are coalesced at the same shared interrupt.
 434          *
 435          * Keep EMPTY interrupts disabled at startup and only enable them when
 436          * the mailbox is actually full. This is required because the FULL and
 437          * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
 438          * enabled all the time would cause an interrupt storm while mailboxes
 439          * are idle.
 440          */
 441
 442         spin_lock_irqsave(&hsp->lock, flags);
 443
 444         if (mb->producer)
 445                 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 446         else
 447                 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
 448
 449         tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
 450
 451         spin_unlock_irqrestore(&hsp->lock, flags);
 452
 453         if (hsp->soc->has_per_mb_ie) {
 454                 if (mb->producer)
 455                         tegra_hsp_channel_writel(ch, 0x0,
 456                                                  HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
 457                 else
 458                         tegra_hsp_channel_writel(ch, 0x1,
 459                                                  HSP_SM_SHRD_MBOX_FULL_INT_IE);
 460         }
 461
 462         return 0;
 463 }
 464
 465 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
 466 {
 467         struct tegra_hsp_mailbox *mb = chan->con_priv;
 468         struct tegra_hsp_channel *ch = &mb->channel;
 469         struct tegra_hsp *hsp = mb->channel.hsp;
 470         unsigned long flags;
 471
 472         if (hsp->soc->has_per_mb_ie) {
 473                 if (mb->producer)
 474                         tegra_hsp_channel_writel(ch, 0x0,
 475                                                  HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
 476                 else
 477                         tegra_hsp_channel_writel(ch, 0x0,
 478                                                  HSP_SM_SHRD_MBOX_FULL_INT_IE);
 479         }
 480
 481         spin_lock_irqsave(&hsp->lock, flags);
 482
 483         if (mb->producer)
 484                 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 485         else
 486                 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
 487
 488         tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
 489
 490         spin_unlock_irqrestore(&hsp->lock, flags);
 491 }
 492
 493 static const struct mbox_chan_ops tegra_hsp_sm_ops = {
 494         .send_data = tegra_hsp_mailbox_send_data,
 495         .flush = tegra_hsp_mailbox_flush,
 496         .startup = tegra_hsp_mailbox_startup,
 497         .shutdown = tegra_hsp_mailbox_shutdown,
 498 };
 499
 500 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
 501                                             const struct of_phandle_args *args)
 502 {
 503         struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
 504         unsigned int type = args->args[0], master = args->args[1];
 505         struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
 506         struct tegra_hsp_doorbell *db;
 507         struct mbox_chan *chan;
 508         unsigned long flags;
 509         unsigned int i;
 510
 511         if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
 512                 return ERR_PTR(-ENODEV);
 513
 514         db = tegra_hsp_doorbell_get(hsp, master);
 515         if (db)
 516                 channel = &db->channel;
 517
 518         if (IS_ERR(channel))
 519                 return ERR_CAST(channel);
 520
 521         spin_lock_irqsave(&hsp->lock, flags);
 522
 523         for (i = 0; i < mbox->num_chans; i++) {
 524                 chan = &mbox->chans[i];
 525                 if (!chan->con_priv) {
 526                         channel->chan = chan;
 527                         chan->con_priv = db;
 528                         break;
 529                 }
 530
 531                 chan = NULL;
 532         }
 533
 534         spin_unlock_irqrestore(&hsp->lock, flags);
 535
 536         return chan ?: ERR_PTR(-EBUSY);
 537 }
 538
 539 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
 540                                             const struct of_phandle_args *args)
 541 {
 542         struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
 543         unsigned int type = args->args[0], index;
 544         struct tegra_hsp_mailbox *mb;
 545
 546         index = args->args[1] & TEGRA_HSP_SM_MASK;
 547
 548         if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
 549             index >= hsp->num_sm)
 550                 return ERR_PTR(-ENODEV);
 551
 552         mb = &hsp->mailboxes[index];
 553
 554         if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
 555                 mb->producer = false;
 556         else
 557                 mb->producer = true;
 558
 559         return mb->channel.chan;
 560 }
 561
 562 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
 563 {
 564         const struct tegra_hsp_db_map *map = hsp->soc->map;
 565         struct tegra_hsp_channel *channel;
 566
 567         while (map->name) {
 568                 channel = tegra_hsp_doorbell_create(hsp, map->name,
 569                                                     map->master, map->index);
 570                 if (IS_ERR(channel))
 571                         return PTR_ERR(channel);
 572
 573                 map++;
 574         }
 575
 576         return 0;
 577 }
 578
 579 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
 580 {
 581         int i;
 582
 583         hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
 584                                       GFP_KERNEL);
 585         if (!hsp->mailboxes)
 586                 return -ENOMEM;
 587
 588         for (i = 0; i < hsp->num_sm; i++) {
 589                 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
 590
 591                 mb->index = i;
 592
 593                 mb->channel.hsp = hsp;
 594                 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
 595                 mb->channel.chan = &hsp->mbox_sm.chans[i];
 596                 mb->channel.chan->con_priv = mb;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
 603 {
 604         unsigned int i, irq = 0;
 605         int err;
 606
 607         for (i = 0; i < hsp->num_si; i++) {
 608                 irq = hsp->shared_irqs[i];
 609                 if (irq <= 0)
 610                         continue;
 611
 612                 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
 613                                        dev_name(hsp->dev), hsp);
 614                 if (err < 0) {
 615                         dev_err(hsp->dev, "failed to request interrupt: %d\n",
 616                                 err);
 617                         continue;
 618                 }
 619
 620                 hsp->shared_irq = i;
 621
 622                 /* disable all interrupts */
 623                 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
 624
 625                 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
 626
 627                 break;
 628         }
 629
 630         if (i == hsp->num_si) {
 631                 dev_err(hsp->dev, "failed to find available interrupt\n");
 632                 return -ENOENT;
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int tegra_hsp_probe(struct platform_device *pdev)
 639 {
 640         struct tegra_hsp *hsp;
 641         struct resource *res;
 642         unsigned int i;
 643         u32 value;
 644         int err;
 645
 646         hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
 647         if (!hsp)
 648                 return -ENOMEM;
 649
 650         hsp->dev = &pdev->dev;
 651         hsp->soc = of_device_get_match_data(&pdev->dev);
 652         INIT_LIST_HEAD(&hsp->doorbells);
 653         spin_lock_init(&hsp->lock);
 654
 655         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 656         hsp->regs = devm_ioremap_resource(&pdev->dev, res);
 657         if (IS_ERR(hsp->regs))
 658                 return PTR_ERR(hsp->regs);
 659
 660         value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
 661         hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
 662         hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
 663         hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
 664         hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
 665         hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
 666
 667         err = platform_get_irq_byname_optional(pdev, "doorbell");
 668         if (err >= 0)
 669                 hsp->doorbell_irq = err;
 670
 671         if (hsp->num_si > 0) {
 672                 unsigned int count = 0;
 673
 674                 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
 675                                                 sizeof(*hsp->shared_irqs),
 676                                                 GFP_KERNEL);
 677                 if (!hsp->shared_irqs)
 678                         return -ENOMEM;
 679
 680                 for (i = 0; i < hsp->num_si; i++) {
 681                         char *name;
 682
 683                         name = kasprintf(GFP_KERNEL, "shared%u", i);
 684                         if (!name)
 685                                 return -ENOMEM;
 686
 687                         err = platform_get_irq_byname_optional(pdev, name);
 688                         if (err >= 0) {
 689                                 hsp->shared_irqs[i] = err;
 690                                 count++;
 691                         }
 692
 693                         kfree(name);
 694                 }
 695
 696                 if (count == 0) {
 697                         devm_kfree(&pdev->dev, hsp->shared_irqs);
 698                         hsp->shared_irqs = NULL;
 699                 }
 700         }
 701
 702         /* setup the doorbell controller */
 703         hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
 704         hsp->mbox_db.num_chans = 32;
 705         hsp->mbox_db.dev = &pdev->dev;
 706         hsp->mbox_db.ops = &tegra_hsp_db_ops;
 707
 708         hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
 709                                           sizeof(*hsp->mbox_db.chans),
 710                                           GFP_KERNEL);
 711         if (!hsp->mbox_db.chans)
 712                 return -ENOMEM;
 713
 714         if (hsp->doorbell_irq) {
 715                 err = tegra_hsp_add_doorbells(hsp);
 716                 if (err < 0) {
 717                         dev_err(&pdev->dev, "failed to add doorbells: %d\n",
 718                                 err);
 719                         return err;
 720                 }
 721         }
 722
 723         err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
 724         if (err < 0) {
 725                 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
 726                         err);
 727                 return err;
 728         }
 729
 730         /* setup the shared mailbox controller */
 731         hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
 732         hsp->mbox_sm.num_chans = hsp->num_sm;
 733         hsp->mbox_sm.dev = &pdev->dev;
 734         hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
 735
 736         hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
 737                                           sizeof(*hsp->mbox_sm.chans),
 738                                           GFP_KERNEL);
 739         if (!hsp->mbox_sm.chans)
 740                 return -ENOMEM;
 741
 742         if (hsp->shared_irqs) {
 743                 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
 744                 if (err < 0) {
 745                         dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
 746                                 err);
 747                         return err;
 748                 }
 749         }
 750
 751         err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
 752         if (err < 0) {
 753                 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
 754                         err);
 755                 return err;
 756         }
 757
 758         platform_set_drvdata(pdev, hsp);
 759
 760         if (hsp->doorbell_irq) {
 761                 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
 762                                        tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
 763                                        dev_name(&pdev->dev), hsp);
 764                 if (err < 0) {
 765                         dev_err(&pdev->dev,
 766                                 "failed to request doorbell IRQ#%u: %d\n",
 767                                 hsp->doorbell_irq, err);
 768                         return err;
 769                 }
 770         }
 771
 772         if (hsp->shared_irqs) {
 773                 err = tegra_hsp_request_shared_irq(hsp);
 774                 if (err < 0)
 775                         return err;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int __maybe_unused tegra_hsp_resume(struct device *dev)
 782 {
 783         struct tegra_hsp *hsp = dev_get_drvdata(dev);
 784         unsigned int i;
 785         struct tegra_hsp_doorbell *db;
 786
 787         list_for_each_entry(db, &hsp->doorbells, list) {
 788                 if (db && db->channel.chan)
 789                         tegra_hsp_doorbell_startup(db->channel.chan);
 790         }
 791
 792         if (hsp->mailboxes) {
 793                 for (i = 0; i < hsp->num_sm; i++) {
 794                         struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
 795
 796                         if (mb->channel.chan->cl)
 797                                 tegra_hsp_mailbox_startup(mb->channel.chan);
 798                 }
 799         }
 800
 801         return 0;
 802 }
 803
 804 static const struct dev_pm_ops tegra_hsp_pm_ops = {
 805         .resume_noirq = tegra_hsp_resume,
 806 };
 807
 808 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
 809         { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
 810         { "bpmp",   TEGRA_HSP_DB_MASTER_BPMP,   HSP_DB_BPMP,   },
 811         { /* sentinel */ }
 812 };
 813
 814 static const struct tegra_hsp_soc tegra186_hsp_soc = {
 815         .map = tegra186_hsp_db_map,
 816         .has_per_mb_ie = false,
 817 };
 818
 819 static const struct tegra_hsp_soc tegra194_hsp_soc = {
 820         .map = tegra186_hsp_db_map,
 821         .has_per_mb_ie = true,
 822 };
 823
 824 static const struct of_device_id tegra_hsp_match[] = {
 825         { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
 826         { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
 827         { }
 828 };
 829
 830 static struct platform_driver tegra_hsp_driver = {
 831         .driver = {
 832                 .name = "tegra-hsp",
 833                 .of_match_table = tegra_hsp_match,
 834                 .pm = &tegra_hsp_pm_ops,
 835         },
 836         .probe = tegra_hsp_probe,
 837 };
 838
 839 static int __init tegra_hsp_init(void)
 840 {
 841         return platform_driver_register(&tegra_hsp_driver);
 842 }
 843 core_initcall(tegra_hsp_init);