1 #include <media/drv-intf/saa7146_vv.h>
3 static int vbi_pixel_to_capture
= 720 * 2;
5 static int vbi_workaround(struct saa7146_dev
*dev
)
7 struct saa7146_vv
*vv
= dev
->vv_data
;
15 DECLARE_WAITQUEUE(wait
, current
);
17 DEB_VBI("dev:%p\n", dev
);
19 /* once again, a bug in the saa7146: the brs acquisition
20 is buggy and especially the BXO-counter does not work
21 as specified. there is this workaround, but please
22 don't let me explain it. ;-) */
24 cpu
= pci_alloc_consistent(dev
->pci
, 4096, &dma_addr
);
28 /* setup some basic programming, just for the workaround */
29 saa7146_write(dev
, BASE_EVEN3
, dma_addr
);
30 saa7146_write(dev
, BASE_ODD3
, dma_addr
+vbi_pixel_to_capture
);
31 saa7146_write(dev
, PROT_ADDR3
, dma_addr
+4096);
32 saa7146_write(dev
, PITCH3
, vbi_pixel_to_capture
);
33 saa7146_write(dev
, BASE_PAGE3
, 0x0);
34 saa7146_write(dev
, NUM_LINE_BYTE3
, (2<<16)|((vbi_pixel_to_capture
)<<0));
35 saa7146_write(dev
, MC2
, MASK_04
|MASK_20
);
37 /* load brs-control register */
38 WRITE_RPS1(CMD_WR_REG
| (1 << 8) | (BRS_CTRL
/4));
39 /* BXO = 1h, BRS to outbound */
40 WRITE_RPS1(0xc000008c);
41 /* wait for vbi_a or vbi_b*/
42 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI
& dev
->ext_vv_data
->flags
)) {
43 DEB_D("...using port b\n");
44 WRITE_RPS1(CMD_PAUSE
| CMD_OAN
| CMD_SIG1
| CMD_E_FID_B
);
45 WRITE_RPS1(CMD_PAUSE
| CMD_OAN
| CMD_SIG1
| CMD_O_FID_B
);
47 WRITE_RPS1(CMD_PAUSE | MASK_09);
50 DEB_D("...using port a\n");
51 WRITE_RPS1(CMD_PAUSE
| MASK_10
);
54 WRITE_RPS1(CMD_UPLOAD
| MASK_08
);
55 /* load brs-control register */
56 WRITE_RPS1(CMD_WR_REG
| (1 << 8) | (BRS_CTRL
/4));
57 /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
58 WRITE_RPS1(((1728-(vbi_pixel_to_capture
)) << 7) | MASK_19
);
59 /* wait for brs_done */
60 WRITE_RPS1(CMD_PAUSE
| MASK_08
);
62 WRITE_RPS1(CMD_UPLOAD
| MASK_08
);
63 /* load video-dma3 NumLines3 and NumBytes3 */
64 WRITE_RPS1(CMD_WR_REG
| (1 << 8) | (NUM_LINE_BYTE3
/4));
65 /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
66 WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture
));
67 /* load brs-control register */
68 WRITE_RPS1(CMD_WR_REG
| (1 << 8) | (BRS_CTRL
/4));
69 /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
70 WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
71 /* wait for brs_done */
72 WRITE_RPS1(CMD_PAUSE
| MASK_08
);
73 /* upload brs and video-dma3*/
74 WRITE_RPS1(CMD_UPLOAD
| MASK_08
| MASK_04
);
75 /* load mc2 register: enable dma3 */
76 WRITE_RPS1(CMD_WR_REG
| (1 << 8) | (MC1
/4));
77 WRITE_RPS1(MASK_20
| MASK_04
);
78 /* generate interrupt */
79 WRITE_RPS1(CMD_INTERRUPT
);
83 /* we have to do the workaround twice to be sure that
85 for(i
= 0; i
< 2; i
++) {
87 /* indicate to the irq handler that we do the workaround */
88 saa7146_write(dev
, MC2
, MASK_31
|MASK_15
);
90 saa7146_write(dev
, NUM_LINE_BYTE3
, (1<<16)|(2<<0));
91 saa7146_write(dev
, MC2
, MASK_04
|MASK_20
);
93 /* enable rps1 irqs */
94 SAA7146_IER_ENABLE(dev
,MASK_28
);
96 /* prepare to wait to be woken up by the irq-handler */
97 add_wait_queue(&vv
->vbi_wq
, &wait
);
98 set_current_state(TASK_INTERRUPTIBLE
);
100 /* start rps1 to enable workaround */
101 saa7146_write(dev
, RPS_ADDR1
, dev
->d_rps1
.dma_handle
);
102 saa7146_write(dev
, MC1
, (MASK_13
| MASK_29
));
106 DEB_VBI("brs bug workaround %d/1\n", i
);
108 remove_wait_queue(&vv
->vbi_wq
, &wait
);
109 __set_current_state(TASK_RUNNING
);
111 /* disable rps1 irqs */
112 SAA7146_IER_DISABLE(dev
,MASK_28
);
114 /* stop video-dma3 */
115 saa7146_write(dev
, MC1
, MASK_20
);
117 if(signal_pending(current
)) {
119 DEB_VBI("aborted (rps:0x%08x)\n",
120 saa7146_read(dev
, RPS_ADDR1
));
122 /* stop rps1 for sure */
123 saa7146_write(dev
, MC1
, MASK_29
);
125 pci_free_consistent(dev
->pci
, 4096, cpu
, dma_addr
);
130 pci_free_consistent(dev
->pci
, 4096, cpu
, dma_addr
);
134 static void saa7146_set_vbi_capture(struct saa7146_dev
*dev
, struct saa7146_buf
*buf
, struct saa7146_buf
*next
)
136 struct saa7146_vv
*vv
= dev
->vv_data
;
138 struct saa7146_video_dma vdma3
;
141 unsigned long e_wait
= vv
->current_hps_sync
== SAA7146_HPS_SYNC_PORT_A
? CMD_E_FID_A
: CMD_E_FID_B
;
142 unsigned long o_wait
= vv
->current_hps_sync
== SAA7146_HPS_SYNC_PORT_A
? CMD_O_FID_A
: CMD_O_FID_B
;
145 vdma3.base_even = 0xc8000000+2560*70;
146 vdma3.base_odd = 0xc8000000;
147 vdma3.prot_addr = 0xc8000000+2560*164;
150 vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above!
152 vdma3
.base_even
= buf
->pt
[2].offset
;
153 vdma3
.base_odd
= buf
->pt
[2].offset
+ 16 * vbi_pixel_to_capture
;
154 vdma3
.prot_addr
= buf
->pt
[2].offset
+ 16 * 2 * vbi_pixel_to_capture
;
155 vdma3
.pitch
= vbi_pixel_to_capture
;
156 vdma3
.base_page
= buf
->pt
[2].dma
| ME1
;
157 vdma3
.num_line_byte
= (16 << 16) | vbi_pixel_to_capture
;
159 saa7146_write_out_dma(dev
, 3, &vdma3
);
161 /* write beginning of rps-program */
164 /* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */
166 /* we don't wait here for the first field anymore. this is different from the video
167 capture and might cause that the first buffer is only half filled (with only
168 one field). but since this is some sort of streaming data, this is not that negative.
169 but by doing this, we can use the whole engine from videobuf-dma-sg.c... */
172 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait);
173 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait);
176 WRITE_RPS1(CMD_WR_REG
| (1 << 8) | (MC2
/4));
177 WRITE_RPS1(MASK_28
| MASK_12
);
179 /* turn on video-dma3 */
180 WRITE_RPS1(CMD_WR_REG_MASK
| (MC1
/4));
181 WRITE_RPS1(MASK_04
| MASK_20
); /* => mask */
182 WRITE_RPS1(MASK_04
| MASK_20
); /* => values */
184 /* wait for o_fid_a/b / e_fid_a/b toggle */
185 WRITE_RPS1(CMD_PAUSE
| o_wait
);
186 WRITE_RPS1(CMD_PAUSE
| e_wait
);
188 /* generate interrupt */
189 WRITE_RPS1(CMD_INTERRUPT
);
192 WRITE_RPS1(CMD_STOP
);
194 /* enable rps1 irqs */
195 SAA7146_IER_ENABLE(dev
, MASK_28
);
197 /* write the address of the rps-program */
198 saa7146_write(dev
, RPS_ADDR1
, dev
->d_rps1
.dma_handle
);
201 saa7146_write(dev
, MC1
, (MASK_13
| MASK_29
));
204 static int buffer_activate(struct saa7146_dev
*dev
,
205 struct saa7146_buf
*buf
,
206 struct saa7146_buf
*next
)
208 struct saa7146_vv
*vv
= dev
->vv_data
;
209 buf
->vb
.state
= VIDEOBUF_ACTIVE
;
211 DEB_VBI("dev:%p, buf:%p, next:%p\n", dev
, buf
, next
);
212 saa7146_set_vbi_capture(dev
,buf
,next
);
214 mod_timer(&vv
->vbi_dmaq
.timeout
, jiffies
+BUFFER_TIMEOUT
);
218 static int buffer_prepare(struct videobuf_queue
*q
, struct videobuf_buffer
*vb
,enum v4l2_field field
)
220 struct file
*file
= q
->priv_data
;
221 struct saa7146_fh
*fh
= file
->private_data
;
222 struct saa7146_dev
*dev
= fh
->dev
;
223 struct saa7146_buf
*buf
= (struct saa7146_buf
*)vb
;
226 int lines
, llength
, size
;
228 lines
= 16 * 2 ; /* 2 fields */
229 llength
= vbi_pixel_to_capture
;
230 size
= lines
* llength
;
232 DEB_VBI("vb:%p\n", vb
);
234 if (0 != buf
->vb
.baddr
&& buf
->vb
.bsize
< size
) {
235 DEB_VBI("size mismatch\n");
239 if (buf
->vb
.size
!= size
)
240 saa7146_dma_free(dev
,q
,buf
);
242 if (VIDEOBUF_NEEDS_INIT
== buf
->vb
.state
) {
243 struct videobuf_dmabuf
*dma
=videobuf_to_dma(&buf
->vb
);
245 buf
->vb
.width
= llength
;
246 buf
->vb
.height
= lines
;
248 buf
->vb
.field
= field
; // FIXME: check this
250 saa7146_pgtable_free(dev
->pci
, &buf
->pt
[2]);
251 saa7146_pgtable_alloc(dev
->pci
, &buf
->pt
[2]);
253 err
= videobuf_iolock(q
,&buf
->vb
, NULL
);
256 err
= saa7146_pgtable_build_single(dev
->pci
, &buf
->pt
[2],
257 dma
->sglist
, dma
->sglen
);
261 buf
->vb
.state
= VIDEOBUF_PREPARED
;
262 buf
->activate
= buffer_activate
;
267 DEB_VBI("error out\n");
268 saa7146_dma_free(dev
,q
,buf
);
273 static int buffer_setup(struct videobuf_queue
*q
, unsigned int *count
, unsigned int *size
)
277 lines
= 16 * 2 ; /* 2 fields */
278 llength
= vbi_pixel_to_capture
;
280 *size
= lines
* llength
;
283 DEB_VBI("count:%d, size:%d\n", *count
, *size
);
288 static void buffer_queue(struct videobuf_queue
*q
, struct videobuf_buffer
*vb
)
290 struct file
*file
= q
->priv_data
;
291 struct saa7146_fh
*fh
= file
->private_data
;
292 struct saa7146_dev
*dev
= fh
->dev
;
293 struct saa7146_vv
*vv
= dev
->vv_data
;
294 struct saa7146_buf
*buf
= (struct saa7146_buf
*)vb
;
296 DEB_VBI("vb:%p\n", vb
);
297 saa7146_buffer_queue(dev
, &vv
->vbi_dmaq
, buf
);
300 static void buffer_release(struct videobuf_queue
*q
, struct videobuf_buffer
*vb
)
302 struct file
*file
= q
->priv_data
;
303 struct saa7146_fh
*fh
= file
->private_data
;
304 struct saa7146_dev
*dev
= fh
->dev
;
305 struct saa7146_buf
*buf
= (struct saa7146_buf
*)vb
;
307 DEB_VBI("vb:%p\n", vb
);
308 saa7146_dma_free(dev
,q
,buf
);
311 static const struct videobuf_queue_ops vbi_qops
= {
312 .buf_setup
= buffer_setup
,
313 .buf_prepare
= buffer_prepare
,
314 .buf_queue
= buffer_queue
,
315 .buf_release
= buffer_release
,
318 /* ------------------------------------------------------------------ */
320 static void vbi_stop(struct saa7146_fh
*fh
, struct file
*file
)
322 struct saa7146_dev
*dev
= fh
->dev
;
323 struct saa7146_vv
*vv
= dev
->vv_data
;
325 DEB_VBI("dev:%p, fh:%p\n", dev
, fh
);
327 spin_lock_irqsave(&dev
->slock
,flags
);
330 saa7146_write(dev
, MC1
, MASK_29
);
332 /* disable rps1 irqs */
333 SAA7146_IER_DISABLE(dev
, MASK_28
);
335 /* shut down dma 3 transfers */
336 saa7146_write(dev
, MC1
, MASK_20
);
338 if (vv
->vbi_dmaq
.curr
)
339 saa7146_buffer_finish(dev
, &vv
->vbi_dmaq
, VIDEOBUF_DONE
);
341 videobuf_queue_cancel(&fh
->vbi_q
);
343 vv
->vbi_streaming
= NULL
;
345 del_timer(&vv
->vbi_dmaq
.timeout
);
346 del_timer(&vv
->vbi_read_timeout
);
348 spin_unlock_irqrestore(&dev
->slock
, flags
);
351 static void vbi_read_timeout(unsigned long data
)
353 struct file
*file
= (struct file
*)data
;
354 struct saa7146_fh
*fh
= file
->private_data
;
355 struct saa7146_dev
*dev
= fh
->dev
;
357 DEB_VBI("dev:%p, fh:%p\n", dev
, fh
);
362 static void vbi_init(struct saa7146_dev
*dev
, struct saa7146_vv
*vv
)
364 DEB_VBI("dev:%p\n", dev
);
366 INIT_LIST_HEAD(&vv
->vbi_dmaq
.queue
);
368 setup_timer(&vv
->vbi_dmaq
.timeout
, saa7146_buffer_timeout
,
369 (unsigned long)(&vv
->vbi_dmaq
));
370 vv
->vbi_dmaq
.dev
= dev
;
372 init_waitqueue_head(&vv
->vbi_wq
);
375 static int vbi_open(struct saa7146_dev
*dev
, struct file
*file
)
377 struct saa7146_fh
*fh
= file
->private_data
;
378 struct saa7146_vv
*vv
= fh
->dev
->vv_data
;
380 u32 arbtr_ctrl
= saa7146_read(dev
, PCI_BT_V1
);
383 DEB_VBI("dev:%p, fh:%p\n", dev
, fh
);
385 ret
= saa7146_res_get(fh
, RESOURCE_DMA3_BRS
);
387 DEB_S("cannot get vbi RESOURCE_DMA3_BRS resource\n");
391 /* adjust arbitrition control for video dma 3 */
392 arbtr_ctrl
&= ~0x1f0000;
393 arbtr_ctrl
|= 0x1d0000;
394 saa7146_write(dev
, PCI_BT_V1
, arbtr_ctrl
);
395 saa7146_write(dev
, MC2
, (MASK_04
|MASK_20
));
397 videobuf_queue_sg_init(&fh
->vbi_q
, &vbi_qops
,
398 &dev
->pci
->dev
, &dev
->slock
,
399 V4L2_BUF_TYPE_VBI_CAPTURE
,
400 V4L2_FIELD_SEQ_TB
, // FIXME: does this really work?
401 sizeof(struct saa7146_buf
),
402 file
, &dev
->v4l2_lock
);
404 vv
->vbi_read_timeout
.function
= vbi_read_timeout
;
405 vv
->vbi_read_timeout
.data
= (unsigned long)file
;
407 /* initialize the brs */
408 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI
& dev
->ext_vv_data
->flags
)) {
409 saa7146_write(dev
, BRS_CTRL
, MASK_30
|MASK_29
| (7 << 19));
411 saa7146_write(dev
, BRS_CTRL
, 0x00000001);
413 if (0 != (ret
= vbi_workaround(dev
))) {
414 DEB_VBI("vbi workaround failed!\n");
419 /* upload brs register */
420 saa7146_write(dev
, MC2
, (MASK_08
|MASK_24
));
424 static void vbi_close(struct saa7146_dev
*dev
, struct file
*file
)
426 struct saa7146_fh
*fh
= file
->private_data
;
427 struct saa7146_vv
*vv
= dev
->vv_data
;
428 DEB_VBI("dev:%p, fh:%p\n", dev
, fh
);
430 if( fh
== vv
->vbi_streaming
) {
433 saa7146_res_free(fh
, RESOURCE_DMA3_BRS
);
436 static void vbi_irq_done(struct saa7146_dev
*dev
, unsigned long status
)
438 struct saa7146_vv
*vv
= dev
->vv_data
;
439 spin_lock(&dev
->slock
);
441 if (vv
->vbi_dmaq
.curr
) {
442 DEB_VBI("dev:%p, curr:%p\n", dev
, vv
->vbi_dmaq
.curr
);
443 /* this must be += 2, one count for each field */
444 vv
->vbi_fieldcount
+=2;
445 vv
->vbi_dmaq
.curr
->vb
.field_count
= vv
->vbi_fieldcount
;
446 saa7146_buffer_finish(dev
, &vv
->vbi_dmaq
, VIDEOBUF_DONE
);
448 DEB_VBI("dev:%p\n", dev
);
450 saa7146_buffer_next(dev
, &vv
->vbi_dmaq
, 1);
452 spin_unlock(&dev
->slock
);
455 static ssize_t
vbi_read(struct file
*file
, char __user
*data
, size_t count
, loff_t
*ppos
)
457 struct saa7146_fh
*fh
= file
->private_data
;
458 struct saa7146_dev
*dev
= fh
->dev
;
459 struct saa7146_vv
*vv
= dev
->vv_data
;
462 DEB_VBI("dev:%p, fh:%p\n", dev
, fh
);
464 if( NULL
== vv
->vbi_streaming
) {
465 // fixme: check if dma3 is available
466 // fixme: activate vbi engine here if necessary. (really?)
467 vv
->vbi_streaming
= fh
;
470 if( fh
!= vv
->vbi_streaming
) {
471 DEB_VBI("open %p is already using vbi capture\n",
476 mod_timer(&vv
->vbi_read_timeout
, jiffies
+BUFFER_TIMEOUT
);
477 ret
= videobuf_read_stream(&fh
->vbi_q
, data
, count
, ppos
, 1,
478 file
->f_flags
& O_NONBLOCK
);
480 printk("BASE_ODD3: 0x%08x\n", saa7146_read(dev, BASE_ODD3));
481 printk("BASE_EVEN3: 0x%08x\n", saa7146_read(dev, BASE_EVEN3));
482 printk("PROT_ADDR3: 0x%08x\n", saa7146_read(dev, PROT_ADDR3));
483 printk("PITCH3: 0x%08x\n", saa7146_read(dev, PITCH3));
484 printk("BASE_PAGE3: 0x%08x\n", saa7146_read(dev, BASE_PAGE3));
485 printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3));
486 printk("BRS_CTRL: 0x%08x\n", saa7146_read(dev, BRS_CTRL));
491 struct saa7146_use_ops saa7146_vbi_uops
= {
494 .release
= vbi_close
,
495 .irq_done
= vbi_irq_done
,