drivers/media/dvb/frontends/mt352.c

   1 /*
   2  *  Driver for Zarlink DVB-T MT352 demodulator
   3  *
   4  *  Written by Holger Waechtler <holger@qanu.de>
   5  *       and Daniel Mack <daniel@qanu.de>
   6  *
   7  *  AVerMedia AVerTV DVB-T 771 support by
   8  *       Wolfram Joost <dbox2@frokaschwei.de>
   9  *
  10  *  Support for Samsung TDTC9251DH01C(M) tuner
  11  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
  12  *                     Amauri  Celani  <acelani@essegi.net>
  13  *
  14  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
  15  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *
  26  *  GNU General Public License for more details.
  27  *
  28  *  You should have received a copy of the GNU General Public License
  29  *  along with this program; if not, write to the Free Software
  30  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/init.h>
  37 #include <linux/delay.h>
  38
  39 #include "dvb_frontend.h"
  40 #include "mt352_priv.h"
  41 #include "mt352.h"
  42
  43 struct mt352_state {
  44         struct i2c_adapter* i2c;
  45         struct dvb_frontend frontend;
  46         struct dvb_frontend_ops ops;
  47
  48         /* configuration settings */
  49         const struct mt352_config* config;
  50 };
  51
  52 static int debug;
  53 #define dprintk(args...) \
  54         do { \
  55                 if (debug) printk(KERN_DEBUG "mt352: " args); \
  56         } while (0)
  57
  58 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
  59 {
  60         struct mt352_state* state = fe->demodulator_priv;
  61         u8 buf[2] = { reg, val };
  62         struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0,
  63                                .buf = buf, .len = 2 };
  64         int err = i2c_transfer(state->i2c, &msg, 1);
  65         if (err != 1) {
  66                 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
  67                 return err;
  68         }
  69         return 0;
  70 }
  71
  72 int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
  73 {
  74         int err,i;
  75         for (i=0; i < ilen-1; i++)
  76                 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
  77                         return err;
  78
  79         return 0;
  80 }
  81
  82 static int mt352_read_register(struct mt352_state* state, u8 reg)
  83 {
  84         int ret;
  85         u8 b0 [] = { reg };
  86         u8 b1 [] = { 0 };
  87         struct i2c_msg msg [] = { { .addr = state->config->demod_address,
  88                                     .flags = 0,
  89                                     .buf = b0, .len = 1 },
  90                                   { .addr = state->config->demod_address,
  91                                     .flags = I2C_M_RD,
  92                                     .buf = b1, .len = 1 } };
  93
  94         ret = i2c_transfer(state->i2c, msg, 2);
  95
  96         if (ret != 2) {
  97                 printk("%s: readreg error (reg=%d, ret==%i)\n",
  98                        __FUNCTION__, reg, ret);
  99                 return ret;
 100         }
 101
 102         return b1[0];
 103 }
 104
 105 int mt352_read(struct dvb_frontend *fe, u8 reg)
 106 {
 107         return mt352_read_register(fe->demodulator_priv,reg);
 108 }
 109
 110 static int mt352_sleep(struct dvb_frontend* fe)
 111 {
 112         static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
 113
 114         mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
 115         return 0;
 116 }
 117
 118 static void mt352_calc_nominal_rate(struct mt352_state* state,
 119                                     enum fe_bandwidth bandwidth,
 120                                     unsigned char *buf)
 121 {
 122         u32 adc_clock = 20480; /* 20.340 MHz */
 123         u32 bw,value;
 124
 125         switch (bandwidth) {
 126         case BANDWIDTH_6_MHZ:
 127                 bw = 6;
 128                 break;
 129         case BANDWIDTH_7_MHZ:
 130                 bw = 7;
 131                 break;
 132         case BANDWIDTH_8_MHZ:
 133         default:
 134                 bw = 8;
 135                 break;
 136         }
 137         if (state->config->adc_clock)
 138                 adc_clock = state->config->adc_clock;
 139
 140         value = 64 * bw * (1<<16) / (7 * 8);
 141         value = value * 1000 / adc_clock;
 142         dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
 143                 __FUNCTION__, bw, adc_clock, value);
 144         buf[0] = msb(value);
 145         buf[1] = lsb(value);
 146 }
 147
 148 static void mt352_calc_input_freq(struct mt352_state* state,
 149                                   unsigned char *buf)
 150 {
 151         int adc_clock = 20480; /* 20.480000 MHz */
 152         int if2       = 36167; /* 36.166667 MHz */
 153         int ife,value;
 154
 155         if (state->config->adc_clock)
 156                 adc_clock = state->config->adc_clock;
 157         if (state->config->if2)
 158                 if2 = state->config->if2;
 159
 160         ife = (2*adc_clock - if2);
 161         value = -16374 * ife / adc_clock;
 162         dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
 163                 __FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
 164         buf[0] = msb(value);
 165         buf[1] = lsb(value);
 166 }
 167
 168 static int mt352_set_parameters(struct dvb_frontend* fe,
 169                                 struct dvb_frontend_parameters *param)
 170 {
 171         struct mt352_state* state = fe->demodulator_priv;
 172         unsigned char buf[13];
 173         static unsigned char tuner_go[] = { 0x5d, 0x01 };
 174         static unsigned char fsm_go[]   = { 0x5e, 0x01 };
 175         unsigned int tps = 0;
 176         struct dvb_ofdm_parameters *op = &param->u.ofdm;
 177
 178         switch (op->code_rate_HP) {
 179                 case FEC_2_3:
 180                         tps |= (1 << 7);
 181                         break;
 182                 case FEC_3_4:
 183                         tps |= (2 << 7);
 184                         break;
 185                 case FEC_5_6:
 186                         tps |= (3 << 7);
 187                         break;
 188                 case FEC_7_8:
 189                         tps |= (4 << 7);
 190                         break;
 191                 case FEC_1_2:
 192                 case FEC_AUTO:
 193                         break;
 194                 default:
 195                         return -EINVAL;
 196         }
 197
 198         switch (op->code_rate_LP) {
 199                 case FEC_2_3:
 200                         tps |= (1 << 4);
 201                         break;
 202                 case FEC_3_4:
 203                         tps |= (2 << 4);
 204                         break;
 205                 case FEC_5_6:
 206                         tps |= (3 << 4);
 207                         break;
 208                 case FEC_7_8:
 209                         tps |= (4 << 4);
 210                         break;
 211                 case FEC_1_2:
 212                 case FEC_AUTO:
 213                         break;
 214                 case FEC_NONE:
 215                         if (op->hierarchy_information == HIERARCHY_AUTO ||
 216                             op->hierarchy_information == HIERARCHY_NONE)
 217                                 break;
 218                 default:
 219                         return -EINVAL;
 220         }
 221
 222         switch (op->constellation) {
 223                 case QPSK:
 224                         break;
 225                 case QAM_AUTO:
 226                 case QAM_16:
 227                         tps |= (1 << 13);
 228                         break;
 229                 case QAM_64:
 230                         tps |= (2 << 13);
 231                         break;
 232                 default:
 233                         return -EINVAL;
 234         }
 235
 236         switch (op->transmission_mode) {
 237                 case TRANSMISSION_MODE_2K:
 238                 case TRANSMISSION_MODE_AUTO:
 239                         break;
 240                 case TRANSMISSION_MODE_8K:
 241                         tps |= (1 << 0);
 242                         break;
 243                 default:
 244                         return -EINVAL;
 245         }
 246
 247         switch (op->guard_interval) {
 248                 case GUARD_INTERVAL_1_32:
 249                 case GUARD_INTERVAL_AUTO:
 250                         break;
 251                 case GUARD_INTERVAL_1_16:
 252                         tps |= (1 << 2);
 253                         break;
 254                 case GUARD_INTERVAL_1_8:
 255                         tps |= (2 << 2);
 256                         break;
 257                 case GUARD_INTERVAL_1_4:
 258                         tps |= (3 << 2);
 259                         break;
 260                 default:
 261                         return -EINVAL;
 262         }
 263
 264         switch (op->hierarchy_information) {
 265                 case HIERARCHY_AUTO:
 266                 case HIERARCHY_NONE:
 267                         break;
 268                 case HIERARCHY_1:
 269                         tps |= (1 << 10);
 270                         break;
 271                 case HIERARCHY_2:
 272                         tps |= (2 << 10);
 273                         break;
 274                 case HIERARCHY_4:
 275                         tps |= (3 << 10);
 276                         break;
 277                 default:
 278                         return -EINVAL;
 279         }
 280
 281
 282         buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
 283
 284         buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
 285         buf[2] = lsb(tps);
 286
 287         buf[3] = 0x50;  // old
 288 //      buf[3] = 0xf4;  // pinnacle
 289
 290         mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
 291         mt352_calc_input_freq(state, buf+6);
 292         state->config->pll_set(fe, param, buf+8);
 293
 294         mt352_write(fe, buf, sizeof(buf));
 295         if (state->config->no_tuner) {
 296                 /* start decoding */
 297                 mt352_write(fe, fsm_go, 2);
 298         } else {
 299                 /* start tuning */
 300                 mt352_write(fe, tuner_go, 2);
 301         }
 302         return 0;
 303 }
 304
 305 static int mt352_get_parameters(struct dvb_frontend* fe,
 306                                 struct dvb_frontend_parameters *param)
 307 {
 308         struct mt352_state* state = fe->demodulator_priv;
 309         u16 tps;
 310         u16 div;
 311         u8 trl;
 312         struct dvb_ofdm_parameters *op = &param->u.ofdm;
 313         static const u8 tps_fec_to_api[8] =
 314         {
 315                 FEC_1_2,
 316                 FEC_2_3,
 317                 FEC_3_4,
 318                 FEC_5_6,
 319                 FEC_7_8,
 320                 FEC_AUTO,
 321                 FEC_AUTO,
 322                 FEC_AUTO
 323         };
 324
 325         if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
 326                 return -EINVAL;
 327
 328         /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
 329          * the mt352 sometimes works with the wrong parameters
 330          */
 331         tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
 332         div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
 333         trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
 334
 335         op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
 336         op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
 337
 338         switch ( (tps >> 13) & 3)
 339         {
 340                 case 0:
 341                         op->constellation = QPSK;
 342                         break;
 343                 case 1:
 344                         op->constellation = QAM_16;
 345                         break;
 346                 case 2:
 347                         op->constellation = QAM_64;
 348                         break;
 349                 default:
 350                         op->constellation = QAM_AUTO;
 351                         break;
 352         }
 353
 354         op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
 355
 356         switch ( (tps >> 2) & 3)
 357         {
 358                 case 0:
 359                         op->guard_interval = GUARD_INTERVAL_1_32;
 360                         break;
 361                 case 1:
 362                         op->guard_interval = GUARD_INTERVAL_1_16;
 363                         break;
 364                 case 2:
 365                         op->guard_interval = GUARD_INTERVAL_1_8;
 366                         break;
 367                 case 3:
 368                         op->guard_interval = GUARD_INTERVAL_1_4;
 369                         break;
 370                 default:
 371                         op->guard_interval = GUARD_INTERVAL_AUTO;
 372                         break;
 373         }
 374
 375         switch ( (tps >> 10) & 7)
 376         {
 377                 case 0:
 378                         op->hierarchy_information = HIERARCHY_NONE;
 379                         break;
 380                 case 1:
 381                         op->hierarchy_information = HIERARCHY_1;
 382                         break;
 383                 case 2:
 384                         op->hierarchy_information = HIERARCHY_2;
 385                         break;
 386                 case 3:
 387                         op->hierarchy_information = HIERARCHY_4;
 388                         break;
 389                 default:
 390                         op->hierarchy_information = HIERARCHY_AUTO;
 391                         break;
 392         }
 393
 394         param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
 395
 396         if (trl == 0x72)
 397                 op->bandwidth = BANDWIDTH_8_MHZ;
 398         else if (trl == 0x64)
 399                 op->bandwidth = BANDWIDTH_7_MHZ;
 400         else
 401                 op->bandwidth = BANDWIDTH_6_MHZ;
 402
 403
 404         if (mt352_read_register(state, STATUS_2) & 0x02)
 405                 param->inversion = INVERSION_OFF;
 406         else
 407                 param->inversion = INVERSION_ON;
 408
 409         return 0;
 410 }
 411
 412 static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
 413 {
 414         struct mt352_state* state = fe->demodulator_priv;
 415         int s0, s1, s3;
 416
 417         /* FIXME:
 418          *
 419          * The MT352 design manual from Zarlink states (page 46-47):
 420          *
 421          * Notes about the TUNER_GO register:
 422          *
 423          * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
 424          * byte is copied from the tuner to the STATUS_3 register and
 425          * completion of the read operation is indicated by bit-5 of the
 426          * INTERRUPT_3 register.
 427          */
 428
 429         if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
 430                 return -EREMOTEIO;
 431         if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
 432                 return -EREMOTEIO;
 433         if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
 434                 return -EREMOTEIO;
 435
 436         *status = 0;
 437         if (s0 & (1 << 4))
 438                 *status |= FE_HAS_CARRIER;
 439         if (s0 & (1 << 1))
 440                 *status |= FE_HAS_VITERBI;
 441         if (s0 & (1 << 5))
 442                 *status |= FE_HAS_LOCK;
 443         if (s1 & (1 << 1))
 444                 *status |= FE_HAS_SYNC;
 445         if (s3 & (1 << 6))
 446                 *status |= FE_HAS_SIGNAL;
 447
 448         if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
 449                       (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
 450                 *status &= ~FE_HAS_LOCK;
 451
 452         return 0;
 453 }
 454
 455 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
 456 {
 457         struct mt352_state* state = fe->demodulator_priv;
 458
 459         *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
 460                (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
 461                (mt352_read_register (state, RS_ERR_CNT_0));
 462
 463         return 0;
 464 }
 465
 466 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 467 {
 468         struct mt352_state* state = fe->demodulator_priv;
 469
 470         u16 signal = ((mt352_read_register(state, AGC_GAIN_1) << 8) & 0x0f) |
 471                       (mt352_read_register(state, AGC_GAIN_0));
 472
 473         *strength = ~signal;
 474         return 0;
 475 }
 476
 477 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
 478 {
 479         struct mt352_state* state = fe->demodulator_priv;
 480
 481         u8 _snr = mt352_read_register (state, SNR);
 482         *snr = (_snr << 8) | _snr;
 483
 484         return 0;
 485 }
 486
 487 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 488 {
 489         struct mt352_state* state = fe->demodulator_priv;
 490
 491         *ucblocks = (mt352_read_register (state,  RS_UBC_1) << 8) |
 492                     (mt352_read_register (state,  RS_UBC_0));
 493
 494         return 0;
 495 }
 496
 497 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
 498 {
 499         fe_tune_settings->min_delay_ms = 800;
 500         fe_tune_settings->step_size = 0;
 501         fe_tune_settings->max_drift = 0;
 502
 503         return 0;
 504 }
 505
 506 static int mt352_init(struct dvb_frontend* fe)
 507 {
 508         struct mt352_state* state = fe->demodulator_priv;
 509
 510         static u8 mt352_reset_attach [] = { RESET, 0xC0 };
 511
 512         dprintk("%s: hello\n",__FUNCTION__);
 513
 514         if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
 515             (mt352_read_register(state, CONFIG) & 0x20) == 0) {
 516
 517                 /* Do a "hard" reset */
 518                 mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
 519                 return state->config->demod_init(fe);
 520         }
 521
 522         return 0;
 523 }
 524
 525 static void mt352_release(struct dvb_frontend* fe)
 526 {
 527         struct mt352_state* state = fe->demodulator_priv;
 528         kfree(state);
 529 }
 530
 531 static struct dvb_frontend_ops mt352_ops;
 532
 533 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
 534                                   struct i2c_adapter* i2c)
 535 {
 536         struct mt352_state* state = NULL;
 537
 538         /* allocate memory for the internal state */
 539         state = kmalloc(sizeof(struct mt352_state), GFP_KERNEL);
 540         if (state == NULL) goto error;
 541         memset(state,0,sizeof(*state));
 542
 543         /* setup the state */
 544         state->config = config;
 545         state->i2c = i2c;
 546         memcpy(&state->ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
 547
 548         /* check if the demod is there */
 549         if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
 550
 551         /* create dvb_frontend */
 552         state->frontend.ops = &state->ops;
 553         state->frontend.demodulator_priv = state;
 554         return &state->frontend;
 555
 556 error:
 557         kfree(state);
 558         return NULL;
 559 }
 560
 561 static struct dvb_frontend_ops mt352_ops = {
 562
 563         .info = {
 564                 .name                   = "Zarlink MT352 DVB-T",
 565                 .type                   = FE_OFDM,
 566                 .frequency_min          = 174000000,
 567                 .frequency_max          = 862000000,
 568                 .frequency_stepsize     = 166667,
 569                 .frequency_tolerance    = 0,
 570                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 571                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 572                         FE_CAN_FEC_AUTO |
 573                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 574                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
 575                         FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
 576                         FE_CAN_MUTE_TS
 577         },
 578
 579         .release = mt352_release,
 580
 581         .init = mt352_init,
 582         .sleep = mt352_sleep,
 583
 584         .set_frontend = mt352_set_parameters,
 585         .get_frontend = mt352_get_parameters,
 586         .get_tune_settings = mt352_get_tune_settings,
 587
 588         .read_status = mt352_read_status,
 589         .read_ber = mt352_read_ber,
 590         .read_signal_strength = mt352_read_signal_strength,
 591         .read_snr = mt352_read_snr,
 592         .read_ucblocks = mt352_read_ucblocks,
 593 };
 594
 595 module_param(debug, int, 0644);
 596 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 597
 598 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
 599 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
 600 MODULE_LICENSE("GPL");
 601
 602 EXPORT_SYMBOL(mt352_attach);
 603 EXPORT_SYMBOL(mt352_write);
 604 EXPORT_SYMBOL(mt352_read);
 605 /*
 606  * Local variables:
 607  * c-basic-offset: 8
 608  * compile-command: "make DVB=1"
 609  * End:
 610  */