drivers/media/dvb/frontends/mt352.c

   1 /*
   2  *  Driver for Zarlink DVB-T MT352 demodulator
   3  *
   4  *  Written by Holger Waechtler <holger@qanu.de>
   5  *       and Daniel Mack <daniel@qanu.de>
   6  *
   7  *  AVerMedia AVerTV DVB-T 771 support by
   8  *       Wolfram Joost <dbox2@frokaschwei.de>
   9  *
  10  *  Support for Samsung TDTC9251DH01C(M) tuner
  11  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
  12  *                     Amauri  Celani  <acelani@essegi.net>
  13  *
  14  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
  15  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *
  26  *  GNU General Public License for more details.
  27  *
  28  *  You should have received a copy of the GNU General Public License
  29  *  along with this program; if not, write to the Free Software
  30  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/init.h>
  37 #include <linux/delay.h>
  38 #include <linux/string.h>
  39 #include <linux/slab.h>
  40
  41 #include "dvb_frontend.h"
  42 #include "mt352_priv.h"
  43 #include "mt352.h"
  44
  45 struct mt352_state {
  46         struct i2c_adapter* i2c;
  47         struct dvb_frontend frontend;
  48
  49         /* configuration settings */
  50         struct mt352_config config;
  51 };
  52
  53 static int debug;
  54 #define dprintk(args...) \
  55         do { \
  56                 if (debug) printk(KERN_DEBUG "mt352: " args); \
  57         } while (0)
  58
  59 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
  60 {
  61         struct mt352_state* state = fe->demodulator_priv;
  62         u8 buf[2] = { reg, val };
  63         struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
  64                                .buf = buf, .len = 2 };
  65         int err = i2c_transfer(state->i2c, &msg, 1);
  66         if (err != 1) {
  67                 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
  68                 return err;
  69         }
  70         return 0;
  71 }
  72
  73 static int _mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
  74 {
  75         int err,i;
  76         for (i=0; i < ilen-1; i++)
  77                 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
  78                         return err;
  79
  80         return 0;
  81 }
  82
  83 static int mt352_read_register(struct mt352_state* state, u8 reg)
  84 {
  85         int ret;
  86         u8 b0 [] = { reg };
  87         u8 b1 [] = { 0 };
  88         struct i2c_msg msg [] = { { .addr = state->config.demod_address,
  89                                     .flags = 0,
  90                                     .buf = b0, .len = 1 },
  91                                   { .addr = state->config.demod_address,
  92                                     .flags = I2C_M_RD,
  93                                     .buf = b1, .len = 1 } };
  94
  95         ret = i2c_transfer(state->i2c, msg, 2);
  96
  97         if (ret != 2) {
  98                 printk("%s: readreg error (reg=%d, ret==%i)\n",
  99                        __FUNCTION__, reg, ret);
 100                 return ret;
 101         }
 102
 103         return b1[0];
 104 }
 105
 106 static int mt352_sleep(struct dvb_frontend* fe)
 107 {
 108         static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
 109
 110         _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
 111         return 0;
 112 }
 113
 114 static void mt352_calc_nominal_rate(struct mt352_state* state,
 115                                     enum fe_bandwidth bandwidth,
 116                                     unsigned char *buf)
 117 {
 118         u32 adc_clock = 20480; /* 20.340 MHz */
 119         u32 bw,value;
 120
 121         switch (bandwidth) {
 122         case BANDWIDTH_6_MHZ:
 123                 bw = 6;
 124                 break;
 125         case BANDWIDTH_7_MHZ:
 126                 bw = 7;
 127                 break;
 128         case BANDWIDTH_8_MHZ:
 129         default:
 130                 bw = 8;
 131                 break;
 132         }
 133         if (state->config.adc_clock)
 134                 adc_clock = state->config.adc_clock;
 135
 136         value = 64 * bw * (1<<16) / (7 * 8);
 137         value = value * 1000 / adc_clock;
 138         dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
 139                 __FUNCTION__, bw, adc_clock, value);
 140         buf[0] = msb(value);
 141         buf[1] = lsb(value);
 142 }
 143
 144 static void mt352_calc_input_freq(struct mt352_state* state,
 145                                   unsigned char *buf)
 146 {
 147         int adc_clock = 20480; /* 20.480000 MHz */
 148         int if2       = 36167; /* 36.166667 MHz */
 149         int ife,value;
 150
 151         if (state->config.adc_clock)
 152                 adc_clock = state->config.adc_clock;
 153         if (state->config.if2)
 154                 if2 = state->config.if2;
 155
 156         ife = (2*adc_clock - if2);
 157         value = -16374 * ife / adc_clock;
 158         dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
 159                 __FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
 160         buf[0] = msb(value);
 161         buf[1] = lsb(value);
 162 }
 163
 164 static int mt352_set_parameters(struct dvb_frontend* fe,
 165                                 struct dvb_frontend_parameters *param)
 166 {
 167         struct mt352_state* state = fe->demodulator_priv;
 168         unsigned char buf[13];
 169         static unsigned char tuner_go[] = { 0x5d, 0x01 };
 170         static unsigned char fsm_go[]   = { 0x5e, 0x01 };
 171         unsigned int tps = 0;
 172         struct dvb_ofdm_parameters *op = &param->u.ofdm;
 173
 174         switch (op->code_rate_HP) {
 175                 case FEC_2_3:
 176                         tps |= (1 << 7);
 177                         break;
 178                 case FEC_3_4:
 179                         tps |= (2 << 7);
 180                         break;
 181                 case FEC_5_6:
 182                         tps |= (3 << 7);
 183                         break;
 184                 case FEC_7_8:
 185                         tps |= (4 << 7);
 186                         break;
 187                 case FEC_1_2:
 188                 case FEC_AUTO:
 189                         break;
 190                 default:
 191                         return -EINVAL;
 192         }
 193
 194         switch (op->code_rate_LP) {
 195                 case FEC_2_3:
 196                         tps |= (1 << 4);
 197                         break;
 198                 case FEC_3_4:
 199                         tps |= (2 << 4);
 200                         break;
 201                 case FEC_5_6:
 202                         tps |= (3 << 4);
 203                         break;
 204                 case FEC_7_8:
 205                         tps |= (4 << 4);
 206                         break;
 207                 case FEC_1_2:
 208                 case FEC_AUTO:
 209                         break;
 210                 case FEC_NONE:
 211                         if (op->hierarchy_information == HIERARCHY_AUTO ||
 212                             op->hierarchy_information == HIERARCHY_NONE)
 213                                 break;
 214                 default:
 215                         return -EINVAL;
 216         }
 217
 218         switch (op->constellation) {
 219                 case QPSK:
 220                         break;
 221                 case QAM_AUTO:
 222                 case QAM_16:
 223                         tps |= (1 << 13);
 224                         break;
 225                 case QAM_64:
 226                         tps |= (2 << 13);
 227                         break;
 228                 default:
 229                         return -EINVAL;
 230         }
 231
 232         switch (op->transmission_mode) {
 233                 case TRANSMISSION_MODE_2K:
 234                 case TRANSMISSION_MODE_AUTO:
 235                         break;
 236                 case TRANSMISSION_MODE_8K:
 237                         tps |= (1 << 0);
 238                         break;
 239                 default:
 240                         return -EINVAL;
 241         }
 242
 243         switch (op->guard_interval) {
 244                 case GUARD_INTERVAL_1_32:
 245                 case GUARD_INTERVAL_AUTO:
 246                         break;
 247                 case GUARD_INTERVAL_1_16:
 248                         tps |= (1 << 2);
 249                         break;
 250                 case GUARD_INTERVAL_1_8:
 251                         tps |= (2 << 2);
 252                         break;
 253                 case GUARD_INTERVAL_1_4:
 254                         tps |= (3 << 2);
 255                         break;
 256                 default:
 257                         return -EINVAL;
 258         }
 259
 260         switch (op->hierarchy_information) {
 261                 case HIERARCHY_AUTO:
 262                 case HIERARCHY_NONE:
 263                         break;
 264                 case HIERARCHY_1:
 265                         tps |= (1 << 10);
 266                         break;
 267                 case HIERARCHY_2:
 268                         tps |= (2 << 10);
 269                         break;
 270                 case HIERARCHY_4:
 271                         tps |= (3 << 10);
 272                         break;
 273                 default:
 274                         return -EINVAL;
 275         }
 276
 277
 278         buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
 279
 280         buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
 281         buf[2] = lsb(tps);
 282
 283         buf[3] = 0x50;  // old
 284 //      buf[3] = 0xf4;  // pinnacle
 285
 286         mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
 287         mt352_calc_input_freq(state, buf+6);
 288
 289         if (state->config.no_tuner) {
 290                 if (fe->ops.tuner_ops.set_params) {
 291                         fe->ops.tuner_ops.set_params(fe, param);
 292                         if (fe->ops.i2c_gate_ctrl)
 293                                 fe->ops.i2c_gate_ctrl(fe, 0);
 294                 }
 295
 296                 _mt352_write(fe, buf, 8);
 297                 _mt352_write(fe, fsm_go, 2);
 298         } else {
 299                 if (fe->ops.tuner_ops.calc_regs) {
 300                         fe->ops.tuner_ops.calc_regs(fe, param, buf+8, 5);
 301                         buf[8] <<= 1;
 302                         _mt352_write(fe, buf, sizeof(buf));
 303                         _mt352_write(fe, tuner_go, 2);
 304                 }
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int mt352_get_parameters(struct dvb_frontend* fe,
 311                                 struct dvb_frontend_parameters *param)
 312 {
 313         struct mt352_state* state = fe->demodulator_priv;
 314         u16 tps;
 315         u16 div;
 316         u8 trl;
 317         struct dvb_ofdm_parameters *op = &param->u.ofdm;
 318         static const u8 tps_fec_to_api[8] =
 319         {
 320                 FEC_1_2,
 321                 FEC_2_3,
 322                 FEC_3_4,
 323                 FEC_5_6,
 324                 FEC_7_8,
 325                 FEC_AUTO,
 326                 FEC_AUTO,
 327                 FEC_AUTO
 328         };
 329
 330         if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
 331                 return -EINVAL;
 332
 333         /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
 334          * the mt352 sometimes works with the wrong parameters
 335          */
 336         tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
 337         div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
 338         trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
 339
 340         op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
 341         op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
 342
 343         switch ( (tps >> 13) & 3)
 344         {
 345                 case 0:
 346                         op->constellation = QPSK;
 347                         break;
 348                 case 1:
 349                         op->constellation = QAM_16;
 350                         break;
 351                 case 2:
 352                         op->constellation = QAM_64;
 353                         break;
 354                 default:
 355                         op->constellation = QAM_AUTO;
 356                         break;
 357         }
 358
 359         op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
 360
 361         switch ( (tps >> 2) & 3)
 362         {
 363                 case 0:
 364                         op->guard_interval = GUARD_INTERVAL_1_32;
 365                         break;
 366                 case 1:
 367                         op->guard_interval = GUARD_INTERVAL_1_16;
 368                         break;
 369                 case 2:
 370                         op->guard_interval = GUARD_INTERVAL_1_8;
 371                         break;
 372                 case 3:
 373                         op->guard_interval = GUARD_INTERVAL_1_4;
 374                         break;
 375                 default:
 376                         op->guard_interval = GUARD_INTERVAL_AUTO;
 377                         break;
 378         }
 379
 380         switch ( (tps >> 10) & 7)
 381         {
 382                 case 0:
 383                         op->hierarchy_information = HIERARCHY_NONE;
 384                         break;
 385                 case 1:
 386                         op->hierarchy_information = HIERARCHY_1;
 387                         break;
 388                 case 2:
 389                         op->hierarchy_information = HIERARCHY_2;
 390                         break;
 391                 case 3:
 392                         op->hierarchy_information = HIERARCHY_4;
 393                         break;
 394                 default:
 395                         op->hierarchy_information = HIERARCHY_AUTO;
 396                         break;
 397         }
 398
 399         param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
 400
 401         if (trl == 0x72)
 402                 op->bandwidth = BANDWIDTH_8_MHZ;
 403         else if (trl == 0x64)
 404                 op->bandwidth = BANDWIDTH_7_MHZ;
 405         else
 406                 op->bandwidth = BANDWIDTH_6_MHZ;
 407
 408
 409         if (mt352_read_register(state, STATUS_2) & 0x02)
 410                 param->inversion = INVERSION_OFF;
 411         else
 412                 param->inversion = INVERSION_ON;
 413
 414         return 0;
 415 }
 416
 417 static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
 418 {
 419         struct mt352_state* state = fe->demodulator_priv;
 420         int s0, s1, s3;
 421
 422         /* FIXME:
 423          *
 424          * The MT352 design manual from Zarlink states (page 46-47):
 425          *
 426          * Notes about the TUNER_GO register:
 427          *
 428          * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
 429          * byte is copied from the tuner to the STATUS_3 register and
 430          * completion of the read operation is indicated by bit-5 of the
 431          * INTERRUPT_3 register.
 432          */
 433
 434         if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
 435                 return -EREMOTEIO;
 436         if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
 437                 return -EREMOTEIO;
 438         if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
 439                 return -EREMOTEIO;
 440
 441         *status = 0;
 442         if (s0 & (1 << 4))
 443                 *status |= FE_HAS_CARRIER;
 444         if (s0 & (1 << 1))
 445                 *status |= FE_HAS_VITERBI;
 446         if (s0 & (1 << 5))
 447                 *status |= FE_HAS_LOCK;
 448         if (s1 & (1 << 1))
 449                 *status |= FE_HAS_SYNC;
 450         if (s3 & (1 << 6))
 451                 *status |= FE_HAS_SIGNAL;
 452
 453         if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
 454                       (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
 455                 *status &= ~FE_HAS_LOCK;
 456
 457         return 0;
 458 }
 459
 460 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
 461 {
 462         struct mt352_state* state = fe->demodulator_priv;
 463
 464         *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
 465                (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
 466                (mt352_read_register (state, RS_ERR_CNT_0));
 467
 468         return 0;
 469 }
 470
 471 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 472 {
 473         struct mt352_state* state = fe->demodulator_priv;
 474
 475         /* align the 12 bit AGC gain with the most significant bits */
 476         u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
 477                 (mt352_read_register(state, AGC_GAIN_0) << 4);
 478
 479         /* inverse of gain is signal strength */
 480         *strength = ~signal;
 481         return 0;
 482 }
 483
 484 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
 485 {
 486         struct mt352_state* state = fe->demodulator_priv;
 487
 488         u8 _snr = mt352_read_register (state, SNR);
 489         *snr = (_snr << 8) | _snr;
 490
 491         return 0;
 492 }
 493
 494 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 495 {
 496         struct mt352_state* state = fe->demodulator_priv;
 497
 498         *ucblocks = (mt352_read_register (state,  RS_UBC_1) << 8) |
 499                     (mt352_read_register (state,  RS_UBC_0));
 500
 501         return 0;
 502 }
 503
 504 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
 505 {
 506         fe_tune_settings->min_delay_ms = 800;
 507         fe_tune_settings->step_size = 0;
 508         fe_tune_settings->max_drift = 0;
 509
 510         return 0;
 511 }
 512
 513 static int mt352_init(struct dvb_frontend* fe)
 514 {
 515         struct mt352_state* state = fe->demodulator_priv;
 516
 517         static u8 mt352_reset_attach [] = { RESET, 0xC0 };
 518
 519         dprintk("%s: hello\n",__FUNCTION__);
 520
 521         if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
 522             (mt352_read_register(state, CONFIG) & 0x20) == 0) {
 523
 524                 /* Do a "hard" reset */
 525                 _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
 526                 return state->config.demod_init(fe);
 527         }
 528
 529         return 0;
 530 }
 531
 532 static void mt352_release(struct dvb_frontend* fe)
 533 {
 534         struct mt352_state* state = fe->demodulator_priv;
 535         kfree(state);
 536 }
 537
 538 static struct dvb_frontend_ops mt352_ops;
 539
 540 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
 541                                   struct i2c_adapter* i2c)
 542 {
 543         struct mt352_state* state = NULL;
 544
 545         /* allocate memory for the internal state */
 546         state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
 547         if (state == NULL) goto error;
 548
 549         /* setup the state */
 550         state->i2c = i2c;
 551         memcpy(&state->config,config,sizeof(struct mt352_config));
 552
 553         /* check if the demod is there */
 554         if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
 555
 556         /* create dvb_frontend */
 557         memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
 558         state->frontend.demodulator_priv = state;
 559         return &state->frontend;
 560
 561 error:
 562         kfree(state);
 563         return NULL;
 564 }
 565
 566 static struct dvb_frontend_ops mt352_ops = {
 567
 568         .info = {
 569                 .name                   = "Zarlink MT352 DVB-T",
 570                 .type                   = FE_OFDM,
 571                 .frequency_min          = 174000000,
 572                 .frequency_max          = 862000000,
 573                 .frequency_stepsize     = 166667,
 574                 .frequency_tolerance    = 0,
 575                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 576                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 577                         FE_CAN_FEC_AUTO |
 578                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 579                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
 580                         FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
 581                         FE_CAN_MUTE_TS
 582         },
 583
 584         .release = mt352_release,
 585
 586         .init = mt352_init,
 587         .sleep = mt352_sleep,
 588         .write = _mt352_write,
 589
 590         .set_frontend = mt352_set_parameters,
 591         .get_frontend = mt352_get_parameters,
 592         .get_tune_settings = mt352_get_tune_settings,
 593
 594         .read_status = mt352_read_status,
 595         .read_ber = mt352_read_ber,
 596         .read_signal_strength = mt352_read_signal_strength,
 597         .read_snr = mt352_read_snr,
 598         .read_ucblocks = mt352_read_ucblocks,
 599 };
 600
 601 module_param(debug, int, 0644);
 602 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 603
 604 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
 605 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
 606 MODULE_LICENSE("GPL");
 607
 608 EXPORT_SYMBOL(mt352_attach);