drivers/media/dvb/frontends/stv0297.c

   1 /*
   2     Driver for STV0297 demodulator
   3
   4     Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
   5     Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 #include <linux/init.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/delay.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/slab.h>
  29
  30 #include "dvb_frontend.h"
  31 #include "stv0297.h"
  32
  33 struct stv0297_state {
  34         struct i2c_adapter *i2c;
  35         struct dvb_frontend_ops ops;
  36         const struct stv0297_config *config;
  37         struct dvb_frontend frontend;
  38
  39         unsigned long base_freq;
  40 };
  41
  42 #if 1
  43 #define dprintk(x...) printk(x)
  44 #else
  45 #define dprintk(x...)
  46 #endif
  47
  48 #define STV0297_CLOCK_KHZ   28900
  49
  50
  51 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
  52 {
  53         int ret;
  54         u8 buf[] = { reg, data };
  55         struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
  56
  57         ret = i2c_transfer(state->i2c, &msg, 1);
  58
  59         if (ret != 1)
  60                 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
  61                         "ret == %i)\n", __FUNCTION__, reg, data, ret);
  62
  63         return (ret != 1) ? -1 : 0;
  64 }
  65
  66 static int stv0297_readreg(struct stv0297_state *state, u8 reg)
  67 {
  68         int ret;
  69         u8 b0[] = { reg };
  70         u8 b1[] = { 0 };
  71         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len =
  72                                   1},
  73         {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  74         };
  75
  76         // this device needs a STOP between the register and data
  77         if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
  78                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
  79                 return -1;
  80         }
  81         if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
  82                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
  83                 return -1;
  84         }
  85
  86         return b1[0];
  87 }
  88
  89 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
  90 {
  91         int val;
  92
  93         val = stv0297_readreg(state, reg);
  94         val &= ~mask;
  95         val |= (data & mask);
  96         stv0297_writereg(state, reg, val);
  97
  98         return 0;
  99 }
 100
 101 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
 102 {
 103         int ret;
 104         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
 105                                   &reg1,.len = 1},
 106         {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
 107         };
 108
 109         // this device needs a STOP between the register and data
 110         if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
 111                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
 112                 return -1;
 113         }
 114         if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
 115                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
 116                 return -1;
 117         }
 118
 119         return 0;
 120 }
 121
 122 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
 123 {
 124         u64 tmp;
 125
 126         tmp = stv0297_readreg(state, 0x55);
 127         tmp |= stv0297_readreg(state, 0x56) << 8;
 128         tmp |= stv0297_readreg(state, 0x57) << 16;
 129         tmp |= stv0297_readreg(state, 0x58) << 24;
 130
 131         tmp *= STV0297_CLOCK_KHZ;
 132         tmp >>= 32;
 133
 134         return (u32) tmp;
 135 }
 136
 137 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
 138 {
 139         long tmp;
 140
 141         tmp = 131072L * srate;  /* 131072 = 2^17  */
 142         tmp = tmp / (STV0297_CLOCK_KHZ / 4);    /* 1/4 = 2^-2 */
 143         tmp = tmp * 8192L;      /* 8192 = 2^13 */
 144
 145         stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
 146         stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
 147         stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
 148         stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
 149 }
 150
 151 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
 152 {
 153         long tmp;
 154
 155         tmp = (long) fshift *262144L;   /* 262144 = 2*18 */
 156         tmp /= symrate;
 157         tmp *= 1024;            /* 1024 = 2*10   */
 158
 159         // adjust
 160         if (tmp >= 0) {
 161                 tmp += 500000;
 162         } else {
 163                 tmp -= 500000;
 164         }
 165         tmp /= 1000000;
 166
 167         stv0297_writereg(state, 0x60, tmp & 0xFF);
 168         stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
 169 }
 170
 171 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
 172 {
 173         long tmp;
 174
 175         /* symrate is hardcoded to 10000 */
 176         tmp = offset * 26844L;  /* (2**28)/10000 */
 177         if (tmp < 0)
 178                 tmp += 0x10000000;
 179         tmp &= 0x0FFFFFFF;
 180
 181         stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
 182         stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
 183         stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
 184         stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
 185 }
 186
 187 /*
 188 static long stv0297_get_carrieroffset(struct stv0297_state *state)
 189 {
 190         s64 tmp;
 191
 192         stv0297_writereg(state, 0x6B, 0x00);
 193
 194         tmp = stv0297_readreg(state, 0x66);
 195         tmp |= (stv0297_readreg(state, 0x67) << 8);
 196         tmp |= (stv0297_readreg(state, 0x68) << 16);
 197         tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
 198
 199         tmp *= stv0297_get_symbolrate(state);
 200         tmp >>= 28;
 201
 202         return (s32) tmp;
 203 }
 204 */
 205
 206 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
 207 {
 208         s32 tmp;
 209
 210         if (freq > 10000)
 211                 freq -= STV0297_CLOCK_KHZ;
 212
 213         tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
 214         tmp = (freq * 1000) / tmp;
 215         if (tmp > 0xffff)
 216                 tmp = 0xffff;
 217
 218         stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
 219         stv0297_writereg(state, 0x21, tmp >> 8);
 220         stv0297_writereg(state, 0x20, tmp);
 221 }
 222
 223 static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
 224 {
 225         int val = 0;
 226
 227         switch (modulation) {
 228         case QAM_16:
 229                 val = 0;
 230                 break;
 231
 232         case QAM_32:
 233                 val = 1;
 234                 break;
 235
 236         case QAM_64:
 237                 val = 4;
 238                 break;
 239
 240         case QAM_128:
 241                 val = 2;
 242                 break;
 243
 244         case QAM_256:
 245                 val = 3;
 246                 break;
 247
 248         default:
 249                 return -EINVAL;
 250         }
 251
 252         stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
 253
 254         return 0;
 255 }
 256
 257 static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
 258 {
 259         int val = 0;
 260
 261         switch (inversion) {
 262         case INVERSION_OFF:
 263                 val = 0;
 264                 break;
 265
 266         case INVERSION_ON:
 267                 val = 1;
 268                 break;
 269
 270         default:
 271                 return -EINVAL;
 272         }
 273
 274         stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
 275
 276         return 0;
 277 }
 278
 279 int stv0297_enable_plli2c(struct dvb_frontend *fe)
 280 {
 281         struct stv0297_state *state = fe->demodulator_priv;
 282
 283         stv0297_writereg(state, 0x87, 0x78);
 284         stv0297_writereg(state, 0x86, 0xc8);
 285
 286         return 0;
 287 }
 288
 289 static int stv0297_init(struct dvb_frontend *fe)
 290 {
 291         struct stv0297_state *state = fe->demodulator_priv;
 292         int i;
 293
 294         /* load init table */
 295         for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
 296                 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
 297         msleep(200);
 298
 299         if (state->config->pll_init)
 300                 state->config->pll_init(fe);
 301
 302         return 0;
 303 }
 304
 305 static int stv0297_sleep(struct dvb_frontend *fe)
 306 {
 307         struct stv0297_state *state = fe->demodulator_priv;
 308
 309         stv0297_writereg_mask(state, 0x80, 1, 1);
 310
 311         return 0;
 312 }
 313
 314 static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
 315 {
 316         struct stv0297_state *state = fe->demodulator_priv;
 317
 318         u8 sync = stv0297_readreg(state, 0xDF);
 319
 320         *status = 0;
 321         if (sync & 0x80)
 322                 *status |=
 323                         FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
 324         return 0;
 325 }
 326
 327 static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
 328 {
 329         struct stv0297_state *state = fe->demodulator_priv;
 330         u8 BER[3];
 331
 332         stv0297_writereg(state, 0xA0, 0x80);    // Start Counting bit errors for 4096 Bytes
 333         mdelay(25);             // Hopefully got 4096 Bytes
 334         stv0297_readregs(state, 0xA0, BER, 3);
 335         mdelay(25);
 336         *ber = (BER[2] << 8 | BER[1]) / (8 * 4096);
 337
 338         return 0;
 339 }
 340
 341
 342 static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
 343 {
 344         struct stv0297_state *state = fe->demodulator_priv;
 345         u8 STRENGTH[2];
 346
 347         stv0297_readregs(state, 0x41, STRENGTH, 2);
 348         *strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
 349
 350         return 0;
 351 }
 352
 353 static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
 354 {
 355         struct stv0297_state *state = fe->demodulator_priv;
 356         u8 SNR[2];
 357
 358         stv0297_readregs(state, 0x07, SNR, 2);
 359         *snr = SNR[1] << 8 | SNR[0];
 360
 361         return 0;
 362 }
 363
 364 static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 365 {
 366         struct stv0297_state *state = fe->demodulator_priv;
 367
 368         *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
 369                 | stv0297_readreg(state, 0xD4);
 370
 371         return 0;
 372 }
 373
 374 static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 375 {
 376         struct stv0297_state *state = fe->demodulator_priv;
 377         int u_threshold;
 378         int initial_u;
 379         int blind_u;
 380         int delay;
 381         int sweeprate;
 382         int carrieroffset;
 383         unsigned long starttime;
 384         unsigned long timeout;
 385         fe_spectral_inversion_t inversion;
 386
 387         switch (p->u.qam.modulation) {
 388         case QAM_16:
 389         case QAM_32:
 390         case QAM_64:
 391                 delay = 100;
 392                 sweeprate = 1500;
 393                 break;
 394
 395         case QAM_128:
 396                 delay = 150;
 397                 sweeprate = 1000;
 398                 break;
 399
 400         case QAM_256:
 401                 delay = 200;
 402                 sweeprate = 500;
 403                 break;
 404
 405         default:
 406                 return -EINVAL;
 407         }
 408
 409         // determine inversion dependant parameters
 410         inversion = p->inversion;
 411         if (state->config->invert)
 412                 inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 413         carrieroffset = -330;
 414         switch (inversion) {
 415         case INVERSION_OFF:
 416                 break;
 417
 418         case INVERSION_ON:
 419                 sweeprate = -sweeprate;
 420                 carrieroffset = -carrieroffset;
 421                 break;
 422
 423         default:
 424                 return -EINVAL;
 425         }
 426
 427         stv0297_init(fe);
 428         state->config->pll_set(fe, p);
 429
 430         /* clear software interrupts */
 431         stv0297_writereg(state, 0x82, 0x0);
 432
 433         /* set initial demodulation frequency */
 434         stv0297_set_initialdemodfreq(state, 7250);
 435
 436         /* setup AGC */
 437         stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
 438         stv0297_writereg(state, 0x41, 0x00);
 439         stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
 440         stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
 441         stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
 442         stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
 443         stv0297_writereg(state, 0x72, 0x00);
 444         stv0297_writereg(state, 0x73, 0x00);
 445         stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
 446         stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
 447         stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
 448
 449         /* setup STL */
 450         stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
 451         stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
 452         stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
 453         stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
 454         stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
 455
 456         /* disable frequency sweep */
 457         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 458
 459         /* reset deinterleaver */
 460         stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
 461         stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
 462
 463         /* ??? */
 464         stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
 465         stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
 466
 467         /* reset equaliser */
 468         u_threshold = stv0297_readreg(state, 0x00) & 0xf;
 469         initial_u = stv0297_readreg(state, 0x01) >> 4;
 470         blind_u = stv0297_readreg(state, 0x01) & 0xf;
 471         stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
 472         stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
 473         stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
 474         stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
 475         stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
 476
 477         /* data comes from internal A/D */
 478         stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
 479
 480         /* clear phase registers */
 481         stv0297_writereg(state, 0x63, 0x00);
 482         stv0297_writereg(state, 0x64, 0x00);
 483         stv0297_writereg(state, 0x65, 0x00);
 484         stv0297_writereg(state, 0x66, 0x00);
 485         stv0297_writereg(state, 0x67, 0x00);
 486         stv0297_writereg(state, 0x68, 0x00);
 487         stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
 488
 489         /* set parameters */
 490         stv0297_set_qam(state, p->u.qam.modulation);
 491         stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);
 492         stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
 493         stv0297_set_carrieroffset(state, carrieroffset);
 494         stv0297_set_inversion(state, inversion);
 495
 496         /* kick off lock */
 497         /* Disable corner detection for higher QAMs */
 498         if (p->u.qam.modulation == QAM_128 ||
 499                 p->u.qam.modulation == QAM_256)
 500                 stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
 501         else
 502                 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
 503
 504         stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
 505         stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
 506         stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
 507         stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
 508         stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
 509         stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
 510         stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
 511
 512         /* wait for WGAGC lock */
 513         starttime = jiffies;
 514         timeout = jiffies + msecs_to_jiffies(2000);
 515         while (time_before(jiffies, timeout)) {
 516                 msleep(10);
 517                 if (stv0297_readreg(state, 0x43) & 0x08)
 518                         break;
 519         }
 520         if (time_after(jiffies, timeout)) {
 521                 goto timeout;
 522         }
 523         msleep(20);
 524
 525         /* wait for equaliser partial convergence */
 526         timeout = jiffies + msecs_to_jiffies(500);
 527         while (time_before(jiffies, timeout)) {
 528                 msleep(10);
 529
 530                 if (stv0297_readreg(state, 0x82) & 0x04) {
 531                         break;
 532                 }
 533         }
 534         if (time_after(jiffies, timeout)) {
 535                 goto timeout;
 536         }
 537
 538         /* wait for equaliser full convergence */
 539         timeout = jiffies + msecs_to_jiffies(delay);
 540         while (time_before(jiffies, timeout)) {
 541                 msleep(10);
 542
 543                 if (stv0297_readreg(state, 0x82) & 0x08) {
 544                         break;
 545                 }
 546         }
 547         if (time_after(jiffies, timeout)) {
 548                 goto timeout;
 549         }
 550
 551         /* disable sweep */
 552         stv0297_writereg_mask(state, 0x6a, 1, 0);
 553         stv0297_writereg_mask(state, 0x88, 8, 0);
 554
 555         /* wait for main lock */
 556         timeout = jiffies + msecs_to_jiffies(20);
 557         while (time_before(jiffies, timeout)) {
 558                 msleep(10);
 559
 560                 if (stv0297_readreg(state, 0xDF) & 0x80) {
 561                         break;
 562                 }
 563         }
 564         if (time_after(jiffies, timeout)) {
 565                 goto timeout;
 566         }
 567         msleep(100);
 568
 569         /* is it still locked after that delay? */
 570         if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
 571                 goto timeout;
 572         }
 573
 574         /* success!! */
 575         stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
 576         state->base_freq = p->frequency;
 577         return 0;
 578
 579 timeout:
 580         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 581         return 0;
 582 }
 583
 584 static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 585 {
 586         struct stv0297_state *state = fe->demodulator_priv;
 587         int reg_00, reg_83;
 588
 589         reg_00 = stv0297_readreg(state, 0x00);
 590         reg_83 = stv0297_readreg(state, 0x83);
 591
 592         p->frequency = state->base_freq;
 593         p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
 594         if (state->config->invert)
 595                 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 596         p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
 597         p->u.qam.fec_inner = FEC_NONE;
 598
 599         switch ((reg_00 >> 4) & 0x7) {
 600         case 0:
 601                 p->u.qam.modulation = QAM_16;
 602                 break;
 603         case 1:
 604                 p->u.qam.modulation = QAM_32;
 605                 break;
 606         case 2:
 607                 p->u.qam.modulation = QAM_128;
 608                 break;
 609         case 3:
 610                 p->u.qam.modulation = QAM_256;
 611                 break;
 612         case 4:
 613                 p->u.qam.modulation = QAM_64;
 614                 break;
 615         }
 616
 617         return 0;
 618 }
 619
 620 static void stv0297_release(struct dvb_frontend *fe)
 621 {
 622         struct stv0297_state *state = fe->demodulator_priv;
 623         kfree(state);
 624 }
 625
 626 static struct dvb_frontend_ops stv0297_ops;
 627
 628 struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
 629                                     struct i2c_adapter *i2c)
 630 {
 631         struct stv0297_state *state = NULL;
 632
 633         /* allocate memory for the internal state */
 634         state = kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
 635         if (state == NULL)
 636                 goto error;
 637
 638         /* setup the state */
 639         state->config = config;
 640         state->i2c = i2c;
 641         memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
 642         state->base_freq = 0;
 643
 644         /* check if the demod is there */
 645         if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
 646                 goto error;
 647
 648         /* create dvb_frontend */
 649         state->frontend.ops = &state->ops;
 650         state->frontend.demodulator_priv = state;
 651         return &state->frontend;
 652
 653 error:
 654         kfree(state);
 655         return NULL;
 656 }
 657
 658 static struct dvb_frontend_ops stv0297_ops = {
 659
 660         .info = {
 661                  .name = "ST STV0297 DVB-C",
 662                  .type = FE_QAM,
 663                  .frequency_min = 64000000,
 664                  .frequency_max = 1300000000,
 665                  .frequency_stepsize = 62500,
 666                  .symbol_rate_min = 870000,
 667                  .symbol_rate_max = 11700000,
 668                  .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
 669                  FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
 670
 671         .release = stv0297_release,
 672
 673         .init = stv0297_init,
 674         .sleep = stv0297_sleep,
 675
 676         .set_frontend = stv0297_set_frontend,
 677         .get_frontend = stv0297_get_frontend,
 678
 679         .read_status = stv0297_read_status,
 680         .read_ber = stv0297_read_ber,
 681         .read_signal_strength = stv0297_read_signal_strength,
 682         .read_snr = stv0297_read_snr,
 683         .read_ucblocks = stv0297_read_ucblocks,
 684 };
 685
 686 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
 687 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
 688 MODULE_LICENSE("GPL");
 689
 690 EXPORT_SYMBOL(stv0297_attach);
 691 EXPORT_SYMBOL(stv0297_enable_plli2c);