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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[mirror_ubuntu-zesty-kernel.git] / drivers / media / dvb / frontends / stv0900_core.c
1 /*
2 * stv0900_core.c
3 *
4 * Driver for ST STV0900 satellite demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
31
32 #include "stv0900.h"
33 #include "stv0900_reg.h"
34 #include "stv0900_priv.h"
35 #include "stv0900_init.h"
36
37 static int stvdebug = 1;
38 module_param_named(debug, stvdebug, int, 0644);
39
40 /* internal params node */
41 struct stv0900_inode {
42 /* pointer for internal params, one for each pair of demods */
43 struct stv0900_internal *internal;
44 struct stv0900_inode *next_inode;
45 };
46
47 /* first internal params */
48 static struct stv0900_inode *stv0900_first_inode;
49
50 /* find chip by i2c adapter and i2c address */
51 static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
52 u8 i2c_addr)
53 {
54 struct stv0900_inode *temp_chip = stv0900_first_inode;
55
56 if (temp_chip != NULL) {
57 /*
58 Search of the last stv0900 chip or
59 find it by i2c adapter and i2c address */
60 while ((temp_chip != NULL) &&
61 ((temp_chip->internal->i2c_adap != i2c_adap) ||
62 (temp_chip->internal->i2c_addr != i2c_addr)))
63
64 temp_chip = temp_chip->next_inode;
65
66 }
67
68 return temp_chip;
69 }
70
71 /* deallocating chip */
72 static void remove_inode(struct stv0900_internal *internal)
73 {
74 struct stv0900_inode *prev_node = stv0900_first_inode;
75 struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
76 internal->i2c_addr);
77
78 if (del_node != NULL) {
79 if (del_node == stv0900_first_inode) {
80 stv0900_first_inode = del_node->next_inode;
81 } else {
82 while (prev_node->next_inode != del_node)
83 prev_node = prev_node->next_inode;
84
85 if (del_node->next_inode == NULL)
86 prev_node->next_inode = NULL;
87 else
88 prev_node->next_inode =
89 prev_node->next_inode->next_inode;
90 }
91
92 kfree(del_node);
93 }
94 }
95
96 /* allocating new chip */
97 static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
98 {
99 struct stv0900_inode *new_node = stv0900_first_inode;
100
101 if (new_node == NULL) {
102 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
103 stv0900_first_inode = new_node;
104 } else {
105 while (new_node->next_inode != NULL)
106 new_node = new_node->next_inode;
107
108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
109 if (new_node->next_inode != NULL)
110 new_node = new_node->next_inode;
111 else
112 new_node = NULL;
113 }
114
115 if (new_node != NULL) {
116 new_node->internal = internal;
117 new_node->next_inode = NULL;
118 }
119
120 return new_node;
121 }
122
123 s32 ge2comp(s32 a, s32 width)
124 {
125 if (width == 32)
126 return a;
127 else
128 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
129 }
130
131 void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
132 u8 reg_data)
133 {
134 u8 data[3];
135 int ret;
136 struct i2c_msg i2cmsg = {
137 .addr = i_params->i2c_addr,
138 .flags = 0,
139 .len = 3,
140 .buf = data,
141 };
142
143 data[0] = MSB(reg_addr);
144 data[1] = LSB(reg_addr);
145 data[2] = reg_data;
146
147 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
148 if (ret != 1)
149 dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
150 }
151
152 u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg_addr)
153 {
154 u8 data[2];
155 int ret;
156 struct i2c_msg i2cmsg = {
157 .addr = i_params->i2c_addr,
158 .flags = 0,
159 .len = 2,
160 .buf = data,
161 };
162
163 data[0] = MSB(reg_addr);
164 data[1] = LSB(reg_addr);
165
166 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
167 if (ret != 1)
168 dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
169
170 i2cmsg.flags = I2C_M_RD;
171 i2cmsg.len = 1;
172 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
173 if (ret != 1)
174 dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
175
176 return data[0];
177 }
178
179 void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
180 {
181 u8 position = 0, i = 0;
182
183 (*mask) = label & 0xff;
184
185 while ((position == 0) && (i < 8)) {
186 position = ((*mask) >> i) & 0x01;
187 i++;
188 }
189
190 (*pos) = (i - 1);
191 }
192
193 void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val)
194 {
195 u8 reg, mask, pos;
196
197 reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff);
198 extract_mask_pos(label, &mask, &pos);
199
200 val = mask & (val << pos);
201
202 reg = (reg & (~mask)) | val;
203 stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg);
204
205 }
206
207 u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label)
208 {
209 u8 val = 0xff;
210 u8 mask, pos;
211
212 extract_mask_pos(label, &mask, &pos);
213
214 val = stv0900_read_reg(i_params, label >> 16);
215 val = (val & mask) >> pos;
216
217 return val;
218 }
219
220 enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
221 {
222 s32 i;
223 enum fe_stv0900_error error;
224
225 if (i_params != NULL) {
226 i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
227 if (i_params->errs == STV0900_NO_ERROR) {
228 /*Startup sequence*/
229 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
230 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
231 stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
232 stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
233 stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x24);
234 stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x24);
235 stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
236 msleep(3);
237 stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
238
239 switch (i_params->clkmode) {
240 case 0:
241 case 2:
242 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
243 | i_params->clkmode);
244 break;
245 default:
246 /* preserve SELOSCI bit */
247 i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
248 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
249 break;
250 }
251
252 msleep(3);
253 for (i = 0; i < 182; i++)
254 stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
255
256 if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {
257 stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
258 for (i = 0; i < 32; i++)
259 stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
260 }
261
262 stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c);
263 stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c);
264 stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
265 stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
266 }
267 error = i_params->errs;
268 } else
269 error = STV0900_INVALID_HANDLE;
270
271 return error;
272
273 }
274
275 u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
276 {
277 u32 mclk = 90000000, div = 0, ad_div = 0;
278
279 div = stv0900_get_bits(i_params, F0900_M_DIV);
280 ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
281
282 mclk = (div + 1) * ext_clk / ad_div;
283
284 dprintk(KERN_INFO "%s: Calculated Mclk = %d\n", __func__, mclk);
285
286 return mclk;
287 }
288
289 enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk)
290 {
291 enum fe_stv0900_error error = STV0900_NO_ERROR;
292 u32 m_div, clk_sel;
293
294 dprintk(KERN_INFO "%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
295 i_params->quartz);
296
297 if (i_params == NULL)
298 error = STV0900_INVALID_HANDLE;
299 else {
300 if (i_params->errs)
301 error = STV0900_I2C_ERROR;
302 else {
303 clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
304 m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
305 stv0900_write_bits(i_params, F0900_M_DIV, m_div);
306 i_params->mclk = stv0900_get_mclk_freq(i_params,
307 i_params->quartz);
308
309 /*Set the DiseqC frequency to 22KHz */
310 /*
311 Formula:
312 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
313 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
314 */
315 m_div = i_params->mclk / 704000;
316 stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
317 stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
318
319 stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
320 stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
321
322 if ((i_params->errs))
323 error = STV0900_I2C_ERROR;
324 }
325 }
326
327 return error;
328 }
329
330 u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
331 enum fe_stv0900_demod_num demod)
332 {
333 u32 lsb, msb, hsb, err_val;
334 s32 err1field_hsb, err1field_msb, err1field_lsb;
335 s32 err2field_hsb, err2field_msb, err2field_lsb;
336
337 dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
338 dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
339 dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
340
341 dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
342 dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
343 dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
344
345 switch (cntr) {
346 case 0:
347 default:
348 hsb = stv0900_get_bits(i_params, err1field_hsb);
349 msb = stv0900_get_bits(i_params, err1field_msb);
350 lsb = stv0900_get_bits(i_params, err1field_lsb);
351 break;
352 case 1:
353 hsb = stv0900_get_bits(i_params, err2field_hsb);
354 msb = stv0900_get_bits(i_params, err2field_msb);
355 lsb = stv0900_get_bits(i_params, err2field_lsb);
356 break;
357 }
358
359 err_val = (hsb << 16) + (msb << 8) + (lsb);
360
361 return err_val;
362 }
363
364 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
365 {
366 struct stv0900_state *state = fe->demodulator_priv;
367 struct stv0900_internal *i_params = state->internal;
368 enum fe_stv0900_demod_num demod = state->demod;
369
370 u32 fi2c;
371
372 dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
373 if (enable)
374 stv0900_write_bits(i_params, fi2c, 1);
375
376 return 0;
377 }
378
379 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
380 enum fe_stv0900_clock_type path1_ts,
381 enum fe_stv0900_clock_type path2_ts)
382 {
383
384 dprintk(KERN_INFO "%s\n", __func__);
385
386 if (i_params->chip_id >= 0x20) {
387 switch (path1_ts) {
388 case STV0900_PARALLEL_PUNCT_CLOCK:
389 case STV0900_DVBCI_CLOCK:
390 switch (path2_ts) {
391 case STV0900_SERIAL_PUNCT_CLOCK:
392 case STV0900_SERIAL_CONT_CLOCK:
393 default:
394 stv0900_write_reg(i_params, R0900_TSGENERAL,
395 0x00);
396 break;
397 case STV0900_PARALLEL_PUNCT_CLOCK:
398 case STV0900_DVBCI_CLOCK:
399 stv0900_write_reg(i_params, R0900_TSGENERAL,
400 0x06);
401 stv0900_write_bits(i_params,
402 F0900_P1_TSFIFO_MANSPEED, 3);
403 stv0900_write_bits(i_params,
404 F0900_P2_TSFIFO_MANSPEED, 0);
405 stv0900_write_reg(i_params,
406 R0900_P1_TSSPEED, 0x14);
407 stv0900_write_reg(i_params,
408 R0900_P2_TSSPEED, 0x28);
409 break;
410 }
411 break;
412 case STV0900_SERIAL_PUNCT_CLOCK:
413 case STV0900_SERIAL_CONT_CLOCK:
414 default:
415 switch (path2_ts) {
416 case STV0900_SERIAL_PUNCT_CLOCK:
417 case STV0900_SERIAL_CONT_CLOCK:
418 default:
419 stv0900_write_reg(i_params,
420 R0900_TSGENERAL, 0x0C);
421 break;
422 case STV0900_PARALLEL_PUNCT_CLOCK:
423 case STV0900_DVBCI_CLOCK:
424 stv0900_write_reg(i_params,
425 R0900_TSGENERAL, 0x0A);
426 dprintk(KERN_INFO "%s: 0x0a\n", __func__);
427 break;
428 }
429 break;
430 }
431 } else {
432 switch (path1_ts) {
433 case STV0900_PARALLEL_PUNCT_CLOCK:
434 case STV0900_DVBCI_CLOCK:
435 switch (path2_ts) {
436 case STV0900_SERIAL_PUNCT_CLOCK:
437 case STV0900_SERIAL_CONT_CLOCK:
438 default:
439 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
440 0x10);
441 break;
442 case STV0900_PARALLEL_PUNCT_CLOCK:
443 case STV0900_DVBCI_CLOCK:
444 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
445 0x16);
446 stv0900_write_bits(i_params,
447 F0900_P1_TSFIFO_MANSPEED, 3);
448 stv0900_write_bits(i_params,
449 F0900_P2_TSFIFO_MANSPEED, 0);
450 stv0900_write_reg(i_params, R0900_P1_TSSPEED,
451 0x14);
452 stv0900_write_reg(i_params, R0900_P2_TSSPEED,
453 0x28);
454 break;
455 }
456
457 break;
458 case STV0900_SERIAL_PUNCT_CLOCK:
459 case STV0900_SERIAL_CONT_CLOCK:
460 default:
461 switch (path2_ts) {
462 case STV0900_SERIAL_PUNCT_CLOCK:
463 case STV0900_SERIAL_CONT_CLOCK:
464 default:
465 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
466 0x14);
467 break;
468 case STV0900_PARALLEL_PUNCT_CLOCK:
469 case STV0900_DVBCI_CLOCK:
470 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
471 0x12);
472 dprintk(KERN_INFO "%s: 0x12\n", __func__);
473 break;
474 }
475
476 break;
477 }
478 }
479
480 switch (path1_ts) {
481 case STV0900_PARALLEL_PUNCT_CLOCK:
482 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
483 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
484 break;
485 case STV0900_DVBCI_CLOCK:
486 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
487 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
488 break;
489 case STV0900_SERIAL_PUNCT_CLOCK:
490 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
491 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
492 break;
493 case STV0900_SERIAL_CONT_CLOCK:
494 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
495 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
496 break;
497 default:
498 break;
499 }
500
501 switch (path2_ts) {
502 case STV0900_PARALLEL_PUNCT_CLOCK:
503 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
504 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
505 break;
506 case STV0900_DVBCI_CLOCK:
507 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
508 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
509 break;
510 case STV0900_SERIAL_PUNCT_CLOCK:
511 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
512 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
513 break;
514 case STV0900_SERIAL_CONT_CLOCK:
515 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
516 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
517 break;
518 default:
519 break;
520 }
521
522 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
523 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0);
524 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
525 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0);
526 }
527
528 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
529 u32 bandwidth)
530 {
531 struct dvb_frontend_ops *frontend_ops = NULL;
532 struct dvb_tuner_ops *tuner_ops = NULL;
533
534 if (&fe->ops)
535 frontend_ops = &fe->ops;
536
537 if (&frontend_ops->tuner_ops)
538 tuner_ops = &frontend_ops->tuner_ops;
539
540 if (tuner_ops->set_frequency) {
541 if ((tuner_ops->set_frequency(fe, frequency)) < 0)
542 dprintk("%s: Invalid parameter\n", __func__);
543 else
544 dprintk("%s: Frequency=%d\n", __func__, frequency);
545
546 }
547
548 if (tuner_ops->set_bandwidth) {
549 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
550 dprintk("%s: Invalid parameter\n", __func__);
551 else
552 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
553
554 }
555 }
556
557 void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
558 {
559 struct dvb_frontend_ops *frontend_ops = NULL;
560 struct dvb_tuner_ops *tuner_ops = NULL;
561
562 if (&fe->ops)
563 frontend_ops = &fe->ops;
564
565 if (&frontend_ops->tuner_ops)
566 tuner_ops = &frontend_ops->tuner_ops;
567
568 if (tuner_ops->set_bandwidth) {
569 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
570 dprintk("%s: Invalid parameter\n", __func__);
571 else
572 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
573
574 }
575 }
576
577 static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
578 const struct stv0900_table *lookup,
579 enum fe_stv0900_demod_num demod)
580 {
581 s32 agc_gain = 0,
582 imin,
583 imax,
584 i,
585 rf_lvl = 0;
586
587 dprintk(KERN_INFO "%s\n", __func__);
588
589 if ((lookup != NULL) && lookup->size) {
590 switch (demod) {
591 case STV0900_DEMOD_1:
592 default:
593 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
594 stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
595 break;
596 case STV0900_DEMOD_2:
597 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
598 stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
599 break;
600 }
601
602 imin = 0;
603 imax = lookup->size - 1;
604 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
605 while ((imax - imin) > 1) {
606 i = (imax + imin) >> 1;
607
608 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval))
609 imax = i;
610 else
611 imin = i;
612 }
613
614 rf_lvl = (((s32)agc_gain - lookup->table[imin].regval)
615 * (lookup->table[imax].realval - lookup->table[imin].realval)
616 / (lookup->table[imax].regval - lookup->table[imin].regval))
617 + lookup->table[imin].realval;
618 } else if (agc_gain > lookup->table[0].regval)
619 rf_lvl = 5;
620 else if (agc_gain < lookup->table[lookup->size-1].regval)
621 rf_lvl = -100;
622
623 }
624
625 dprintk(KERN_INFO "%s: RFLevel = %d\n", __func__, rf_lvl);
626
627 return rf_lvl;
628 }
629
630 static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
631 {
632 struct stv0900_state *state = fe->demodulator_priv;
633 struct stv0900_internal *internal = state->internal;
634 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
635 state->demod);
636
637 *strength = (rflevel + 100) * (16383 / 105);
638
639 return 0;
640 }
641
642
643 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
644 const struct stv0900_table *lookup)
645 {
646 struct stv0900_state *state = fe->demodulator_priv;
647 struct stv0900_internal *i_params = state->internal;
648 enum fe_stv0900_demod_num demod = state->demod;
649
650 s32 c_n = -100,
651 regval, imin, imax,
652 i,
653 lock_flag_field,
654 noise_field1,
655 noise_field0;
656
657 dprintk(KERN_INFO "%s\n", __func__);
658
659 dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
660 F0900_P2_LOCK_DEFINITIF);
661 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
662 dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1,
663 F0900_P2_NOSPLHT_NORMED1);
664 dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
665 F0900_P2_NOSPLHT_NORMED0);
666 } else {
667 dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1,
668 F0900_P2_NOSDATAT_NORMED1);
669 dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
670 F0900_P2_NOSDATAT_NORMED0);
671 }
672
673 if (stv0900_get_bits(i_params, lock_flag_field)) {
674 if ((lookup != NULL) && lookup->size) {
675 regval = 0;
676 msleep(5);
677 for (i = 0; i < 16; i++) {
678 regval += MAKEWORD(stv0900_get_bits(i_params,
679 noise_field1),
680 stv0900_get_bits(i_params,
681 noise_field0));
682 msleep(1);
683 }
684
685 regval /= 16;
686 imin = 0;
687 imax = lookup->size - 1;
688 if (INRANGE(lookup->table[imin].regval,
689 regval,
690 lookup->table[imax].regval)) {
691 while ((imax - imin) > 1) {
692 i = (imax + imin) >> 1;
693 if (INRANGE(lookup->table[imin].regval,
694 regval,
695 lookup->table[i].regval))
696 imax = i;
697 else
698 imin = i;
699 }
700
701 c_n = ((regval - lookup->table[imin].regval)
702 * (lookup->table[imax].realval
703 - lookup->table[imin].realval)
704 / (lookup->table[imax].regval
705 - lookup->table[imin].regval))
706 + lookup->table[imin].realval;
707 } else if (regval < lookup->table[imin].regval)
708 c_n = 1000;
709 }
710 }
711
712 return c_n;
713 }
714
715 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
716 {
717 *snr = stv0900_carr_get_quality(fe,
718 (const struct stv0900_table *)&stv0900_s2_cn);
719 *snr += 30;
720 *snr *= (16383 / 1030);
721
722 return 0;
723 }
724
725 static u32 stv0900_get_ber(struct stv0900_internal *i_params,
726 enum fe_stv0900_demod_num demod)
727 {
728 u32 ber = 10000000, i;
729 s32 dmd_state_reg;
730 s32 demod_state;
731 s32 vstatus_reg;
732 s32 prvit_field;
733 s32 pdel_status_reg;
734 s32 pdel_lock_field;
735
736 dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
737 dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
738 dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
739 dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
740 dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
741 F0900_P2_PKTDELIN_LOCK);
742
743 demod_state = stv0900_get_bits(i_params, dmd_state_reg);
744
745 switch (demod_state) {
746 case STV0900_SEARCH:
747 case STV0900_PLH_DETECTED:
748 default:
749 ber = 10000000;
750 break;
751 case STV0900_DVBS_FOUND:
752 ber = 0;
753 for (i = 0; i < 5; i++) {
754 msleep(5);
755 ber += stv0900_get_err_count(i_params, 0, demod);
756 }
757
758 ber /= 5;
759 if (stv0900_get_bits(i_params, prvit_field)) {
760 ber *= 9766;
761 ber = ber >> 13;
762 }
763
764 break;
765 case STV0900_DVBS2_FOUND:
766 ber = 0;
767 for (i = 0; i < 5; i++) {
768 msleep(5);
769 ber += stv0900_get_err_count(i_params, 0, demod);
770 }
771
772 ber /= 5;
773 if (stv0900_get_bits(i_params, pdel_lock_field)) {
774 ber *= 9766;
775 ber = ber >> 13;
776 }
777
778 break;
779 }
780
781 return ber;
782 }
783
784 static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
785 {
786 struct stv0900_state *state = fe->demodulator_priv;
787 struct stv0900_internal *internal = state->internal;
788
789 *ber = stv0900_get_ber(internal, state->demod);
790
791 return 0;
792 }
793
794 int stv0900_get_demod_lock(struct stv0900_internal *i_params,
795 enum fe_stv0900_demod_num demod, s32 time_out)
796 {
797 s32 timer = 0,
798 lock = 0,
799 header_field,
800 lock_field;
801
802 enum fe_stv0900_search_state dmd_state;
803
804 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
805 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
806 while ((timer < time_out) && (lock == 0)) {
807 dmd_state = stv0900_get_bits(i_params, header_field);
808 dprintk("Demod State = %d\n", dmd_state);
809 switch (dmd_state) {
810 case STV0900_SEARCH:
811 case STV0900_PLH_DETECTED:
812 default:
813 lock = 0;
814 break;
815 case STV0900_DVBS2_FOUND:
816 case STV0900_DVBS_FOUND:
817 lock = stv0900_get_bits(i_params, lock_field);
818 break;
819 }
820
821 if (lock == 0)
822 msleep(10);
823
824 timer += 10;
825 }
826
827 if (lock)
828 dprintk("DEMOD LOCK OK\n");
829 else
830 dprintk("DEMOD LOCK FAIL\n");
831
832 return lock;
833 }
834
835 void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
836 enum fe_stv0900_demod_num demod)
837 {
838 s32 regflist,
839 i;
840
841 dprintk(KERN_INFO "%s\n", __func__);
842
843 dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0);
844
845 for (i = 0; i < 16; i++)
846 stv0900_write_reg(i_params, regflist + i, 0xff);
847 }
848
849 void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
850 enum fe_stv0900_demod_num demod)
851 {
852 u32 matype,
853 mod_code,
854 fmod,
855 reg_index,
856 field_index;
857
858 dprintk(KERN_INFO "%s\n", __func__);
859
860 if (i_params->chip_id <= 0x11) {
861 msleep(5);
862
863 switch (demod) {
864 case STV0900_DEMOD_1:
865 default:
866 mod_code = stv0900_read_reg(i_params,
867 R0900_P1_PLHMODCOD);
868 matype = mod_code & 0x3;
869 mod_code = (mod_code & 0x7f) >> 2;
870
871 reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
872 field_index = mod_code % 2;
873 break;
874 case STV0900_DEMOD_2:
875 mod_code = stv0900_read_reg(i_params,
876 R0900_P2_PLHMODCOD);
877 matype = mod_code & 0x3;
878 mod_code = (mod_code & 0x7f) >> 2;
879
880 reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
881 field_index = mod_code % 2;
882 break;
883 }
884
885
886 switch (matype) {
887 case 0:
888 default:
889 fmod = 14;
890 break;
891 case 1:
892 fmod = 13;
893 break;
894 case 2:
895 fmod = 11;
896 break;
897 case 3:
898 fmod = 7;
899 break;
900 }
901
902 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
903 && (matype <= 1)) {
904 if (field_index == 0)
905 stv0900_write_reg(i_params, reg_index,
906 0xf0 | fmod);
907 else
908 stv0900_write_reg(i_params, reg_index,
909 (fmod << 4) | 0xf);
910 }
911 } else if (i_params->chip_id >= 0x12) {
912 switch (demod) {
913 case STV0900_DEMOD_1:
914 default:
915 for (reg_index = 0; reg_index < 7; reg_index++)
916 stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
917
918 stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
919 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
920 for (reg_index = 0; reg_index < 8; reg_index++)
921 stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
922
923 break;
924 case STV0900_DEMOD_2:
925 for (reg_index = 0; reg_index < 7; reg_index++)
926 stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
927
928 stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
929 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
930 for (reg_index = 0; reg_index < 8; reg_index++)
931 stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
932
933 break;
934 }
935
936 }
937 }
938
939 void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
940 enum fe_stv0900_demod_num demod)
941 {
942 u32 reg_index;
943
944 dprintk(KERN_INFO "%s\n", __func__);
945
946 switch (demod) {
947 case STV0900_DEMOD_1:
948 default:
949 stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
950 stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
951 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
952 for (reg_index = 0; reg_index < 13; reg_index++)
953 stv0900_write_reg(i_params,
954 R0900_P1_MODCODLST2 + reg_index, 0);
955
956 break;
957 case STV0900_DEMOD_2:
958 stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
959 stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
960 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
961 for (reg_index = 0; reg_index < 13; reg_index++)
962 stv0900_write_reg(i_params,
963 R0900_P2_MODCODLST2 + reg_index, 0);
964
965 break;
966 }
967 }
968
969 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
970 {
971 return DVBFE_ALGO_CUSTOM;
972 }
973
974 static int stb0900_set_property(struct dvb_frontend *fe,
975 struct dtv_property *tvp)
976 {
977 dprintk(KERN_INFO "%s(..)\n", __func__);
978
979 return 0;
980 }
981
982 static int stb0900_get_property(struct dvb_frontend *fe,
983 struct dtv_property *tvp)
984 {
985 dprintk(KERN_INFO "%s(..)\n", __func__);
986
987 return 0;
988 }
989
990 void stv0900_start_search(struct stv0900_internal *i_params,
991 enum fe_stv0900_demod_num demod)
992 {
993
994 switch (demod) {
995 case STV0900_DEMOD_1:
996 default:
997 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f);
998
999 if (i_params->chip_id == 0x10)
1000 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa);
1001
1002 if (i_params->chip_id < 0x20)
1003 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
1004
1005 if (i_params->dmd1_symbol_rate <= 5000000) {
1006 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44);
1007 stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f);
1008 stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff);
1009 stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0);
1010 stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00);
1011 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
1012 } else {
1013 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4);
1014 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
1015 }
1016
1017 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
1018 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
1019
1020 if (i_params->chip_id >= 0x20) {
1021 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
1022 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
1023
1024 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1025 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
1026 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
1027 }
1028 }
1029
1030 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
1031 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
1032 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
1033 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
1034 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1035 stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
1036 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
1037 if (i_params->chip_id >= 0x20) {
1038 if (i_params->dmd1_symbol_rate < 2000000) {
1039 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
1040 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
1041 }
1042
1043 if (i_params->dmd1_symbol_rate < 10000000) {
1044 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
1045 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1046 } else {
1047 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
1048 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1049 }
1050
1051 } else {
1052 if (i_params->dmd1_symbol_rate < 10000000)
1053 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef);
1054 else
1055 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
1056 }
1057
1058 switch (i_params->dmd1_srch_algo) {
1059 case STV0900_WARM_START:
1060 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1061 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1062 break;
1063 case STV0900_COLD_START:
1064 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1065 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
1066 break;
1067 default:
1068 break;
1069 }
1070
1071 break;
1072 case STV0900_DEMOD_2:
1073 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
1074 if (i_params->chip_id == 0x10)
1075 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
1076
1077 if (i_params->chip_id < 0x20)
1078 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
1079
1080 if (i_params->dmd2_symbol_rate <= 5000000) {
1081 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
1082 stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
1083 stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
1084 stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
1085 stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
1086 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
1087 } else {
1088 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
1089 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
1090 }
1091
1092 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
1093 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
1094
1095 if (i_params->chip_id >= 0x20) {
1096 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
1097 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
1098 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1099 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
1100 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
1101 }
1102 }
1103
1104 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
1105 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0);
1106 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0);
1107 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1108 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1109 stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
1110 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
1111 if (i_params->chip_id >= 0x20) {
1112 if (i_params->dmd2_symbol_rate < 2000000) {
1113 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
1114 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
1115 }
1116
1117 if (i_params->dmd2_symbol_rate < 10000000) {
1118 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c);
1119 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1120 } else {
1121 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b);
1122 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1123 }
1124
1125 } else {
1126 if (i_params->dmd2_symbol_rate < 10000000)
1127 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef);
1128 else
1129 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
1130 }
1131
1132 switch (i_params->dmd2_srch_algo) {
1133 case STV0900_WARM_START:
1134 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1135 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1136 break;
1137 case STV0900_COLD_START:
1138 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1139 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
1140 break;
1141 default:
1142 break;
1143 }
1144
1145 break;
1146 }
1147 }
1148
1149 u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1150 s32 pilot, u8 chip_id)
1151 {
1152 u8 aclc_value = 0x29;
1153 s32 i;
1154 const struct stv0900_car_loop_optim *car_loop_s2;
1155
1156 dprintk(KERN_INFO "%s\n", __func__);
1157
1158 if (chip_id <= 0x12)
1159 car_loop_s2 = FE_STV0900_S2CarLoop;
1160 else if (chip_id == 0x20)
1161 car_loop_s2 = FE_STV0900_S2CarLoopCut20;
1162 else
1163 car_loop_s2 = FE_STV0900_S2CarLoop;
1164
1165 if (modcode < STV0900_QPSK_12) {
1166 i = 0;
1167 while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode))
1168 i++;
1169
1170 if (i >= 3)
1171 i = 2;
1172 } else {
1173 i = 0;
1174 while ((i < 14) && (modcode != car_loop_s2[i].modcode))
1175 i++;
1176
1177 if (i >= 14) {
1178 i = 0;
1179 while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode))
1180 i++;
1181
1182 if (i >= 11)
1183 i = 10;
1184 }
1185 }
1186
1187 if (modcode <= STV0900_QPSK_25) {
1188 if (pilot) {
1189 if (srate <= 3000000)
1190 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2;
1191 else if (srate <= 7000000)
1192 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5;
1193 else if (srate <= 15000000)
1194 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10;
1195 else if (srate <= 25000000)
1196 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20;
1197 else
1198 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30;
1199 } else {
1200 if (srate <= 3000000)
1201 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2;
1202 else if (srate <= 7000000)
1203 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5;
1204 else if (srate <= 15000000)
1205 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10;
1206 else if (srate <= 25000000)
1207 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20;
1208 else
1209 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30;
1210 }
1211
1212 } else if (modcode <= STV0900_8PSK_910) {
1213 if (pilot) {
1214 if (srate <= 3000000)
1215 aclc_value = car_loop_s2[i].car_loop_pilots_on_2;
1216 else if (srate <= 7000000)
1217 aclc_value = car_loop_s2[i].car_loop_pilots_on_5;
1218 else if (srate <= 15000000)
1219 aclc_value = car_loop_s2[i].car_loop_pilots_on_10;
1220 else if (srate <= 25000000)
1221 aclc_value = car_loop_s2[i].car_loop_pilots_on_20;
1222 else
1223 aclc_value = car_loop_s2[i].car_loop_pilots_on_30;
1224 } else {
1225 if (srate <= 3000000)
1226 aclc_value = car_loop_s2[i].car_loop_pilots_off_2;
1227 else if (srate <= 7000000)
1228 aclc_value = car_loop_s2[i].car_loop_pilots_off_5;
1229 else if (srate <= 15000000)
1230 aclc_value = car_loop_s2[i].car_loop_pilots_off_10;
1231 else if (srate <= 25000000)
1232 aclc_value = car_loop_s2[i].car_loop_pilots_off_20;
1233 else
1234 aclc_value = car_loop_s2[i].car_loop_pilots_off_30;
1235 }
1236
1237 } else {
1238 if (srate <= 3000000)
1239 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2;
1240 else if (srate <= 7000000)
1241 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5;
1242 else if (srate <= 15000000)
1243 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10;
1244 else if (srate <= 25000000)
1245 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20;
1246 else
1247 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30;
1248 }
1249
1250 return aclc_value;
1251 }
1252
1253 u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id)
1254 {
1255 s32 mod_index = 0;
1256
1257 u8 aclc_value = 0x0b;
1258
1259 dprintk(KERN_INFO "%s\n", __func__);
1260
1261 switch (modulation) {
1262 case STV0900_QPSK:
1263 default:
1264 mod_index = 0;
1265 break;
1266 case STV0900_8PSK:
1267 mod_index = 1;
1268 break;
1269 case STV0900_16APSK:
1270 mod_index = 2;
1271 break;
1272 case STV0900_32APSK:
1273 mod_index = 3;
1274 break;
1275 }
1276
1277 switch (chip_id) {
1278 case 0x20:
1279 if (srate <= 3000000)
1280 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2;
1281 else if (srate <= 7000000)
1282 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5;
1283 else if (srate <= 15000000)
1284 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10;
1285 else if (srate <= 25000000)
1286 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20;
1287 else
1288 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30;
1289
1290 break;
1291 case 0x12:
1292 default:
1293 if (srate <= 3000000)
1294 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2;
1295 else if (srate <= 7000000)
1296 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5;
1297 else if (srate <= 15000000)
1298 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10;
1299 else if (srate <= 25000000)
1300 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20;
1301 else
1302 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30;
1303
1304 break;
1305 }
1306
1307 return aclc_value;
1308 }
1309
1310 static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params,
1311 enum fe_stv0900_demod_mode LDPC_Mode,
1312 enum fe_stv0900_demod_num demod)
1313 {
1314 enum fe_stv0900_error error = STV0900_NO_ERROR;
1315
1316 dprintk(KERN_INFO "%s\n", __func__);
1317
1318 switch (LDPC_Mode) {
1319 case STV0900_DUAL:
1320 default:
1321 if ((i_params->demod_mode != STV0900_DUAL)
1322 || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) {
1323 stv0900_write_reg(i_params, R0900_GENCFG, 0x1d);
1324
1325 i_params->demod_mode = STV0900_DUAL;
1326
1327 stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1328 stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1329 }
1330
1331 break;
1332 case STV0900_SINGLE:
1333 if (demod == STV0900_DEMOD_2)
1334 stv0900_write_reg(i_params, R0900_GENCFG, 0x06);
1335 else
1336 stv0900_write_reg(i_params, R0900_GENCFG, 0x04);
1337
1338 i_params->demod_mode = STV0900_SINGLE;
1339
1340 stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1341 stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1342 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
1343 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
1344 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
1345 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
1346 break;
1347 }
1348
1349 return error;
1350 }
1351
1352 static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1353 struct stv0900_init_params *p_init)
1354 {
1355 struct stv0900_state *state = fe->demodulator_priv;
1356 enum fe_stv0900_error error = STV0900_NO_ERROR;
1357 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1358 int selosci;
1359
1360 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1361 state->config->demod_address);
1362
1363 dprintk(KERN_INFO "%s\n", __func__);
1364
1365 if (temp_int != NULL) {
1366 state->internal = temp_int->internal;
1367 (state->internal->dmds_used)++;
1368 dprintk(KERN_INFO "%s: Find Internal Structure!\n", __func__);
1369 return STV0900_NO_ERROR;
1370 } else {
1371 state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL);
1372 temp_int = append_internal(state->internal);
1373 state->internal->dmds_used = 1;
1374 state->internal->i2c_adap = state->i2c_adap;
1375 state->internal->i2c_addr = state->config->demod_address;
1376 state->internal->clkmode = state->config->clkmode;
1377 state->internal->errs = STV0900_NO_ERROR;
1378 dprintk(KERN_INFO "%s: Create New Internal Structure!\n", __func__);
1379 }
1380
1381 if (state->internal != NULL) {
1382 demodError = stv0900_initialize(state->internal);
1383 if (demodError == STV0900_NO_ERROR) {
1384 error = STV0900_NO_ERROR;
1385 } else {
1386 if (demodError == STV0900_INVALID_HANDLE)
1387 error = STV0900_INVALID_HANDLE;
1388 else
1389 error = STV0900_I2C_ERROR;
1390 }
1391
1392 if (state->internal != NULL) {
1393 if (error == STV0900_NO_ERROR) {
1394 state->internal->demod_mode = p_init->demod_mode;
1395
1396 stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1);
1397
1398 state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID);
1399 state->internal->rolloff = p_init->rolloff;
1400 state->internal->quartz = p_init->dmd_ref_clk;
1401
1402 stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1403 stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1404
1405 stv0900_set_ts_parallel_serial(state->internal, p_init->path1_ts_clock, p_init->path2_ts_clock);
1406 stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1407 switch (p_init->tuner1_adc) {
1408 case 1:
1409 stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
1410 break;
1411 default:
1412 break;
1413 }
1414
1415 stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1416 switch (p_init->tuner2_adc) {
1417 case 1:
1418 stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26);
1419 break;
1420 default:
1421 break;
1422 }
1423
1424 stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion);
1425 stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
1426 stv0900_set_mclk(state->internal, 135000000);
1427 msleep(3);
1428
1429 switch (state->internal->clkmode) {
1430 case 0:
1431 case 2:
1432 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
1433 break;
1434 default:
1435 selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
1436 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
1437 break;
1438 }
1439 msleep(3);
1440
1441 state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz);
1442 if (state->internal->errs)
1443 error = STV0900_I2C_ERROR;
1444 }
1445 } else {
1446 error = STV0900_INVALID_HANDLE;
1447 }
1448 }
1449
1450 return error;
1451 }
1452
1453 static int stv0900_status(struct stv0900_internal *i_params,
1454 enum fe_stv0900_demod_num demod)
1455 {
1456 enum fe_stv0900_search_state demod_state;
1457 s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
1458 int locked = FALSE;
1459
1460 dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1461 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
1462 dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1463 dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1464 dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1465
1466 demod_state = stv0900_get_bits(i_params, mode_field);
1467 switch (demod_state) {
1468 case STV0900_SEARCH:
1469 case STV0900_PLH_DETECTED:
1470 default:
1471 locked = FALSE;
1472 break;
1473 case STV0900_DVBS2_FOUND:
1474 locked = stv0900_get_bits(i_params, lock_field) &&
1475 stv0900_get_bits(i_params, delin_field) &&
1476 stv0900_get_bits(i_params, fifo_field);
1477 break;
1478 case STV0900_DVBS_FOUND:
1479 locked = stv0900_get_bits(i_params, lock_field) &&
1480 stv0900_get_bits(i_params, lockedvit_field) &&
1481 stv0900_get_bits(i_params, fifo_field);
1482 break;
1483 }
1484
1485 return locked;
1486 }
1487
1488 static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1489 struct dvb_frontend_parameters *params)
1490 {
1491 struct stv0900_state *state = fe->demodulator_priv;
1492 struct stv0900_internal *i_params = state->internal;
1493 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1494
1495 struct stv0900_search_params p_search;
1496 struct stv0900_signal_info p_result;
1497
1498 enum fe_stv0900_error error = STV0900_NO_ERROR;
1499
1500 dprintk(KERN_INFO "%s: ", __func__);
1501
1502 p_result.locked = FALSE;
1503 p_search.path = state->demod;
1504 p_search.frequency = c->frequency;
1505 p_search.symbol_rate = c->symbol_rate;
1506 p_search.search_range = 10000000;
1507 p_search.fec = STV0900_FEC_UNKNOWN;
1508 p_search.standard = STV0900_AUTO_SEARCH;
1509 p_search.iq_inversion = STV0900_IQ_AUTO;
1510 p_search.search_algo = STV0900_BLIND_SEARCH;
1511
1512 if ((INRANGE(100000, p_search.symbol_rate, 70000000)) &&
1513 (INRANGE(100000, p_search.search_range, 50000000))) {
1514 switch (p_search.path) {
1515 case STV0900_DEMOD_1:
1516 default:
1517 i_params->dmd1_srch_standard = p_search.standard;
1518 i_params->dmd1_symbol_rate = p_search.symbol_rate;
1519 i_params->dmd1_srch_range = p_search.search_range;
1520 i_params->tuner1_freq = p_search.frequency;
1521 i_params->dmd1_srch_algo = p_search.search_algo;
1522 i_params->dmd1_srch_iq_inv = p_search.iq_inversion;
1523 i_params->dmd1_fec = p_search.fec;
1524 break;
1525
1526 case STV0900_DEMOD_2:
1527 i_params->dmd2_srch_stndrd = p_search.standard;
1528 i_params->dmd2_symbol_rate = p_search.symbol_rate;
1529 i_params->dmd2_srch_range = p_search.search_range;
1530 i_params->tuner2_freq = p_search.frequency;
1531 i_params->dmd2_srch_algo = p_search.search_algo;
1532 i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
1533 i_params->dmd2_fec = p_search.fec;
1534 break;
1535 }
1536
1537 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1538 (i_params->errs == STV0900_NO_ERROR)) {
1539 switch (p_search.path) {
1540 case STV0900_DEMOD_1:
1541 default:
1542 p_result.locked = i_params->dmd1_rslts.locked;
1543 p_result.standard = i_params->dmd1_rslts.standard;
1544 p_result.frequency = i_params->dmd1_rslts.frequency;
1545 p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
1546 p_result.fec = i_params->dmd1_rslts.fec;
1547 p_result.modcode = i_params->dmd1_rslts.modcode;
1548 p_result.pilot = i_params->dmd1_rslts.pilot;
1549 p_result.frame_length = i_params->dmd1_rslts.frame_length;
1550 p_result.spectrum = i_params->dmd1_rslts.spectrum;
1551 p_result.rolloff = i_params->dmd1_rslts.rolloff;
1552 p_result.modulation = i_params->dmd1_rslts.modulation;
1553 break;
1554 case STV0900_DEMOD_2:
1555 p_result.locked = i_params->dmd2_rslts.locked;
1556 p_result.standard = i_params->dmd2_rslts.standard;
1557 p_result.frequency = i_params->dmd2_rslts.frequency;
1558 p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
1559 p_result.fec = i_params->dmd2_rslts.fec;
1560 p_result.modcode = i_params->dmd2_rslts.modcode;
1561 p_result.pilot = i_params->dmd2_rslts.pilot;
1562 p_result.frame_length = i_params->dmd2_rslts.frame_length;
1563 p_result.spectrum = i_params->dmd2_rslts.spectrum;
1564 p_result.rolloff = i_params->dmd2_rslts.rolloff;
1565 p_result.modulation = i_params->dmd2_rslts.modulation;
1566 break;
1567 }
1568
1569 } else {
1570 p_result.locked = FALSE;
1571 switch (p_search.path) {
1572 case STV0900_DEMOD_1:
1573 switch (i_params->dmd1_err) {
1574 case STV0900_I2C_ERROR:
1575 error = STV0900_I2C_ERROR;
1576 break;
1577 case STV0900_NO_ERROR:
1578 default:
1579 error = STV0900_SEARCH_FAILED;
1580 break;
1581 }
1582 break;
1583 case STV0900_DEMOD_2:
1584 switch (i_params->dmd2_err) {
1585 case STV0900_I2C_ERROR:
1586 error = STV0900_I2C_ERROR;
1587 break;
1588 case STV0900_NO_ERROR:
1589 default:
1590 error = STV0900_SEARCH_FAILED;
1591 break;
1592 }
1593 break;
1594 }
1595 }
1596
1597 } else
1598 error = STV0900_BAD_PARAMETER;
1599
1600 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1601 dprintk(KERN_INFO "Search Success\n");
1602 return DVBFE_ALGO_SEARCH_SUCCESS;
1603 } else {
1604 dprintk(KERN_INFO "Search Fail\n");
1605 return DVBFE_ALGO_SEARCH_FAILED;
1606 }
1607
1608 return DVBFE_ALGO_SEARCH_ERROR;
1609 }
1610
1611 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1612 {
1613 struct stv0900_state *state = fe->demodulator_priv;
1614
1615 dprintk("%s: ", __func__);
1616
1617 if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1618 dprintk("DEMOD LOCK OK\n");
1619 *status = FE_HAS_CARRIER
1620 | FE_HAS_VITERBI
1621 | FE_HAS_SYNC
1622 | FE_HAS_LOCK;
1623 } else
1624 dprintk("DEMOD LOCK FAIL\n");
1625
1626 return 0;
1627 }
1628
1629 static int stv0900_track(struct dvb_frontend *fe,
1630 struct dvb_frontend_parameters *p)
1631 {
1632 return 0;
1633 }
1634
1635 static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1636 {
1637
1638 struct stv0900_state *state = fe->demodulator_priv;
1639 struct stv0900_internal *i_params = state->internal;
1640 enum fe_stv0900_demod_num demod = state->demod;
1641 s32 rst_field;
1642
1643 dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1644
1645 if (stop_ts == TRUE)
1646 stv0900_write_bits(i_params, rst_field, 1);
1647 else
1648 stv0900_write_bits(i_params, rst_field, 0);
1649
1650 return 0;
1651 }
1652
1653 static int stv0900_diseqc_init(struct dvb_frontend *fe)
1654 {
1655 struct stv0900_state *state = fe->demodulator_priv;
1656 struct stv0900_internal *i_params = state->internal;
1657 enum fe_stv0900_demod_num demod = state->demod;
1658 s32 mode_field, reset_field;
1659
1660 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1661 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1662
1663 stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
1664 stv0900_write_bits(i_params, reset_field, 1);
1665 stv0900_write_bits(i_params, reset_field, 0);
1666
1667 return 0;
1668 }
1669
1670 static int stv0900_init(struct dvb_frontend *fe)
1671 {
1672 dprintk(KERN_INFO "%s\n", __func__);
1673
1674 stv0900_stop_ts(fe, 1);
1675 stv0900_diseqc_init(fe);
1676
1677 return 0;
1678 }
1679
1680 static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data,
1681 u32 NbData, enum fe_stv0900_demod_num demod)
1682 {
1683 s32 i = 0;
1684
1685 switch (demod) {
1686 case STV0900_DEMOD_1:
1687 default:
1688 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1);
1689 while (i < NbData) {
1690 while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL))
1691 ;/* checkpatch complains */
1692 stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
1693 i++;
1694 }
1695
1696 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
1697 i = 0;
1698 while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
1699 msleep(10);
1700 i++;
1701 }
1702
1703 break;
1704 case STV0900_DEMOD_2:
1705 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
1706
1707 while (i < NbData) {
1708 while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
1709 ;/* checkpatch complains */
1710 stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
1711 i++;
1712 }
1713
1714 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
1715 i = 0;
1716 while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
1717 msleep(10);
1718 i++;
1719 }
1720
1721 break;
1722 }
1723
1724 return 0;
1725 }
1726
1727 static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1728 struct dvb_diseqc_master_cmd *cmd)
1729 {
1730 struct stv0900_state *state = fe->demodulator_priv;
1731
1732 return stv0900_diseqc_send(state->internal,
1733 cmd->msg,
1734 cmd->msg_len,
1735 state->demod);
1736 }
1737
1738 static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1739 {
1740 struct stv0900_state *state = fe->demodulator_priv;
1741 struct stv0900_internal *i_params = state->internal;
1742 enum fe_stv0900_demod_num demod = state->demod;
1743 s32 mode_field;
1744 u32 diseqc_fifo;
1745
1746 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1747 dmd_reg(diseqc_fifo, R0900_P1_DISTXDATA, R0900_P2_DISTXDATA);
1748
1749 switch (burst) {
1750 case SEC_MINI_A:
1751 stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */
1752 stv0900_write_reg(i_params, diseqc_fifo, 0x00);
1753 break;
1754 case SEC_MINI_B:
1755 stv0900_write_bits(i_params, mode_field, 2);/* Modulated */
1756 stv0900_write_reg(i_params, diseqc_fifo, 0xff);
1757 break;
1758 }
1759
1760 return 0;
1761 }
1762
1763 static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1764 struct dvb_diseqc_slave_reply *reply)
1765 {
1766 struct stv0900_state *state = fe->demodulator_priv;
1767 struct stv0900_internal *i_params = state->internal;
1768 s32 i = 0;
1769
1770 switch (state->demod) {
1771 case STV0900_DEMOD_1:
1772 default:
1773 reply->msg_len = 0;
1774
1775 while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
1776 msleep(10);
1777 i++;
1778 }
1779
1780 if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
1781 reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
1782
1783 for (i = 0; i < reply->msg_len; i++)
1784 reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
1785 }
1786 break;
1787 case STV0900_DEMOD_2:
1788 reply->msg_len = 0;
1789
1790 while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
1791 msleep(10);
1792 i++;
1793 }
1794
1795 if (stv0900_get_bits(i_params, F0900_P2_RX_END)) {
1796 reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR);
1797
1798 for (i = 0; i < reply->msg_len; i++)
1799 reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA);
1800 }
1801 break;
1802 }
1803
1804 return 0;
1805 }
1806
1807 static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1808 {
1809 struct stv0900_state *state = fe->demodulator_priv;
1810 struct stv0900_internal *i_params = state->internal;
1811 enum fe_stv0900_demod_num demod = state->demod;
1812 s32 mode_field, reset_field;
1813
1814 dprintk(KERN_INFO "%s: %s\n", __func__, ((tone == 0) ? "Off" : "On"));
1815
1816 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1817 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1818
1819 if (tone) {
1820 /*Set the DiseqC mode to 22Khz continues tone*/
1821 stv0900_write_bits(i_params, mode_field, 0);
1822 stv0900_write_bits(i_params, reset_field, 1);
1823 /*release DiseqC reset to enable the 22KHz tone*/
1824 stv0900_write_bits(i_params, reset_field, 0);
1825 } else {
1826 stv0900_write_bits(i_params, mode_field, 0);
1827 /*maintain the DiseqC reset to disable the 22KHz tone*/
1828 stv0900_write_bits(i_params, reset_field, 1);
1829 }
1830
1831 return 0;
1832 }
1833
1834 static void stv0900_release(struct dvb_frontend *fe)
1835 {
1836 struct stv0900_state *state = fe->demodulator_priv;
1837
1838 dprintk(KERN_INFO "%s\n", __func__);
1839
1840 if ((--(state->internal->dmds_used)) <= 0) {
1841
1842 dprintk(KERN_INFO "%s: Actually removing\n", __func__);
1843
1844 remove_inode(state->internal);
1845 kfree(state->internal);
1846 }
1847
1848 kfree(state);
1849 }
1850
1851 static struct dvb_frontend_ops stv0900_ops = {
1852
1853 .info = {
1854 .name = "STV0900 frontend",
1855 .type = FE_QPSK,
1856 .frequency_min = 950000,
1857 .frequency_max = 2150000,
1858 .frequency_stepsize = 125,
1859 .frequency_tolerance = 0,
1860 .symbol_rate_min = 1000000,
1861 .symbol_rate_max = 45000000,
1862 .symbol_rate_tolerance = 500,
1863 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1864 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1865 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1866 FE_CAN_2G_MODULATION |
1867 FE_CAN_FEC_AUTO
1868 },
1869 .release = stv0900_release,
1870 .init = stv0900_init,
1871 .get_frontend_algo = stv0900_frontend_algo,
1872 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
1873 .diseqc_send_master_cmd = stv0900_send_master_cmd,
1874 .diseqc_send_burst = stv0900_send_burst,
1875 .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
1876 .set_tone = stv0900_set_tone,
1877 .set_property = stb0900_set_property,
1878 .get_property = stb0900_get_property,
1879 .search = stv0900_search,
1880 .track = stv0900_track,
1881 .read_status = stv0900_read_status,
1882 .read_ber = stv0900_read_ber,
1883 .read_signal_strength = stv0900_read_signal_strength,
1884 .read_snr = stv0900_read_snr,
1885 };
1886
1887 struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1888 struct i2c_adapter *i2c,
1889 int demod)
1890 {
1891 struct stv0900_state *state = NULL;
1892 struct stv0900_init_params init_params;
1893 enum fe_stv0900_error err_stv0900;
1894
1895 state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
1896 if (state == NULL)
1897 goto error;
1898
1899 state->demod = demod;
1900 state->config = config;
1901 state->i2c_adap = i2c;
1902
1903 memcpy(&state->frontend.ops, &stv0900_ops,
1904 sizeof(struct dvb_frontend_ops));
1905 state->frontend.demodulator_priv = state;
1906
1907 switch (demod) {
1908 case 0:
1909 case 1:
1910 init_params.dmd_ref_clk = config->xtal;
1911 init_params.demod_mode = STV0900_DUAL;
1912 init_params.rolloff = STV0900_35;
1913 init_params.path1_ts_clock = config->path1_mode;
1914 init_params.tun1_maddress = config->tun1_maddress;
1915 init_params.tun1_iq_inversion = STV0900_IQ_NORMAL;
1916 init_params.tuner1_adc = config->tun1_adc;
1917 init_params.path2_ts_clock = config->path2_mode;
1918 init_params.tun2_maddress = config->tun2_maddress;
1919 init_params.tuner2_adc = config->tun2_adc;
1920 init_params.tun2_iq_inversion = STV0900_IQ_SWAPPED;
1921
1922 err_stv0900 = stv0900_init_internal(&state->frontend,
1923 &init_params);
1924
1925 if (err_stv0900)
1926 goto error;
1927
1928 break;
1929 default:
1930 goto error;
1931 break;
1932 }
1933
1934 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
1935 return &state->frontend;
1936
1937 error:
1938 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1939 __func__, demod);
1940 kfree(state);
1941 return NULL;
1942 }
1943 EXPORT_SYMBOL(stv0900_attach);
1944
1945 MODULE_PARM_DESC(debug, "Set debug");
1946
1947 MODULE_AUTHOR("Igor M. Liplianin");
1948 MODULE_DESCRIPTION("ST STV0900 frontend");
1949 MODULE_LICENSE("GPL");
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