2 * Afatech AF9033 demodulator driver
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "af9033_priv.h"
25 struct i2c_adapter
*i2c
;
26 struct dvb_frontend fe
;
27 struct af9033_config cfg
;
30 bool ts_mode_parallel
;
35 unsigned long last_stat_check
;
38 /* write multiple registers */
39 static int af9033_wr_regs(struct af9033_state
*state
, u32 reg
, const u8
*val
,
44 struct i2c_msg msg
[1] = {
46 .addr
= state
->cfg
.i2c_addr
,
53 buf
[0] = (reg
>> 16) & 0xff;
54 buf
[1] = (reg
>> 8) & 0xff;
55 buf
[2] = (reg
>> 0) & 0xff;
56 memcpy(&buf
[3], val
, len
);
58 ret
= i2c_transfer(state
->i2c
, msg
, 1);
62 dev_warn(&state
->i2c
->dev
, "%s: i2c wr failed=%d reg=%06x " \
63 "len=%d\n", KBUILD_MODNAME
, ret
, reg
, len
);
70 /* read multiple registers */
71 static int af9033_rd_regs(struct af9033_state
*state
, u32 reg
, u8
*val
, int len
)
74 u8 buf
[3] = { (reg
>> 16) & 0xff, (reg
>> 8) & 0xff,
76 struct i2c_msg msg
[2] = {
78 .addr
= state
->cfg
.i2c_addr
,
83 .addr
= state
->cfg
.i2c_addr
,
90 ret
= i2c_transfer(state
->i2c
, msg
, 2);
94 dev_warn(&state
->i2c
->dev
, "%s: i2c rd failed=%d reg=%06x " \
95 "len=%d\n", KBUILD_MODNAME
, ret
, reg
, len
);
103 /* write single register */
104 static int af9033_wr_reg(struct af9033_state
*state
, u32 reg
, u8 val
)
106 return af9033_wr_regs(state
, reg
, &val
, 1);
109 /* read single register */
110 static int af9033_rd_reg(struct af9033_state
*state
, u32 reg
, u8
*val
)
112 return af9033_rd_regs(state
, reg
, val
, 1);
115 /* write single register with mask */
116 static int af9033_wr_reg_mask(struct af9033_state
*state
, u32 reg
, u8 val
,
122 /* no need for read if whole reg is written */
124 ret
= af9033_rd_regs(state
, reg
, &tmp
, 1);
133 return af9033_wr_regs(state
, reg
, &val
, 1);
136 /* read single register with mask */
137 static int af9033_rd_reg_mask(struct af9033_state
*state
, u32 reg
, u8
*val
,
143 ret
= af9033_rd_regs(state
, reg
, &tmp
, 1);
149 /* find position of the first bit */
150 for (i
= 0; i
< 8; i
++) {
151 if ((mask
>> i
) & 0x01)
159 static u32
af9033_div(struct af9033_state
*state
, u32 a
, u32 b
, u32 x
)
163 dev_dbg(&state
->i2c
->dev
, "%s: a=%d b=%d x=%d\n", __func__
, a
, b
, x
);
170 for (i
= 0; i
< x
; i
++) {
178 r
= (c
<< (u32
)x
) + r
;
180 dev_dbg(&state
->i2c
->dev
, "%s: a=%d b=%d x=%d r=%d r=%x\n",
181 __func__
, a
, b
, x
, r
, r
);
186 static void af9033_release(struct dvb_frontend
*fe
)
188 struct af9033_state
*state
= fe
->demodulator_priv
;
193 static int af9033_init(struct dvb_frontend
*fe
)
195 struct af9033_state
*state
= fe
->demodulator_priv
;
197 const struct reg_val
*init
;
199 u32 adc_cw
, clock_cw
;
200 struct reg_val_mask tab
[] = {
201 { 0x80fb24, 0x00, 0x08 },
202 { 0x80004c, 0x00, 0xff },
203 { 0x00f641, state
->cfg
.tuner
, 0xff },
204 { 0x80f5ca, 0x01, 0x01 },
205 { 0x80f715, 0x01, 0x01 },
206 { 0x00f41f, 0x04, 0x04 },
207 { 0x00f41a, 0x01, 0x01 },
208 { 0x80f731, 0x00, 0x01 },
209 { 0x00d91e, 0x00, 0x01 },
210 { 0x00d919, 0x00, 0x01 },
211 { 0x80f732, 0x00, 0x01 },
212 { 0x00d91f, 0x00, 0x01 },
213 { 0x00d91a, 0x00, 0x01 },
214 { 0x80f730, 0x00, 0x01 },
215 { 0x80f778, 0x00, 0xff },
216 { 0x80f73c, 0x01, 0x01 },
217 { 0x80f776, 0x00, 0x01 },
218 { 0x00d8fd, 0x01, 0xff },
219 { 0x00d830, 0x01, 0xff },
220 { 0x00d831, 0x00, 0xff },
221 { 0x00d832, 0x00, 0xff },
222 { 0x80f985, state
->ts_mode_serial
, 0x01 },
223 { 0x80f986, state
->ts_mode_parallel
, 0x01 },
224 { 0x00d827, 0x00, 0xff },
225 { 0x00d829, 0x00, 0xff },
228 /* program clock control */
229 clock_cw
= af9033_div(state
, state
->cfg
.clock
, 1000000ul, 19ul);
230 buf
[0] = (clock_cw
>> 0) & 0xff;
231 buf
[1] = (clock_cw
>> 8) & 0xff;
232 buf
[2] = (clock_cw
>> 16) & 0xff;
233 buf
[3] = (clock_cw
>> 24) & 0xff;
235 dev_dbg(&state
->i2c
->dev
, "%s: clock=%d clock_cw=%08x\n",
236 __func__
, state
->cfg
.clock
, clock_cw
);
238 ret
= af9033_wr_regs(state
, 0x800025, buf
, 4);
242 /* program ADC control */
243 for (i
= 0; i
< ARRAY_SIZE(clock_adc_lut
); i
++) {
244 if (clock_adc_lut
[i
].clock
== state
->cfg
.clock
)
248 adc_cw
= af9033_div(state
, clock_adc_lut
[i
].adc
, 1000000ul, 19ul);
249 buf
[0] = (adc_cw
>> 0) & 0xff;
250 buf
[1] = (adc_cw
>> 8) & 0xff;
251 buf
[2] = (adc_cw
>> 16) & 0xff;
253 dev_dbg(&state
->i2c
->dev
, "%s: adc=%d adc_cw=%06x\n",
254 __func__
, clock_adc_lut
[i
].adc
, adc_cw
);
256 ret
= af9033_wr_regs(state
, 0x80f1cd, buf
, 3);
260 /* program register table */
261 for (i
= 0; i
< ARRAY_SIZE(tab
); i
++) {
262 ret
= af9033_wr_reg_mask(state
, tab
[i
].reg
, tab
[i
].val
,
268 /* settings for TS interface */
269 if (state
->cfg
.ts_mode
== AF9033_TS_MODE_USB
) {
270 ret
= af9033_wr_reg_mask(state
, 0x80f9a5, 0x00, 0x01);
274 ret
= af9033_wr_reg_mask(state
, 0x80f9b5, 0x01, 0x01);
278 ret
= af9033_wr_reg_mask(state
, 0x80f990, 0x00, 0x01);
282 ret
= af9033_wr_reg_mask(state
, 0x80f9b5, 0x00, 0x01);
287 /* load OFSM settings */
288 dev_dbg(&state
->i2c
->dev
, "%s: load ofsm settings\n", __func__
);
289 len
= ARRAY_SIZE(ofsm_init
);
291 for (i
= 0; i
< len
; i
++) {
292 ret
= af9033_wr_reg(state
, init
[i
].reg
, init
[i
].val
);
297 /* load tuner specific settings */
298 dev_dbg(&state
->i2c
->dev
, "%s: load tuner specific settings\n",
300 switch (state
->cfg
.tuner
) {
301 case AF9033_TUNER_TUA9001
:
302 len
= ARRAY_SIZE(tuner_init_tua9001
);
303 init
= tuner_init_tua9001
;
305 case AF9033_TUNER_FC0011
:
306 len
= ARRAY_SIZE(tuner_init_fc0011
);
307 init
= tuner_init_fc0011
;
309 case AF9033_TUNER_MXL5007T
:
310 len
= ARRAY_SIZE(tuner_init_mxl5007t
);
311 init
= tuner_init_mxl5007t
;
313 case AF9033_TUNER_TDA18218
:
314 len
= ARRAY_SIZE(tuner_init_tda18218
);
315 init
= tuner_init_tda18218
;
317 case AF9033_TUNER_FC2580
:
318 len
= ARRAY_SIZE(tuner_init_fc2580
);
319 init
= tuner_init_fc2580
;
321 case AF9033_TUNER_FC0012
:
322 len
= ARRAY_SIZE(tuner_init_fc0012
);
323 init
= tuner_init_fc0012
;
326 dev_dbg(&state
->i2c
->dev
, "%s: unsupported tuner ID=%d\n",
327 __func__
, state
->cfg
.tuner
);
332 for (i
= 0; i
< len
; i
++) {
333 ret
= af9033_wr_reg(state
, init
[i
].reg
, init
[i
].val
);
338 if (state
->cfg
.ts_mode
== AF9033_TS_MODE_SERIAL
) {
339 ret
= af9033_wr_reg_mask(state
, 0x00d91c, 0x01, 0x01);
343 ret
= af9033_wr_reg_mask(state
, 0x00d917, 0x00, 0x01);
347 ret
= af9033_wr_reg_mask(state
, 0x00d916, 0x00, 0x01);
352 state
->bandwidth_hz
= 0; /* force to program all parameters */
357 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
362 static int af9033_sleep(struct dvb_frontend
*fe
)
364 struct af9033_state
*state
= fe
->demodulator_priv
;
368 ret
= af9033_wr_reg(state
, 0x80004c, 1);
372 ret
= af9033_wr_reg(state
, 0x800000, 0);
376 for (i
= 100, tmp
= 1; i
&& tmp
; i
--) {
377 ret
= af9033_rd_reg(state
, 0x80004c, &tmp
);
381 usleep_range(200, 10000);
384 dev_dbg(&state
->i2c
->dev
, "%s: loop=%d\n", __func__
, i
);
391 ret
= af9033_wr_reg_mask(state
, 0x80fb24, 0x08, 0x08);
395 /* prevent current leak (?) */
396 if (state
->cfg
.ts_mode
== AF9033_TS_MODE_SERIAL
) {
397 /* enable parallel TS */
398 ret
= af9033_wr_reg_mask(state
, 0x00d917, 0x00, 0x01);
402 ret
= af9033_wr_reg_mask(state
, 0x00d916, 0x01, 0x01);
410 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
415 static int af9033_get_tune_settings(struct dvb_frontend
*fe
,
416 struct dvb_frontend_tune_settings
*fesettings
)
418 fesettings
->min_delay_ms
= 800;
419 fesettings
->step_size
= 0;
420 fesettings
->max_drift
= 0;
425 static int af9033_set_frontend(struct dvb_frontend
*fe
)
427 struct af9033_state
*state
= fe
->demodulator_priv
;
428 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
429 int ret
, i
, spec_inv
, sampling_freq
;
430 u8 tmp
, buf
[3], bandwidth_reg_val
;
431 u32 if_frequency
, freq_cw
, adc_freq
;
433 dev_dbg(&state
->i2c
->dev
, "%s: frequency=%d bandwidth_hz=%d\n",
434 __func__
, c
->frequency
, c
->bandwidth_hz
);
436 /* check bandwidth */
437 switch (c
->bandwidth_hz
) {
439 bandwidth_reg_val
= 0x00;
442 bandwidth_reg_val
= 0x01;
445 bandwidth_reg_val
= 0x02;
448 dev_dbg(&state
->i2c
->dev
, "%s: invalid bandwidth_hz\n",
455 if (fe
->ops
.tuner_ops
.set_params
)
456 fe
->ops
.tuner_ops
.set_params(fe
);
458 /* program CFOE coefficients */
459 if (c
->bandwidth_hz
!= state
->bandwidth_hz
) {
460 for (i
= 0; i
< ARRAY_SIZE(coeff_lut
); i
++) {
461 if (coeff_lut
[i
].clock
== state
->cfg
.clock
&&
462 coeff_lut
[i
].bandwidth_hz
== c
->bandwidth_hz
) {
466 ret
= af9033_wr_regs(state
, 0x800001,
467 coeff_lut
[i
].val
, sizeof(coeff_lut
[i
].val
));
470 /* program frequency control */
471 if (c
->bandwidth_hz
!= state
->bandwidth_hz
) {
472 spec_inv
= state
->cfg
.spec_inv
? -1 : 1;
474 for (i
= 0; i
< ARRAY_SIZE(clock_adc_lut
); i
++) {
475 if (clock_adc_lut
[i
].clock
== state
->cfg
.clock
)
478 adc_freq
= clock_adc_lut
[i
].adc
;
480 /* get used IF frequency */
481 if (fe
->ops
.tuner_ops
.get_if_frequency
)
482 fe
->ops
.tuner_ops
.get_if_frequency(fe
, &if_frequency
);
486 sampling_freq
= if_frequency
;
488 while (sampling_freq
> (adc_freq
/ 2))
489 sampling_freq
-= adc_freq
;
491 if (sampling_freq
>= 0)
496 freq_cw
= af9033_div(state
, sampling_freq
, adc_freq
, 23ul);
499 freq_cw
= 0x800000 - freq_cw
;
501 /* get adc multiplies */
502 ret
= af9033_rd_reg(state
, 0x800045, &tmp
);
509 buf
[0] = (freq_cw
>> 0) & 0xff;
510 buf
[1] = (freq_cw
>> 8) & 0xff;
511 buf
[2] = (freq_cw
>> 16) & 0x7f;
512 ret
= af9033_wr_regs(state
, 0x800029, buf
, 3);
516 state
->bandwidth_hz
= c
->bandwidth_hz
;
519 ret
= af9033_wr_reg_mask(state
, 0x80f904, bandwidth_reg_val
, 0x03);
523 ret
= af9033_wr_reg(state
, 0x800040, 0x00);
527 ret
= af9033_wr_reg(state
, 0x800047, 0x00);
531 ret
= af9033_wr_reg_mask(state
, 0x80f999, 0x00, 0x01);
535 if (c
->frequency
<= 230000000)
536 tmp
= 0x00; /* VHF */
538 tmp
= 0x01; /* UHF */
540 ret
= af9033_wr_reg(state
, 0x80004b, tmp
);
544 ret
= af9033_wr_reg(state
, 0x800000, 0x00);
551 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
556 static int af9033_get_frontend(struct dvb_frontend
*fe
)
558 struct af9033_state
*state
= fe
->demodulator_priv
;
559 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
563 dev_dbg(&state
->i2c
->dev
, "%s:\n", __func__
);
565 /* read all needed registers */
566 ret
= af9033_rd_regs(state
, 0x80f900, buf
, sizeof(buf
));
570 switch ((buf
[0] >> 0) & 3) {
572 c
->transmission_mode
= TRANSMISSION_MODE_2K
;
575 c
->transmission_mode
= TRANSMISSION_MODE_8K
;
579 switch ((buf
[1] >> 0) & 3) {
581 c
->guard_interval
= GUARD_INTERVAL_1_32
;
584 c
->guard_interval
= GUARD_INTERVAL_1_16
;
587 c
->guard_interval
= GUARD_INTERVAL_1_8
;
590 c
->guard_interval
= GUARD_INTERVAL_1_4
;
594 switch ((buf
[2] >> 0) & 7) {
596 c
->hierarchy
= HIERARCHY_NONE
;
599 c
->hierarchy
= HIERARCHY_1
;
602 c
->hierarchy
= HIERARCHY_2
;
605 c
->hierarchy
= HIERARCHY_4
;
609 switch ((buf
[3] >> 0) & 3) {
611 c
->modulation
= QPSK
;
614 c
->modulation
= QAM_16
;
617 c
->modulation
= QAM_64
;
621 switch ((buf
[4] >> 0) & 3) {
623 c
->bandwidth_hz
= 6000000;
626 c
->bandwidth_hz
= 7000000;
629 c
->bandwidth_hz
= 8000000;
633 switch ((buf
[6] >> 0) & 7) {
635 c
->code_rate_HP
= FEC_1_2
;
638 c
->code_rate_HP
= FEC_2_3
;
641 c
->code_rate_HP
= FEC_3_4
;
644 c
->code_rate_HP
= FEC_5_6
;
647 c
->code_rate_HP
= FEC_7_8
;
650 c
->code_rate_HP
= FEC_NONE
;
654 switch ((buf
[7] >> 0) & 7) {
656 c
->code_rate_LP
= FEC_1_2
;
659 c
->code_rate_LP
= FEC_2_3
;
662 c
->code_rate_LP
= FEC_3_4
;
665 c
->code_rate_LP
= FEC_5_6
;
668 c
->code_rate_LP
= FEC_7_8
;
671 c
->code_rate_LP
= FEC_NONE
;
678 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
683 static int af9033_read_status(struct dvb_frontend
*fe
, fe_status_t
*status
)
685 struct af9033_state
*state
= fe
->demodulator_priv
;
691 /* radio channel status, 0=no result, 1=has signal, 2=no signal */
692 ret
= af9033_rd_reg(state
, 0x800047, &tmp
);
698 *status
|= FE_HAS_SIGNAL
;
702 ret
= af9033_rd_reg_mask(state
, 0x80f5a9, &tmp
, 0x01);
707 *status
|= FE_HAS_SIGNAL
| FE_HAS_CARRIER
|
711 ret
= af9033_rd_reg_mask(state
, 0x80f999, &tmp
, 0x01);
716 *status
|= FE_HAS_SIGNAL
| FE_HAS_CARRIER
|
717 FE_HAS_VITERBI
| FE_HAS_SYNC
|
724 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
729 static int af9033_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
731 struct af9033_state
*state
= fe
->demodulator_priv
;
735 const struct val_snr
*uninitialized_var(snr_lut
);
738 ret
= af9033_rd_regs(state
, 0x80002c, buf
, 3);
742 snr_val
= (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
744 /* read current modulation */
745 ret
= af9033_rd_reg(state
, 0x80f903, &tmp
);
749 switch ((tmp
>> 0) & 3) {
751 len
= ARRAY_SIZE(qpsk_snr_lut
);
752 snr_lut
= qpsk_snr_lut
;
755 len
= ARRAY_SIZE(qam16_snr_lut
);
756 snr_lut
= qam16_snr_lut
;
759 len
= ARRAY_SIZE(qam64_snr_lut
);
760 snr_lut
= qam64_snr_lut
;
766 for (i
= 0; i
< len
; i
++) {
767 tmp
= snr_lut
[i
].snr
;
769 if (snr_val
< snr_lut
[i
].val
)
773 *snr
= tmp
* 10; /* dB/10 */
778 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
783 static int af9033_read_signal_strength(struct dvb_frontend
*fe
, u16
*strength
)
785 struct af9033_state
*state
= fe
->demodulator_priv
;
789 /* read signal strength of 0-100 scale */
790 ret
= af9033_rd_reg(state
, 0x800048, &strength2
);
794 /* scale value to 0x0000-0xffff */
795 *strength
= strength2
* 0xffff / 100;
800 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
805 static int af9033_update_ch_stat(struct af9033_state
*state
)
808 u32 err_cnt
, bit_cnt
;
812 /* only update data every half second */
813 if (time_after(jiffies
, state
->last_stat_check
+ msecs_to_jiffies(500))) {
814 ret
= af9033_rd_regs(state
, 0x800032, buf
, sizeof(buf
));
817 /* in 8 byte packets? */
818 abort_cnt
= (buf
[1] << 8) + buf
[0];
820 err_cnt
= (buf
[4] << 16) + (buf
[3] << 8) + buf
[2];
821 /* in 8 byte packets? always(?) 0x2710 = 10000 */
822 bit_cnt
= (buf
[6] << 8) + buf
[5];
824 if (bit_cnt
< abort_cnt
) {
826 state
->ber
= 0xffffffff;
828 /* 8 byte packets, that have not been rejected already */
829 bit_cnt
-= (u32
)abort_cnt
;
831 state
->ber
= 0xffffffff;
833 err_cnt
-= (u32
)abort_cnt
* 8 * 8;
835 state
->ber
= err_cnt
* (0xffffffff / bit_cnt
);
838 state
->ucb
+= abort_cnt
;
839 state
->last_stat_check
= jiffies
;
844 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
849 static int af9033_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
851 struct af9033_state
*state
= fe
->demodulator_priv
;
854 ret
= af9033_update_ch_stat(state
);
863 static int af9033_read_ucblocks(struct dvb_frontend
*fe
, u32
*ucblocks
)
865 struct af9033_state
*state
= fe
->demodulator_priv
;
868 ret
= af9033_update_ch_stat(state
);
872 *ucblocks
= state
->ucb
;
877 static int af9033_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
879 struct af9033_state
*state
= fe
->demodulator_priv
;
882 dev_dbg(&state
->i2c
->dev
, "%s: enable=%d\n", __func__
, enable
);
884 ret
= af9033_wr_reg_mask(state
, 0x00fa04, enable
, 0x01);
891 dev_dbg(&state
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
896 static struct dvb_frontend_ops af9033_ops
;
898 struct dvb_frontend
*af9033_attach(const struct af9033_config
*config
,
899 struct i2c_adapter
*i2c
)
902 struct af9033_state
*state
;
905 dev_dbg(&i2c
->dev
, "%s:\n", __func__
);
907 /* allocate memory for the internal state */
908 state
= kzalloc(sizeof(struct af9033_state
), GFP_KERNEL
);
912 /* setup the state */
914 memcpy(&state
->cfg
, config
, sizeof(struct af9033_config
));
916 if (state
->cfg
.clock
!= 12000000) {
917 dev_err(&state
->i2c
->dev
, "%s: af9033: unsupported clock=%d, " \
918 "only 12000000 Hz is supported currently\n",
919 KBUILD_MODNAME
, state
->cfg
.clock
);
923 /* firmware version */
924 ret
= af9033_rd_regs(state
, 0x0083e9, &buf
[0], 4);
928 ret
= af9033_rd_regs(state
, 0x804191, &buf
[4], 4);
932 dev_info(&state
->i2c
->dev
, "%s: firmware version: LINK=%d.%d.%d.%d " \
933 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME
, buf
[0], buf
[1],
934 buf
[2], buf
[3], buf
[4], buf
[5], buf
[6], buf
[7]);
937 ret
= af9033_wr_reg(state
, 0x80004c, 1);
941 ret
= af9033_wr_reg(state
, 0x800000, 0);
945 /* configure internal TS mode */
946 switch (state
->cfg
.ts_mode
) {
947 case AF9033_TS_MODE_PARALLEL
:
948 state
->ts_mode_parallel
= true;
950 case AF9033_TS_MODE_SERIAL
:
951 state
->ts_mode_serial
= true;
953 case AF9033_TS_MODE_USB
:
954 /* usb mode for AF9035 */
959 /* create dvb_frontend */
960 memcpy(&state
->fe
.ops
, &af9033_ops
, sizeof(struct dvb_frontend_ops
));
961 state
->fe
.demodulator_priv
= state
;
969 EXPORT_SYMBOL(af9033_attach
);
971 static struct dvb_frontend_ops af9033_ops
= {
972 .delsys
= { SYS_DVBT
},
974 .name
= "Afatech AF9033 (DVB-T)",
975 .frequency_min
= 174000000,
976 .frequency_max
= 862000000,
977 .frequency_stepsize
= 250000,
978 .frequency_tolerance
= 0,
979 .caps
= FE_CAN_FEC_1_2
|
989 FE_CAN_TRANSMISSION_MODE_AUTO
|
990 FE_CAN_GUARD_INTERVAL_AUTO
|
991 FE_CAN_HIERARCHY_AUTO
|
996 .release
= af9033_release
,
999 .sleep
= af9033_sleep
,
1001 .get_tune_settings
= af9033_get_tune_settings
,
1002 .set_frontend
= af9033_set_frontend
,
1003 .get_frontend
= af9033_get_frontend
,
1005 .read_status
= af9033_read_status
,
1006 .read_snr
= af9033_read_snr
,
1007 .read_signal_strength
= af9033_read_signal_strength
,
1008 .read_ber
= af9033_read_ber
,
1009 .read_ucblocks
= af9033_read_ucblocks
,
1011 .i2c_gate_ctrl
= af9033_i2c_gate_ctrl
,
1014 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1015 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1016 MODULE_LICENSE("GPL");