4 * Sony digital demodulator driver for
5 * CXD2441ER - DVB-S/S2/T/T2/C/C2
6 * CXD2454ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <linux/bitops.h>
29 #include <linux/math64.h>
30 #include <linux/log2.h>
31 #include <linux/dynamic_debug.h>
34 #include "dvb_frontend.h"
35 #include "cxd2841er.h"
36 #include "cxd2841er_priv.h"
38 #define MAX_WRITE_REGSIZE 16
40 enum cxd2841er_state
{
48 struct cxd2841er_priv
{
49 struct dvb_frontend frontend
;
50 struct i2c_adapter
*i2c
;
53 const struct cxd2841er_config
*config
;
54 enum cxd2841er_state state
;
56 enum cxd2841er_xtal xtal
;
59 static const struct cxd2841er_cnr_data s_cn_data
[] = {
60 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
61 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
62 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
63 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
64 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
65 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
66 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
67 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
68 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
69 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
70 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
71 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
72 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
73 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
74 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
75 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
76 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
77 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
78 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
79 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
80 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
81 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
82 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
83 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
84 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
85 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
86 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
87 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
88 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
89 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
90 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
91 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
92 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
93 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
94 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
95 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
96 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
97 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
98 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
99 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
100 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
101 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
102 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
103 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
104 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
105 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
106 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
107 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
108 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
109 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
110 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
111 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
112 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
113 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
114 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
115 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
116 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
117 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
118 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
119 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
120 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
121 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
122 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
123 { 0x0015, 19900 }, { 0x0014, 20000 },
126 static const struct cxd2841er_cnr_data s2_cn_data
[] = {
127 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
128 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
129 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
130 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
131 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
132 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
133 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
134 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
135 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
136 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
137 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
138 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
139 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
140 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
141 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
142 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
143 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
144 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
145 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
146 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
147 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
148 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
149 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
150 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
151 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
152 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
153 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
154 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
155 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
156 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
157 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
158 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
159 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
160 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
161 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
162 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
163 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
164 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
165 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
166 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
167 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
168 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
169 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
170 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
171 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
172 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
173 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
174 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
175 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
176 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
177 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
178 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
179 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
180 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
181 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
182 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
183 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
184 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
185 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
186 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
187 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
188 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
189 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
190 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
193 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
194 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
195 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
196 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
198 static void cxd2841er_i2c_debug(struct cxd2841er_priv
*priv
,
199 u8 addr
, u8 reg
, u8 write
,
200 const u8
*data
, u32 len
)
202 dev_dbg(&priv
->i2c
->dev
,
203 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
204 (write
== 0 ? "read" : "write"), addr
, reg
, len
);
205 print_hex_dump_bytes("cxd2841er: I2C data: ",
206 DUMP_PREFIX_OFFSET
, data
, len
);
209 static int cxd2841er_write_regs(struct cxd2841er_priv
*priv
,
210 u8 addr
, u8 reg
, const u8
*data
, u32 len
)
213 u8 buf
[MAX_WRITE_REGSIZE
+ 1];
214 u8 i2c_addr
= (addr
== I2C_SLVX
?
215 priv
->i2c_addr_slvx
: priv
->i2c_addr_slvt
);
216 struct i2c_msg msg
[1] = {
225 if (len
+ 1 >= sizeof(buf
)) {
226 dev_warn(&priv
->i2c
->dev
, "wr reg=%04x: len=%d is too big!\n",
231 cxd2841er_i2c_debug(priv
, i2c_addr
, reg
, 1, data
, len
);
233 memcpy(&buf
[1], data
, len
);
235 ret
= i2c_transfer(priv
->i2c
, msg
, 1);
236 if (ret
>= 0 && ret
!= 1)
239 dev_warn(&priv
->i2c
->dev
,
240 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
241 KBUILD_MODNAME
, ret
, i2c_addr
, reg
, len
);
247 static int cxd2841er_write_reg(struct cxd2841er_priv
*priv
,
248 u8 addr
, u8 reg
, u8 val
)
250 return cxd2841er_write_regs(priv
, addr
, reg
, &val
, 1);
253 static int cxd2841er_read_regs(struct cxd2841er_priv
*priv
,
254 u8 addr
, u8 reg
, u8
*val
, u32 len
)
257 u8 i2c_addr
= (addr
== I2C_SLVX
?
258 priv
->i2c_addr_slvx
: priv
->i2c_addr_slvt
);
259 struct i2c_msg msg
[2] = {
273 ret
= i2c_transfer(priv
->i2c
, &msg
[0], 1);
274 if (ret
>= 0 && ret
!= 1)
277 dev_warn(&priv
->i2c
->dev
,
278 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
279 KBUILD_MODNAME
, ret
, i2c_addr
, reg
);
282 ret
= i2c_transfer(priv
->i2c
, &msg
[1], 1);
283 if (ret
>= 0 && ret
!= 1)
286 dev_warn(&priv
->i2c
->dev
,
287 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
288 KBUILD_MODNAME
, ret
, i2c_addr
, reg
);
294 static int cxd2841er_read_reg(struct cxd2841er_priv
*priv
,
295 u8 addr
, u8 reg
, u8
*val
)
297 return cxd2841er_read_regs(priv
, addr
, reg
, val
, 1);
300 static int cxd2841er_set_reg_bits(struct cxd2841er_priv
*priv
,
301 u8 addr
, u8 reg
, u8 data
, u8 mask
)
307 res
= cxd2841er_read_reg(priv
, addr
, reg
, &rdata
);
310 data
= ((data
& mask
) | (rdata
& (mask
^ 0xFF)));
312 return cxd2841er_write_reg(priv
, addr
, reg
, data
);
315 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv
*priv
,
319 u8 data
[3] = {0, 0, 0};
321 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
323 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
324 * = ((symbolRateKSps * 2^14) + 500) / 1000
325 * = ((symbolRateKSps * 16384) + 500) / 1000
327 reg_value
= DIV_ROUND_CLOSEST(symbol_rate
* 16384, 1000);
328 if ((reg_value
== 0) || (reg_value
> 0xFFFFF)) {
329 dev_err(&priv
->i2c
->dev
,
330 "%s(): reg_value is out of range\n", __func__
);
333 data
[0] = (u8
)((reg_value
>> 16) & 0x0F);
334 data
[1] = (u8
)((reg_value
>> 8) & 0xFF);
335 data
[2] = (u8
)(reg_value
& 0xFF);
336 /* Set SLV-T Bank : 0xAE */
337 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xae);
338 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x20, data
, 3);
342 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv
*priv
,
345 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv
*priv
,
346 u8 system
, u32 symbol_rate
)
349 u8 data
[4] = { 0, 0, 0, 0 };
351 if (priv
->state
!= STATE_SLEEP_S
) {
352 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
353 __func__
, (int)priv
->state
);
356 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
357 cxd2841er_set_ts_clock_mode(priv
, SYS_DVBS
);
359 if (system
== SYS_DVBS
) {
361 } else if (system
== SYS_DVBS2
) {
364 dev_err(&priv
->i2c
->dev
, "%s(): invalid delsys %d\n",
368 /* Set SLV-X Bank : 0x00 */
369 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
370 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, data
[0]);
373 /* Set SLV-T Bank : 0x00 */
374 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
375 /* Enable S/S2 auto detection 1 */
376 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2d, data
[0]);
377 /* Set SLV-T Bank : 0xAE */
378 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xae);
379 /* Enable S/S2 auto detection 2 */
380 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, data
[0]);
381 /* Set SLV-T Bank : 0x00 */
382 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
383 /* Enable demod clock */
384 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x01);
385 /* Enable ADC clock */
386 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x31, 0x01);
388 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x63, 0x16);
390 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x65, 0x3f);
391 /* Set SLV-X Bank : 0x00 */
392 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
394 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x00);
395 /* Set SLV-T Bank : 0xA3 */
396 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa3);
397 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xac, 0x00);
402 /* Set SLV-T Bank : 0xAB */
403 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xab);
404 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x98, data
, 4);
409 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xa8, data
, 4);
412 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xc3, data
, 2);
413 /* Set demod parameter */
414 ret
= cxd2841er_dvbs2_set_symbol_rate(priv
, symbol_rate
);
417 /* Set SLV-T Bank : 0x00 */
418 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
419 /* disable Hi-Z setting 1 */
420 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x10);
421 /* disable Hi-Z setting 2 */
422 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0x00);
423 priv
->state
= STATE_ACTIVE_S
;
427 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv
*priv
,
430 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv
*priv
,
433 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv
*priv
,
436 static int cxd2841er_retune_active(struct cxd2841er_priv
*priv
,
437 struct dtv_frontend_properties
*p
)
439 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
440 if (priv
->state
!= STATE_ACTIVE_S
&&
441 priv
->state
!= STATE_ACTIVE_TC
) {
442 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
443 __func__
, priv
->state
);
446 /* Set SLV-T Bank : 0x00 */
447 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
448 /* disable TS output */
449 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xc3, 0x01);
450 if (priv
->state
== STATE_ACTIVE_S
)
451 return cxd2841er_dvbs2_set_symbol_rate(
452 priv
, p
->symbol_rate
/ 1000);
453 else if (priv
->state
== STATE_ACTIVE_TC
) {
454 switch (priv
->system
) {
456 return cxd2841er_sleep_tc_to_active_t_band(
457 priv
, p
->bandwidth_hz
);
459 return cxd2841er_sleep_tc_to_active_t2_band(
460 priv
, p
->bandwidth_hz
);
461 case SYS_DVBC_ANNEX_A
:
462 return cxd2841er_sleep_tc_to_active_c_band(
466 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid delivery system %d\n",
467 __func__
, priv
->system
);
471 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv
*priv
)
473 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
474 if (priv
->state
!= STATE_ACTIVE_S
) {
475 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
476 __func__
, priv
->state
);
479 /* Set SLV-T Bank : 0x00 */
480 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
481 /* disable TS output */
482 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xc3, 0x01);
483 /* enable Hi-Z setting 1 */
484 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x1f);
485 /* enable Hi-Z setting 2 */
486 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0xff);
487 /* Set SLV-X Bank : 0x00 */
488 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
490 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x01);
491 /* Set SLV-T Bank : 0x00 */
492 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
493 /* disable ADC clock */
494 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x31, 0x00);
496 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x63, 0x16);
498 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x65, 0x27);
500 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x69, 0x06);
501 /* disable demod clock */
502 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x00);
503 /* Set SLV-T Bank : 0xAE */
504 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xae);
505 /* disable S/S2 auto detection1 */
506 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
507 /* Set SLV-T Bank : 0x00 */
508 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
509 /* disable S/S2 auto detection2 */
510 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2d, 0x00);
511 priv
->state
= STATE_SLEEP_S
;
515 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv
*priv
)
517 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
518 if (priv
->state
!= STATE_SLEEP_S
) {
519 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid demod state %d\n",
520 __func__
, priv
->state
);
523 /* Set SLV-T Bank : 0x00 */
524 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
526 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x3f);
528 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x9c, 0x00);
529 /* Set SLV-X Bank : 0x00 */
530 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
531 /* Disable oscillator */
532 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x15, 0x01);
534 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, 0x01);
535 priv
->state
= STATE_SHUTDOWN
;
539 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv
*priv
)
541 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
542 if (priv
->state
!= STATE_SLEEP_TC
) {
543 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid demod state %d\n",
544 __func__
, priv
->state
);
547 /* Set SLV-X Bank : 0x00 */
548 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
549 /* Disable oscillator */
550 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x15, 0x01);
552 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, 0x01);
553 priv
->state
= STATE_SHUTDOWN
;
557 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv
*priv
)
559 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
560 if (priv
->state
!= STATE_ACTIVE_TC
) {
561 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
562 __func__
, priv
->state
);
565 /* Set SLV-T Bank : 0x00 */
566 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
567 /* disable TS output */
568 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xc3, 0x01);
569 /* enable Hi-Z setting 1 */
570 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x3f);
571 /* enable Hi-Z setting 2 */
572 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0xff);
573 /* Set SLV-X Bank : 0x00 */
574 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
576 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x01);
577 /* Set SLV-T Bank : 0x00 */
578 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
580 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x43, 0x0a);
582 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x0a);
583 /* Disable ADC clock */
584 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
585 /* Disable RF level monitor */
586 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x00);
587 /* Disable demod clock */
588 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x00);
589 priv
->state
= STATE_SLEEP_TC
;
593 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv
*priv
)
595 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
596 if (priv
->state
!= STATE_ACTIVE_TC
) {
597 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
598 __func__
, priv
->state
);
601 /* Set SLV-T Bank : 0x00 */
602 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
603 /* disable TS output */
604 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xc3, 0x01);
605 /* enable Hi-Z setting 1 */
606 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x3f);
607 /* enable Hi-Z setting 2 */
608 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0xff);
609 /* Cancel DVB-T2 setting */
610 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x13);
611 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x83, 0x40);
612 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x86, 0x21);
613 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x9e, 0x09, 0x0f);
614 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x9f, 0xfb);
615 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x2a);
616 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x38, 0x00, 0x0f);
617 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x2b);
618 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x11, 0x00, 0x3f);
619 /* Set SLV-X Bank : 0x00 */
620 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
622 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x01);
623 /* Set SLV-T Bank : 0x00 */
624 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
626 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x43, 0x0a);
628 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x0a);
629 /* Disable ADC clock */
630 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
631 /* Disable RF level monitor */
632 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x00);
633 /* Disable demod clock */
634 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x00);
635 priv
->state
= STATE_SLEEP_TC
;
639 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv
*priv
)
641 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
642 if (priv
->state
!= STATE_ACTIVE_TC
) {
643 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
644 __func__
, priv
->state
);
647 /* Set SLV-T Bank : 0x00 */
648 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
649 /* disable TS output */
650 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xc3, 0x01);
651 /* enable Hi-Z setting 1 */
652 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x3f);
653 /* enable Hi-Z setting 2 */
654 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0xff);
655 /* Cancel DVB-C setting */
656 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x11);
657 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xa3, 0x00, 0x1f);
658 /* Set SLV-X Bank : 0x00 */
659 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
661 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x01);
662 /* Set SLV-T Bank : 0x00 */
663 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
665 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x43, 0x0a);
667 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x0a);
668 /* Disable ADC clock */
669 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
670 /* Disable RF level monitor */
671 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x00);
672 /* Disable demod clock */
673 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x00);
674 priv
->state
= STATE_SLEEP_TC
;
678 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv
*priv
)
680 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
681 if (priv
->state
!= STATE_ACTIVE_TC
) {
682 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
683 __func__
, priv
->state
);
686 /* Set SLV-T Bank : 0x00 */
687 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
688 /* disable TS output */
689 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xc3, 0x01);
690 /* enable Hi-Z setting 1 */
691 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x3f);
692 /* enable Hi-Z setting 2 */
693 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0xff);
695 /* TODO: Cancel demod parameter */
697 /* Set SLV-X Bank : 0x00 */
698 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
700 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x01);
701 /* Set SLV-T Bank : 0x00 */
702 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
704 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x43, 0x0a);
706 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x0a);
707 /* Disable ADC clock */
708 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
709 /* Disable RF level monitor */
710 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x00);
711 /* Disable demod clock */
712 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x00);
713 priv
->state
= STATE_SLEEP_TC
;
717 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv
*priv
)
719 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
720 if (priv
->state
!= STATE_SHUTDOWN
) {
721 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid demod state %d\n",
722 __func__
, priv
->state
);
725 /* Set SLV-X Bank : 0x00 */
726 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
727 /* Clear all demodulator registers */
728 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x02, 0x00);
729 usleep_range(3000, 5000);
730 /* Set SLV-X Bank : 0x00 */
731 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
732 /* Set demod SW reset */
733 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x10, 0x01);
735 switch (priv
->xtal
) {
736 case SONY_XTAL_20500
:
737 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x14, 0x00);
739 case SONY_XTAL_24000
:
740 /* Select demod frequency */
741 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x12, 0x00);
742 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x14, 0x03);
744 case SONY_XTAL_41000
:
745 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x14, 0x01);
748 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid demod xtal %d\n",
749 __func__
, priv
->xtal
);
754 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, 0x0a);
755 /* Clear demod SW reset */
756 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x10, 0x00);
757 usleep_range(1000, 2000);
758 /* Set SLV-T Bank : 0x00 */
759 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
761 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x1F);
763 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x9C, 0x40);
765 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x43, 0x0a);
766 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x0a);
768 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x63, 0x16);
769 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x65, 0x27);
770 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x69, 0x06);
771 priv
->state
= STATE_SLEEP_S
;
775 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv
*priv
)
777 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
778 if (priv
->state
!= STATE_SHUTDOWN
) {
779 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid demod state %d\n",
780 __func__
, priv
->state
);
783 /* Set SLV-X Bank : 0x00 */
784 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
785 /* Clear all demodulator registers */
786 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x02, 0x00);
787 usleep_range(3000, 5000);
788 /* Set SLV-X Bank : 0x00 */
789 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
790 /* Set demod SW reset */
791 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x10, 0x01);
792 /* Set X'tal clock to 20.5Mhz */
793 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x13, 0x00);
794 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x14, 0x00);
795 /* Clear demod SW reset */
796 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x10, 0x00);
797 usleep_range(1000, 2000);
798 /* Set SLV-T Bank : 0x00 */
799 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
801 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x43, 0x0a);
802 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x0a);
804 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x63, 0x16);
805 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x65, 0x27);
806 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x69, 0x06);
807 priv
->state
= STATE_SLEEP_TC
;
811 static int cxd2841er_tune_done(struct cxd2841er_priv
*priv
)
813 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
814 /* Set SLV-T Bank : 0x00 */
815 cxd2841er_write_reg(priv
, I2C_SLVT
, 0, 0);
817 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xfe, 0x01);
818 /* Enable TS output */
819 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xc3, 0x00);
823 /* Set TS parallel mode */
824 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv
*priv
,
827 u8 serial_ts
, ts_rate_ctrl_off
, ts_in_off
;
829 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
830 /* Set SLV-T Bank : 0x00 */
831 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
832 cxd2841er_read_reg(priv
, I2C_SLVT
, 0xc4, &serial_ts
);
833 cxd2841er_read_reg(priv
, I2C_SLVT
, 0xd3, &ts_rate_ctrl_off
);
834 cxd2841er_read_reg(priv
, I2C_SLVT
, 0xde, &ts_in_off
);
835 dev_dbg(&priv
->i2c
->dev
, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
836 __func__
, serial_ts
, ts_rate_ctrl_off
, ts_in_off
);
839 * slave Bank Addr Bit default Name
840 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
842 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xd9, 0x08);
844 * Disable TS IF Clock
845 * slave Bank Addr Bit default Name
846 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
848 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x32, 0x00, 0x01);
850 * slave Bank Addr Bit default Name
851 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
853 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x33, 0x00, 0x03);
856 * slave Bank Addr Bit default Name
857 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
859 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x32, 0x01, 0x01);
861 if (system
== SYS_DVBT
) {
862 /* Enable parity period for DVB-T */
863 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
864 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x66, 0x01, 0x01);
865 } else if (system
== SYS_DVBC_ANNEX_A
) {
866 /* Enable parity period for DVB-C */
867 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x40);
868 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x66, 0x01, 0x01);
872 static u8
cxd2841er_chip_id(struct cxd2841er_priv
*priv
)
876 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
877 if (cxd2841er_write_reg(priv
, I2C_SLVT
, 0, 0) == 0)
878 cxd2841er_read_reg(priv
, I2C_SLVT
, 0xfd, &chip_id
);
879 else if (cxd2841er_write_reg(priv
, I2C_SLVX
, 0, 0) == 0)
880 cxd2841er_read_reg(priv
, I2C_SLVX
, 0xfd, &chip_id
);
885 static int cxd2841er_read_status_s(struct dvb_frontend
*fe
,
886 enum fe_status
*status
)
889 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
891 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
893 if (priv
->state
!= STATE_ACTIVE_S
) {
894 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
895 __func__
, priv
->state
);
898 /* Set SLV-T Bank : 0xA0 */
899 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa0);
901 * slave Bank Addr Bit Signal name
902 * <SLV-T> A0h 11h [2] ITSLOCK
904 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x11, ®
);
906 *status
= FE_HAS_SIGNAL
912 dev_dbg(&priv
->i2c
->dev
, "%s(): result 0x%x\n", __func__
, *status
);
916 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv
*priv
,
917 u8
*sync
, u8
*tslock
, u8
*unlock
)
921 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
922 if (priv
->state
!= STATE_ACTIVE_TC
)
924 if (priv
->system
== SYS_DVBT
) {
925 /* Set SLV-T Bank : 0x10 */
926 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
928 /* Set SLV-T Bank : 0x20 */
929 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x20);
931 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x10, &data
);
932 if ((data
& 0x07) == 0x07) {
933 dev_dbg(&priv
->i2c
->dev
,
934 "%s(): invalid hardware state detected\n", __func__
);
939 *sync
= ((data
& 0x07) == 0x6 ? 1 : 0);
940 *tslock
= ((data
& 0x20) ? 1 : 0);
941 *unlock
= ((data
& 0x10) ? 1 : 0);
946 static int cxd2841er_read_status_c(struct cxd2841er_priv
*priv
, u8
*tslock
)
950 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
951 if (priv
->state
!= STATE_ACTIVE_TC
)
953 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x40);
954 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x88, &data
);
955 if ((data
& 0x01) == 0) {
958 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x10, &data
);
959 *tslock
= ((data
& 0x20) ? 1 : 0);
964 static int cxd2841er_read_status_i(struct cxd2841er_priv
*priv
,
965 u8
*sync
, u8
*tslock
, u8
*unlock
)
969 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
970 if (priv
->state
!= STATE_ACTIVE_TC
)
972 /* Set SLV-T Bank : 0x60 */
973 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x60);
974 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x10, &data
);
975 dev_dbg(&priv
->i2c
->dev
,
976 "%s(): lock=0x%x\n", __func__
, data
);
977 *sync
= ((data
& 0x02) ? 1 : 0);
978 *tslock
= ((data
& 0x01) ? 1 : 0);
979 *unlock
= ((data
& 0x10) ? 1 : 0);
983 static int cxd2841er_read_status_tc(struct dvb_frontend
*fe
,
984 enum fe_status
*status
)
990 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
993 if (priv
->state
== STATE_ACTIVE_TC
) {
994 if (priv
->system
== SYS_DVBT
|| priv
->system
== SYS_DVBT2
) {
995 ret
= cxd2841er_read_status_t_t2(
996 priv
, &sync
, &tslock
, &unlock
);
1002 *status
= FE_HAS_SIGNAL
|
1007 *status
|= FE_HAS_LOCK
;
1008 } else if (priv
->system
== SYS_ISDBT
) {
1009 ret
= cxd2841er_read_status_i(
1010 priv
, &sync
, &tslock
, &unlock
);
1016 *status
= FE_HAS_SIGNAL
|
1021 *status
|= FE_HAS_LOCK
;
1022 } else if (priv
->system
== SYS_DVBC_ANNEX_A
) {
1023 ret
= cxd2841er_read_status_c(priv
, &tslock
);
1027 *status
= FE_HAS_SIGNAL
|
1035 dev_dbg(&priv
->i2c
->dev
, "%s(): status 0x%x\n", __func__
, *status
);
1039 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv
*priv
,
1045 s32 temp_div
, temp_q
, temp_r
;
1047 if (priv
->state
!= STATE_ACTIVE_S
) {
1048 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
1049 __func__
, priv
->state
);
1053 * Get High Sampling Rate mode
1054 * slave Bank Addr Bit Signal name
1055 * <SLV-T> A0h 10h [0] ITRL_LOCK
1057 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa0);
1058 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x10, &data
[0]);
1059 if (data
[0] & 0x01) {
1061 * slave Bank Addr Bit Signal name
1062 * <SLV-T> A0h 50h [4] IHSMODE
1064 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x50, &data
[0]);
1065 is_hs_mode
= (data
[0] & 0x10 ? 1 : 0);
1067 dev_dbg(&priv
->i2c
->dev
,
1068 "%s(): unable to detect sampling rate mode\n",
1073 * slave Bank Addr Bit Signal name
1074 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1075 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1076 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1078 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x45, data
, 3);
1079 cfrl_ctrlval
= sign_extend32((((u32
)data
[0] & 0x1F) << 16) |
1080 (((u32
)data
[1] & 0xFF) << 8) |
1081 ((u32
)data
[2] & 0xFF), 20);
1082 temp_div
= (is_hs_mode
? 1048576 : 1572864);
1083 if (cfrl_ctrlval
> 0) {
1084 temp_q
= div_s64_rem(97375LL * cfrl_ctrlval
,
1087 temp_q
= div_s64_rem(-97375LL * cfrl_ctrlval
,
1090 if (temp_r
>= temp_div
/ 2)
1092 if (cfrl_ctrlval
> 0)
1098 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv
*priv
,
1099 u32 bandwidth
, int *offset
)
1103 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1104 if (priv
->state
!= STATE_ACTIVE_TC
) {
1105 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
1106 __func__
, priv
->state
);
1109 if (priv
->system
!= SYS_DVBT
) {
1110 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid delivery system %d\n",
1111 __func__
, priv
->system
);
1114 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
1115 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x4c, data
, sizeof(data
));
1116 *offset
= -1 * sign_extend32(
1117 ((u32
)(data
[0] & 0x1F) << 24) | ((u32
)data
[1] << 16) |
1118 ((u32
)data
[2] << 8) | (u32
)data
[3], 29);
1122 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv
*priv
,
1123 u32 bandwidth
, int *offset
)
1127 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1128 if (priv
->state
!= STATE_ACTIVE_TC
) {
1129 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
1130 __func__
, priv
->state
);
1133 if (priv
->system
!= SYS_DVBT2
) {
1134 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid delivery system %d\n",
1135 __func__
, priv
->system
);
1138 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x20);
1139 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x4c, data
, sizeof(data
));
1140 *offset
= -1 * sign_extend32(
1141 ((u32
)(data
[0] & 0x0F) << 24) | ((u32
)data
[1] << 16) |
1142 ((u32
)data
[2] << 8) | (u32
)data
[3], 27);
1143 switch (bandwidth
) {
1151 *offset
*= (bandwidth
/ 1000000);
1155 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid bandwidth %d\n",
1156 __func__
, bandwidth
);
1162 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv
*priv
,
1167 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1168 if (priv
->state
!= STATE_ACTIVE_TC
) {
1169 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
1170 __func__
, priv
->state
);
1173 if (priv
->system
!= SYS_DVBC_ANNEX_A
) {
1174 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid delivery system %d\n",
1175 __func__
, priv
->system
);
1178 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x40);
1179 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x15, data
, sizeof(data
));
1180 *offset
= div_s64(41000LL * sign_extend32((((u32
)data
[0] & 0x3f) << 8)
1181 | (u32
)data
[1], 13), 16384);
1185 static int cxd2841er_read_packet_errors_t(
1186 struct cxd2841er_priv
*priv
, u32
*penum
)
1191 if (priv
->state
!= STATE_ACTIVE_TC
) {
1192 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
1193 __func__
, priv
->state
);
1196 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
1197 cxd2841er_read_regs(priv
, I2C_SLVT
, 0xea, data
, sizeof(data
));
1199 *penum
= ((u32
)data
[0] << 8) | (u32
)data
[1];
1203 static int cxd2841er_read_packet_errors_t2(
1204 struct cxd2841er_priv
*priv
, u32
*penum
)
1209 if (priv
->state
!= STATE_ACTIVE_TC
) {
1210 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
1211 __func__
, priv
->state
);
1214 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x24);
1215 cxd2841er_read_regs(priv
, I2C_SLVT
, 0xfd, data
, sizeof(data
));
1217 *penum
= ((u32
)data
[1] << 8) | (u32
)data
[2];
1221 static int cxd2841er_read_packet_errors_i(
1222 struct cxd2841er_priv
*priv
, u32
*penum
)
1227 if (priv
->state
!= STATE_ACTIVE_TC
) {
1228 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
1229 __func__
, priv
->state
);
1232 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x60);
1233 cxd2841er_read_regs(priv
, I2C_SLVT
, 0xA1, data
, 1);
1235 if (!(data
[0] & 0x01))
1239 cxd2841er_read_regs(priv
, I2C_SLVT
, 0xA2, data
, sizeof(data
));
1240 *penum
= ((u32
)data
[0] << 8) | (u32
)data
[1];
1243 cxd2841er_read_regs(priv
, I2C_SLVT
, 0xA4, data
, sizeof(data
));
1244 *penum
+= ((u32
)data
[0] << 8) | (u32
)data
[1];
1247 cxd2841er_read_regs(priv
, I2C_SLVT
, 0xA6, data
, sizeof(data
));
1248 *penum
+= ((u32
)data
[0] << 8) | (u32
)data
[1];
1253 static u32
cxd2841er_mon_read_ber_s(struct cxd2841er_priv
*priv
)
1256 u32 bit_error
, bit_count
;
1259 /* Set SLV-T Bank : 0xA0 */
1260 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa0);
1262 * slave Bank Addr Bit Signal name
1263 * <SLV-T> A0h 35h [0] IFVBER_VALID
1264 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1265 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1266 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1267 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1268 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1269 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1271 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x35, data
, 11);
1272 if (data
[0] & 0x01) {
1273 bit_error
= ((u32
)(data
[1] & 0x3F) << 16) |
1274 ((u32
)(data
[2] & 0xFF) << 8) |
1275 (u32
)(data
[3] & 0xFF);
1276 bit_count
= ((u32
)(data
[8] & 0x3F) << 16) |
1277 ((u32
)(data
[9] & 0xFF) << 8) |
1278 (u32
)(data
[10] & 0xFF);
1280 * BER = bitError / bitCount
1281 * = (bitError * 10^7) / bitCount
1282 * = ((bitError * 625 * 125 * 128) / bitCount
1284 if ((bit_count
== 0) || (bit_error
> bit_count
)) {
1285 dev_dbg(&priv
->i2c
->dev
,
1286 "%s(): invalid bit_error %d, bit_count %d\n",
1287 __func__
, bit_error
, bit_count
);
1290 temp_q
= div_u64_rem(10000000ULL * bit_error
,
1291 bit_count
, &temp_r
);
1292 if (bit_count
!= 1 && temp_r
>= bit_count
/ 2)
1296 dev_dbg(&priv
->i2c
->dev
, "%s(): no data available\n", __func__
);
1301 static u32
cxd2841er_mon_read_ber_s2(struct cxd2841er_priv
*priv
)
1304 u32 bit_error
, period
;
1308 /* Set SLV-T Bank : 0xB2 */
1309 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xb2);
1311 * slave Bank Addr Bit Signal name
1312 * <SLV-T> B2h 30h [0] IFLBER_VALID
1313 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1314 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1315 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1316 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1318 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x30, data
, 5);
1319 if (data
[0] & 0x01) {
1320 /* Bit error count */
1321 bit_error
= ((u32
)(data
[1] & 0x0F) << 24) |
1322 ((u32
)(data
[2] & 0xFF) << 16) |
1323 ((u32
)(data
[3] & 0xFF) << 8) |
1324 (u32
)(data
[4] & 0xFF);
1326 /* Set SLV-T Bank : 0xA0 */
1327 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa0);
1328 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x7a, data
);
1329 /* Measurement period */
1330 period
= (u32
)(1 << (data
[0] & 0x0F));
1332 dev_dbg(&priv
->i2c
->dev
,
1333 "%s(): period is 0\n", __func__
);
1336 if (bit_error
> (period
* 64800)) {
1337 dev_dbg(&priv
->i2c
->dev
,
1338 "%s(): invalid bit_err 0x%x period 0x%x\n",
1339 __func__
, bit_error
, period
);
1343 * BER = bitError / (period * 64800)
1344 * = (bitError * 10^7) / (period * 64800)
1345 * = (bitError * 10^5) / (period * 648)
1346 * = (bitError * 12500) / (period * 81)
1347 * = (bitError * 10) * 1250 / (period * 81)
1349 temp_q
= div_u64_rem(12500ULL * bit_error
,
1350 period
* 81, &temp_r
);
1351 if (temp_r
>= period
* 40)
1355 dev_dbg(&priv
->i2c
->dev
,
1356 "%s(): no data available\n", __func__
);
1361 static int cxd2841er_read_ber_t2(struct cxd2841er_priv
*priv
, u32
*ber
)
1365 u32 bit_err
, period_exp
, n_ldpc
;
1368 if (priv
->state
!= STATE_ACTIVE_TC
) {
1369 dev_dbg(&priv
->i2c
->dev
,
1370 "%s(): invalid state %d\n", __func__
, priv
->state
);
1373 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x20);
1374 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x39, data
, sizeof(data
));
1375 if (!(data
[0] & 0x10)) {
1376 dev_dbg(&priv
->i2c
->dev
,
1377 "%s(): no valid BER data\n", __func__
);
1380 bit_err
= ((u32
)(data
[0] & 0x0f) << 24) |
1381 ((u32
)data
[1] << 16) |
1382 ((u32
)data
[2] << 8) |
1384 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x6f, data
);
1385 period_exp
= data
[0] & 0x0f;
1386 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x22);
1387 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x5e, data
);
1388 n_ldpc
= ((data
[0] & 0x03) == 0 ? 16200 : 64800);
1389 if (bit_err
> ((1U << period_exp
) * n_ldpc
)) {
1390 dev_dbg(&priv
->i2c
->dev
,
1391 "%s(): invalid BER value\n", __func__
);
1394 if (period_exp
>= 4) {
1395 div
= (1U << (period_exp
- 4)) * (n_ldpc
/ 200);
1396 q
= div_u64_rem(3125ULL * bit_err
, div
, &r
);
1398 div
= (1U << period_exp
) * (n_ldpc
/ 200);
1399 q
= div_u64_rem(50000ULL * bit_err
, div
, &r
);
1401 *ber
= (r
>= div
/ 2) ? q
+ 1 : q
;
1405 static int cxd2841er_read_ber_t(struct cxd2841er_priv
*priv
, u32
*ber
)
1409 u32 bit_err
, period
;
1412 if (priv
->state
!= STATE_ACTIVE_TC
) {
1413 dev_dbg(&priv
->i2c
->dev
,
1414 "%s(): invalid state %d\n", __func__
, priv
->state
);
1417 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
1418 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x39, data
);
1419 if (!(data
[0] & 0x01)) {
1420 dev_dbg(&priv
->i2c
->dev
,
1421 "%s(): no valid BER data\n", __func__
);
1424 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x22, data
, sizeof(data
));
1425 bit_err
= ((u32
)data
[0] << 8) | (u32
)data
[1];
1426 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x6f, data
);
1427 period
= ((data
[0] & 0x07) == 0) ? 256 : (4096 << (data
[0] & 0x07));
1429 q
= div_u64_rem(78125ULL * bit_err
, div
, &r
);
1430 *ber
= (r
>= div
/ 2) ? q
+ 1 : q
;
1434 static u32
cxd2841er_dvbs_read_snr(struct cxd2841er_priv
*priv
, u8 delsys
)
1438 int min_index
, max_index
, index
;
1439 static const struct cxd2841er_cnr_data
*cn_data
;
1441 /* Set SLV-T Bank : 0xA1 */
1442 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa1);
1444 * slave Bank Addr Bit Signal name
1445 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1446 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1447 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1449 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x10, data
, 3);
1450 if (data
[0] & 0x01) {
1451 value
= ((u32
)(data
[1] & 0x1F) << 8) | (u32
)(data
[2] & 0xFF);
1453 if (delsys
== SYS_DVBS
) {
1454 cn_data
= s_cn_data
;
1455 max_index
= sizeof(s_cn_data
) /
1456 sizeof(s_cn_data
[0]) - 1;
1458 cn_data
= s2_cn_data
;
1459 max_index
= sizeof(s2_cn_data
) /
1460 sizeof(s2_cn_data
[0]) - 1;
1462 if (value
>= cn_data
[min_index
].value
) {
1463 res
= cn_data
[min_index
].cnr_x1000
;
1466 if (value
<= cn_data
[max_index
].value
) {
1467 res
= cn_data
[max_index
].cnr_x1000
;
1470 while ((max_index
- min_index
) > 1) {
1471 index
= (max_index
+ min_index
) / 2;
1472 if (value
== cn_data
[index
].value
) {
1473 res
= cn_data
[index
].cnr_x1000
;
1475 } else if (value
> cn_data
[index
].value
)
1479 if ((max_index
- min_index
) <= 1) {
1480 if (value
== cn_data
[max_index
].value
) {
1481 res
= cn_data
[max_index
].cnr_x1000
;
1484 res
= cn_data
[min_index
].cnr_x1000
;
1490 dev_dbg(&priv
->i2c
->dev
,
1491 "%s(): no data available\n", __func__
);
1497 static int cxd2841er_read_snr_t(struct cxd2841er_priv
*priv
, u32
*snr
)
1503 if (priv
->state
!= STATE_ACTIVE_TC
) {
1504 dev_dbg(&priv
->i2c
->dev
,
1505 "%s(): invalid state %d\n", __func__
, priv
->state
);
1508 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
1509 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x28, data
, sizeof(data
));
1510 reg
= ((u32
)data
[0] << 8) | (u32
)data
[1];
1512 dev_dbg(&priv
->i2c
->dev
,
1513 "%s(): reg value out of range\n", __func__
);
1518 *snr
= 10000 * ((intlog10(reg
) - intlog10(5350 - reg
)) >> 24) + 28500;
1522 static int cxd2841er_read_snr_t2(struct cxd2841er_priv
*priv
, u32
*snr
)
1528 if (priv
->state
!= STATE_ACTIVE_TC
) {
1529 dev_dbg(&priv
->i2c
->dev
,
1530 "%s(): invalid state %d\n", __func__
, priv
->state
);
1533 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x20);
1534 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x28, data
, sizeof(data
));
1535 reg
= ((u32
)data
[0] << 8) | (u32
)data
[1];
1537 dev_dbg(&priv
->i2c
->dev
,
1538 "%s(): reg value out of range\n", __func__
);
1543 *snr
= 10000 * ((intlog10(reg
) -
1544 intlog10(12600 - reg
)) >> 24) + 32000;
1548 static int cxd2841er_read_snr_i(struct cxd2841er_priv
*priv
, u32
*snr
)
1554 if (priv
->state
!= STATE_ACTIVE_TC
) {
1555 dev_dbg(&priv
->i2c
->dev
,
1556 "%s(): invalid state %d\n", __func__
,
1561 /* Freeze all registers */
1562 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x01, 0x01);
1565 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x60);
1566 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x28, data
, sizeof(data
));
1567 reg
= ((u32
)data
[0] << 8) | (u32
)data
[1];
1569 dev_dbg(&priv
->i2c
->dev
,
1570 "%s(): reg value out of range\n", __func__
);
1575 *snr
= 100 * intlog10(reg
) - 9031;
1579 static u16
cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv
*priv
,
1584 cxd2841er_write_reg(
1585 priv
, I2C_SLVT
, 0x00, (delsys
== SYS_DVBT
? 0x10 : 0x20));
1586 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x26, data
, 2);
1587 dev_dbg(&priv
->i2c
->dev
,
1588 "%s(): AGC value=%u\n",
1589 __func__
, (((u16
)data
[0] & 0x0F) << 8) |
1590 (u16
)(data
[1] & 0xFF));
1591 return ((((u16
)data
[0] & 0x0F) << 8) | (u16
)(data
[1] & 0xFF)) << 4;
1594 static u16
cxd2841er_read_agc_gain_i(struct cxd2841er_priv
*priv
,
1599 cxd2841er_write_reg(
1600 priv
, I2C_SLVT
, 0x00, 0x60);
1601 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x26, data
, 2);
1603 dev_dbg(&priv
->i2c
->dev
,
1604 "%s(): AGC value=%u\n",
1605 __func__
, (((u16
)data
[0] & 0x0F) << 8) |
1606 (u16
)(data
[1] & 0xFF));
1607 return ((((u16
)data
[0] & 0x0F) << 8) | (u16
)(data
[1] & 0xFF)) << 4;
1610 static u16
cxd2841er_read_agc_gain_s(struct cxd2841er_priv
*priv
)
1614 /* Set SLV-T Bank : 0xA0 */
1615 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa0);
1617 * slave Bank Addr Bit Signal name
1618 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1619 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1621 cxd2841er_read_regs(priv
, I2C_SLVT
, 0x1f, data
, 2);
1622 return ((((u16
)data
[0] & 0x1F) << 8) | (u16
)(data
[1] & 0xFF)) << 3;
1625 static int cxd2841er_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
1627 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
1628 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
1630 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1632 switch (p
->delivery_system
) {
1634 *ber
= cxd2841er_mon_read_ber_s(priv
);
1637 *ber
= cxd2841er_mon_read_ber_s2(priv
);
1640 return cxd2841er_read_ber_t(priv
, ber
);
1642 return cxd2841er_read_ber_t2(priv
, ber
);
1650 static int cxd2841er_read_signal_strength(struct dvb_frontend
*fe
,
1653 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
1654 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
1656 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1657 switch (p
->delivery_system
) {
1660 *strength
= 65535 - cxd2841er_read_agc_gain_t_t2(
1661 priv
, p
->delivery_system
);
1664 *strength
= 65535 - cxd2841er_read_agc_gain_i(
1665 priv
, p
->delivery_system
);
1669 *strength
= 65535 - cxd2841er_read_agc_gain_s(priv
);
1678 static int cxd2841er_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
1681 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
1682 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
1684 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1685 switch (p
->delivery_system
) {
1687 cxd2841er_read_snr_t(priv
, &tmp
);
1690 cxd2841er_read_snr_t2(priv
, &tmp
);
1693 cxd2841er_read_snr_i(priv
, &tmp
);
1697 tmp
= cxd2841er_dvbs_read_snr(priv
, p
->delivery_system
);
1700 dev_dbg(&priv
->i2c
->dev
, "%s(): unknown delivery system %d\n",
1701 __func__
, p
->delivery_system
);
1704 *snr
= tmp
& 0xffff;
1708 static int cxd2841er_read_ucblocks(struct dvb_frontend
*fe
, u32
*ucblocks
)
1710 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
1711 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
1713 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1714 switch (p
->delivery_system
) {
1716 cxd2841er_read_packet_errors_t(priv
, ucblocks
);
1719 cxd2841er_read_packet_errors_t2(priv
, ucblocks
);
1722 cxd2841er_read_packet_errors_i(priv
, ucblocks
);
1728 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1732 static int cxd2841er_dvbt2_set_profile(
1733 struct cxd2841er_priv
*priv
, enum cxd2841er_dvbt2_profile_t profile
)
1738 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1740 case DVBT2_PROFILE_BASE
:
1742 seq_not2d_time
= 12;
1744 case DVBT2_PROFILE_LITE
:
1746 seq_not2d_time
= 40;
1748 case DVBT2_PROFILE_ANY
:
1750 seq_not2d_time
= 40;
1755 /* Set SLV-T Bank : 0x2E */
1756 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x2e);
1757 /* Set profile and tune mode */
1758 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x10, tune_mode
, 0x07);
1759 /* Set SLV-T Bank : 0x2B */
1760 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x2b);
1761 /* Set early unlock detection time */
1762 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x9d, seq_not2d_time
);
1766 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv
*priv
,
1767 u8 is_auto
, u8 plp_id
)
1770 dev_dbg(&priv
->i2c
->dev
,
1771 "%s() using auto PLP selection\n", __func__
);
1773 dev_dbg(&priv
->i2c
->dev
,
1774 "%s() using manual PLP selection, ID %d\n",
1777 /* Set SLV-T Bank : 0x23 */
1778 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x23);
1780 /* Manual PLP selection mode. Set the data PLP Id. */
1781 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xaf, plp_id
);
1783 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1784 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xad, (is_auto
? 0x00 : 0x01));
1788 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv
*priv
,
1797 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
1798 switch (bandwidth
) {
1800 /* bank 0x20, reg 0x9f */
1806 /* bank 0x10, reg 0xa6 */
1821 iffreq
= MAKE_IFFREQ_CONFIG(4.80);
1825 /* bank 0x20, reg 0x9f */
1831 /* bank 0x10, reg 0xa6 */
1846 iffreq
= MAKE_IFFREQ_CONFIG(4.2);
1850 /* bank 0x20, reg 0x9f */
1856 /* bank 0x10, reg 0xa6 */
1871 iffreq
= MAKE_IFFREQ_CONFIG(3.6);
1875 /* bank 0x20, reg 0x9f */
1881 /* bank 0x10, reg 0xa6 */
1896 iffreq
= MAKE_IFFREQ_CONFIG(3.6);
1900 /* bank 0x20, reg 0x9f */
1906 /* bank 0x10, reg 0xa6 */
1921 iffreq
= MAKE_IFFREQ_CONFIG(3.5);
1927 /* Set SLV-T Bank : 0x20 */
1928 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x20);
1929 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x9f, b20_9f
, sizeof(b20_9f
));
1930 /* Set SLV-T Bank : 0x27 */
1931 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x27);
1932 cxd2841er_set_reg_bits(
1933 priv
, I2C_SLVT
, 0x7a,
1934 (bandwidth
== 1712000 ? 0x03 : 0x00), 0x0f);
1935 /* Set SLV-T Bank : 0x10 */
1936 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
1937 /* Group delay equaliser sett. for ASCOT2E */
1938 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xa6, b10_a6
, sizeof(b10_a6
));
1939 /* <IF freq setting> */
1940 b10_b6
[0] = (u8
) ((iffreq
>> 16) & 0xff);
1941 b10_b6
[1] = (u8
)((iffreq
>> 8) & 0xff);
1942 b10_b6
[2] = (u8
)(iffreq
& 0xff);
1943 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xb6, b10_b6
, sizeof(b10_b6
));
1944 /* System bandwidth setting */
1945 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xd7, b10_d7
, 0x07);
1949 static int cxd2841er_sleep_tc_to_active_t_band(
1950 struct cxd2841er_priv
*priv
, u32 bandwidth
)
1952 u8 data
[MAX_WRITE_REGSIZE
];
1954 u8 nominalRate8bw
[3][5] = {
1955 /* TRCG Nominal Rate [37:0] */
1956 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1957 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1958 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1960 u8 nominalRate7bw
[3][5] = {
1961 /* TRCG Nominal Rate [37:0] */
1962 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1963 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1964 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1966 u8 nominalRate6bw
[3][5] = {
1967 /* TRCG Nominal Rate [37:0] */
1968 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1969 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1970 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1972 u8 nominalRate5bw
[3][5] = {
1973 /* TRCG Nominal Rate [37:0] */
1974 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1975 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1976 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1979 u8 itbCoef8bw
[3][14] = {
1980 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1981 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1982 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
1983 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1984 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1985 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1987 u8 itbCoef7bw
[3][14] = {
1988 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1989 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1990 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
1991 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1992 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1993 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1995 u8 itbCoef6bw
[3][14] = {
1996 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
1997 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1998 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
1999 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2000 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2001 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2003 u8 itbCoef5bw
[3][14] = {
2004 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2005 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2006 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2007 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2008 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2009 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2012 /* Set SLV-T Bank : 0x13 */
2013 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x13);
2014 /* Echo performance optimization setting */
2017 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x9C, data
, 2);
2019 /* Set SLV-T Bank : 0x10 */
2020 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2022 switch (bandwidth
) {
2024 /* <Timing Recovery setting> */
2025 cxd2841er_write_regs(priv
, I2C_SLVT
,
2026 0x9F, nominalRate8bw
[priv
->xtal
], 5);
2027 /* Group delay equaliser settings for
2028 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2030 cxd2841er_write_regs(priv
, I2C_SLVT
,
2031 0xA6, itbCoef8bw
[priv
->xtal
], 14);
2032 /* <IF freq setting> */
2033 iffreq
= MAKE_IFFREQ_CONFIG_XTAL(priv
->xtal
, 4.80);
2034 data
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2035 data
[1] = (u8
)((iffreq
>> 8) & 0xff);
2036 data
[2] = (u8
)(iffreq
& 0xff);
2037 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xB6, data
, 3);
2038 /* System bandwidth setting */
2039 cxd2841er_set_reg_bits(
2040 priv
, I2C_SLVT
, 0xD7, 0x00, 0x07);
2042 /* Demod core latency setting */
2043 if (priv
->xtal
== SONY_XTAL_24000
) {
2050 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xD9, data
, 2);
2052 /* Notch filter setting */
2055 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x17);
2056 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x38, data
, 2);
2059 /* <Timing Recovery setting> */
2060 cxd2841er_write_regs(priv
, I2C_SLVT
,
2061 0x9F, nominalRate7bw
[priv
->xtal
], 5);
2062 /* Group delay equaliser settings for
2063 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2065 cxd2841er_write_regs(priv
, I2C_SLVT
,
2066 0xA6, itbCoef7bw
[priv
->xtal
], 14);
2067 /* <IF freq setting> */
2068 iffreq
= MAKE_IFFREQ_CONFIG_XTAL(priv
->xtal
, 4.20);
2069 data
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2070 data
[1] = (u8
)((iffreq
>> 8) & 0xff);
2071 data
[2] = (u8
)(iffreq
& 0xff);
2072 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xB6, data
, 3);
2073 /* System bandwidth setting */
2074 cxd2841er_set_reg_bits(
2075 priv
, I2C_SLVT
, 0xD7, 0x02, 0x07);
2077 /* Demod core latency setting */
2078 if (priv
->xtal
== SONY_XTAL_24000
) {
2085 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xD9, data
, 2);
2087 /* Notch filter setting */
2090 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x17);
2091 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x38, data
, 2);
2094 /* <Timing Recovery setting> */
2095 cxd2841er_write_regs(priv
, I2C_SLVT
,
2096 0x9F, nominalRate6bw
[priv
->xtal
], 5);
2097 /* Group delay equaliser settings for
2098 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2100 cxd2841er_write_regs(priv
, I2C_SLVT
,
2101 0xA6, itbCoef6bw
[priv
->xtal
], 14);
2102 /* <IF freq setting> */
2103 iffreq
= MAKE_IFFREQ_CONFIG_XTAL(priv
->xtal
, 3.60);
2104 data
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2105 data
[1] = (u8
)((iffreq
>> 8) & 0xff);
2106 data
[2] = (u8
)(iffreq
& 0xff);
2107 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xB6, data
, 3);
2108 /* System bandwidth setting */
2109 cxd2841er_set_reg_bits(
2110 priv
, I2C_SLVT
, 0xD7, 0x04, 0x07);
2112 /* Demod core latency setting */
2113 if (priv
->xtal
== SONY_XTAL_24000
) {
2120 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xD9, data
, 2);
2122 /* Notch filter setting */
2125 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x17);
2126 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x38, data
, 2);
2129 /* <Timing Recovery setting> */
2130 cxd2841er_write_regs(priv
, I2C_SLVT
,
2131 0x9F, nominalRate5bw
[priv
->xtal
], 5);
2132 /* Group delay equaliser settings for
2133 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2135 cxd2841er_write_regs(priv
, I2C_SLVT
,
2136 0xA6, itbCoef5bw
[priv
->xtal
], 14);
2137 /* <IF freq setting> */
2138 iffreq
= MAKE_IFFREQ_CONFIG_XTAL(priv
->xtal
, 3.60);
2139 data
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2140 data
[1] = (u8
)((iffreq
>> 8) & 0xff);
2141 data
[2] = (u8
)(iffreq
& 0xff);
2142 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xB6, data
, 3);
2143 /* System bandwidth setting */
2144 cxd2841er_set_reg_bits(
2145 priv
, I2C_SLVT
, 0xD7, 0x06, 0x07);
2147 /* Demod core latency setting */
2148 if (priv
->xtal
== SONY_XTAL_24000
) {
2155 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xD9, data
, 2);
2157 /* Notch filter setting */
2160 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x17);
2161 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x38, data
, 2);
2168 static int cxd2841er_sleep_tc_to_active_i_band(
2169 struct cxd2841er_priv
*priv
, u32 bandwidth
)
2174 /* TRCG Nominal Rate */
2175 u8 nominalRate8bw
[3][5] = {
2176 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2177 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2178 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2181 u8 nominalRate7bw
[3][5] = {
2182 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2183 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2184 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2187 u8 nominalRate6bw
[3][5] = {
2188 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2189 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2190 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2193 u8 itbCoef8bw
[3][14] = {
2194 {0x00}, /* 20.5MHz XTal */
2195 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2196 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2197 {0x0}, /* 41MHz XTal */
2200 u8 itbCoef7bw
[3][14] = {
2201 {0x00}, /* 20.5MHz XTal */
2202 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2203 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2204 {0x00}, /* 41MHz XTal */
2207 u8 itbCoef6bw
[3][14] = {
2208 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2209 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2210 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2211 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2212 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2213 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2216 dev_dbg(&priv
->i2c
->dev
, "%s() bandwidth=%u\n", __func__
, bandwidth
);
2217 /* Set SLV-T Bank : 0x10 */
2218 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2220 /* 20.5/41MHz Xtal support is not available
2221 * on ISDB-T 7MHzBW and 8MHzBW
2223 if (priv
->xtal
!= SONY_XTAL_24000
&& bandwidth
> 6000000) {
2224 dev_err(&priv
->i2c
->dev
,
2225 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2226 __func__
, bandwidth
);
2230 switch (bandwidth
) {
2232 /* TRCG Nominal Rate */
2233 cxd2841er_write_regs(priv
, I2C_SLVT
,
2234 0x9F, nominalRate8bw
[priv
->xtal
], 5);
2235 /* Group delay equaliser settings for ASCOT tuners optimized */
2236 cxd2841er_write_regs(priv
, I2C_SLVT
,
2237 0xA6, itbCoef8bw
[priv
->xtal
], 14);
2239 /* IF freq setting */
2240 iffreq
= MAKE_IFFREQ_CONFIG_XTAL(priv
->xtal
, 4.75);
2241 data
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2242 data
[1] = (u8
)((iffreq
>> 8) & 0xff);
2243 data
[2] = (u8
)(iffreq
& 0xff);
2244 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xB6, data
, 3);
2246 /* System bandwidth setting */
2247 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xd7, 0x0, 0x7);
2249 /* Demod core latency setting */
2252 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xD9, data
, 2);
2254 /* Acquisition optimization setting */
2255 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x12);
2256 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x71, 0x03, 0x07);
2257 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x15);
2258 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xBE, 0x03);
2261 /* TRCG Nominal Rate */
2262 cxd2841er_write_regs(priv
, I2C_SLVT
,
2263 0x9F, nominalRate7bw
[priv
->xtal
], 5);
2264 /* Group delay equaliser settings for ASCOT tuners optimized */
2265 cxd2841er_write_regs(priv
, I2C_SLVT
,
2266 0xA6, itbCoef7bw
[priv
->xtal
], 14);
2268 /* IF freq setting */
2269 iffreq
= MAKE_IFFREQ_CONFIG_XTAL(priv
->xtal
, 4.15);
2270 data
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2271 data
[1] = (u8
)((iffreq
>> 8) & 0xff);
2272 data
[2] = (u8
)(iffreq
& 0xff);
2273 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xB6, data
, 3);
2275 /* System bandwidth setting */
2276 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xd7, 0x02, 0x7);
2278 /* Demod core latency setting */
2281 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xD9, data
, 2);
2283 /* Acquisition optimization setting */
2284 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x12);
2285 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x71, 0x03, 0x07);
2286 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x15);
2287 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xBE, 0x02);
2290 /* TRCG Nominal Rate */
2291 cxd2841er_write_regs(priv
, I2C_SLVT
,
2292 0x9F, nominalRate6bw
[priv
->xtal
], 5);
2293 /* Group delay equaliser settings for ASCOT tuners optimized */
2294 cxd2841er_write_regs(priv
, I2C_SLVT
,
2295 0xA6, itbCoef6bw
[priv
->xtal
], 14);
2297 /* IF freq setting */
2298 iffreq
= MAKE_IFFREQ_CONFIG_XTAL(priv
->xtal
, 3.55);
2299 data
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2300 data
[1] = (u8
)((iffreq
>> 8) & 0xff);
2301 data
[2] = (u8
)(iffreq
& 0xff);
2302 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xB6, data
, 3);
2304 /* System bandwidth setting */
2305 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xd7, 0x04, 0x7);
2307 /* Demod core latency setting */
2308 if (priv
->xtal
== SONY_XTAL_24000
) {
2315 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xD9, data
, 2);
2317 /* Acquisition optimization setting */
2318 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x12);
2319 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x71, 0x07, 0x07);
2320 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x15);
2321 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xBE, 0x02);
2324 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid bandwidth %d\n",
2325 __func__
, bandwidth
);
2331 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv
*priv
,
2334 u8 bw7_8mhz_b10_a6
[] = {
2335 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2336 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2337 u8 bw6mhz_b10_a6
[] = {
2338 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2339 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2343 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2344 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2345 switch (bandwidth
) {
2348 cxd2841er_write_regs(
2349 priv
, I2C_SLVT
, 0xa6,
2350 bw7_8mhz_b10_a6
, sizeof(bw7_8mhz_b10_a6
));
2351 iffreq
= MAKE_IFFREQ_CONFIG(4.9);
2354 cxd2841er_write_regs(
2355 priv
, I2C_SLVT
, 0xa6,
2356 bw6mhz_b10_a6
, sizeof(bw6mhz_b10_a6
));
2357 iffreq
= MAKE_IFFREQ_CONFIG(3.7);
2360 dev_dbg(&priv
->i2c
->dev
, "%s(): unsupported bandwidth %d\n",
2361 __func__
, bandwidth
);
2364 /* <IF freq setting> */
2365 b10_b6
[0] = (u8
) ((iffreq
>> 16) & 0xff);
2366 b10_b6
[1] = (u8
)((iffreq
>> 8) & 0xff);
2367 b10_b6
[2] = (u8
)(iffreq
& 0xff);
2368 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xb6, b10_b6
, sizeof(b10_b6
));
2369 /* Set SLV-T Bank : 0x11 */
2370 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x11);
2371 switch (bandwidth
) {
2374 cxd2841er_set_reg_bits(
2375 priv
, I2C_SLVT
, 0xa3, 0x00, 0x1f);
2378 cxd2841er_set_reg_bits(
2379 priv
, I2C_SLVT
, 0xa3, 0x14, 0x1f);
2382 /* Set SLV-T Bank : 0x40 */
2383 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x40);
2384 switch (bandwidth
) {
2386 cxd2841er_set_reg_bits(
2387 priv
, I2C_SLVT
, 0x26, 0x0b, 0x0f);
2388 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x27, 0x3e);
2391 cxd2841er_set_reg_bits(
2392 priv
, I2C_SLVT
, 0x26, 0x09, 0x0f);
2393 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x27, 0xd6);
2396 cxd2841er_set_reg_bits(
2397 priv
, I2C_SLVT
, 0x26, 0x08, 0x0f);
2398 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x27, 0x6e);
2404 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv
*priv
,
2407 u8 data
[2] = { 0x09, 0x54 };
2408 u8 data24m
[3] = {0xDC, 0x6C, 0x00};
2410 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2411 cxd2841er_set_ts_clock_mode(priv
, SYS_DVBT
);
2412 /* Set SLV-X Bank : 0x00 */
2413 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
2414 /* Set demod mode */
2415 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, 0x01);
2416 /* Set SLV-T Bank : 0x00 */
2417 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2418 /* Enable demod clock */
2419 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x01);
2420 /* Disable RF level monitor */
2421 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x00);
2422 /* Enable ADC clock */
2423 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
2425 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x1a);
2426 /* Enable ADC 2 & 3 */
2427 if (priv
->xtal
== SONY_XTAL_41000
) {
2431 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x43, data
, 2);
2433 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x00);
2434 /* Set SLV-T Bank : 0x10 */
2435 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2436 /* IFAGC gain settings */
2437 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xd2, 0x0c, 0x1f);
2438 /* Set SLV-T Bank : 0x11 */
2439 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x11);
2440 /* BBAGC TARGET level setting */
2441 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x6a, 0x50);
2442 /* Set SLV-T Bank : 0x10 */
2443 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2444 /* ASCOT setting ON */
2445 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xa5, 0x01, 0x01);
2446 /* Set SLV-T Bank : 0x18 */
2447 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x18);
2448 /* Pre-RS BER moniter setting */
2449 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x36, 0x40, 0x07);
2450 /* FEC Auto Recovery setting */
2451 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x30, 0x01, 0x01);
2452 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x31, 0x01, 0x01);
2453 /* Set SLV-T Bank : 0x00 */
2454 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2456 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xce, 0x01, 0x01);
2457 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xcf, 0x01, 0x01);
2459 if (priv
->xtal
== SONY_XTAL_24000
) {
2460 /* Set SLV-T Bank : 0x10 */
2461 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2462 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xBF, 0x60);
2463 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x18);
2464 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x24, data24m
, 3);
2467 cxd2841er_sleep_tc_to_active_t_band(priv
, bandwidth
);
2468 /* Set SLV-T Bank : 0x00 */
2469 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2470 /* Disable HiZ Setting 1 */
2471 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x28);
2472 /* Disable HiZ Setting 2 */
2473 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0x00);
2474 priv
->state
= STATE_ACTIVE_TC
;
2478 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv
*priv
,
2481 u8 data
[2] = { 0x09, 0x54 };
2483 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2484 cxd2841er_set_ts_clock_mode(priv
, SYS_DVBT2
);
2485 /* Set SLV-X Bank : 0x00 */
2486 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
2487 /* Set demod mode */
2488 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, 0x02);
2489 /* Set SLV-T Bank : 0x00 */
2490 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2491 /* Enable demod clock */
2492 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x01);
2493 /* Disable RF level monitor */
2494 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x00);
2495 /* Enable ADC clock */
2496 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
2498 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x1a);
2499 /* xtal freq 20.5MHz */
2500 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x43, data
, 2);
2502 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x00);
2503 /* Set SLV-T Bank : 0x10 */
2504 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2505 /* IFAGC gain settings */
2506 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xd2, 0x0c, 0x1f);
2507 /* Set SLV-T Bank : 0x11 */
2508 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x11);
2509 /* BBAGC TARGET level setting */
2510 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x6a, 0x50);
2511 /* Set SLV-T Bank : 0x10 */
2512 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2513 /* ASCOT setting ON */
2514 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xa5, 0x01, 0x01);
2515 /* Set SLV-T Bank : 0x20 */
2516 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x20);
2517 /* Acquisition optimization setting */
2518 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x8b, 0x3c);
2519 /* Set SLV-T Bank : 0x2b */
2520 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x2b);
2521 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x76, 0x20, 0x70);
2522 /* Set SLV-T Bank : 0x00 */
2523 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2525 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xce, 0x01, 0x01);
2526 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xcf, 0x01, 0x01);
2527 /* DVB-T2 initial setting */
2528 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x13);
2529 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x83, 0x10);
2530 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x86, 0x34);
2531 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x9e, 0x09, 0x0f);
2532 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x9f, 0xd8);
2533 /* Set SLV-T Bank : 0x2a */
2534 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x2a);
2535 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x38, 0x04, 0x0f);
2536 /* Set SLV-T Bank : 0x2b */
2537 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x2b);
2538 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x11, 0x20, 0x3f);
2540 cxd2841er_sleep_tc_to_active_t2_band(priv
, bandwidth
);
2542 /* Set SLV-T Bank : 0x00 */
2543 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2544 /* Disable HiZ Setting 1 */
2545 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x28);
2546 /* Disable HiZ Setting 2 */
2547 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0x00);
2548 priv
->state
= STATE_ACTIVE_TC
;
2553 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv
*priv
,
2556 u8 data
[2] = { 0x09, 0x54 };
2557 u8 data24m
[2] = {0x60, 0x00};
2558 u8 data24m2
[3] = {0xB7, 0x1B, 0x00};
2560 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2561 cxd2841er_set_ts_clock_mode(priv
, SYS_DVBT
);
2562 /* Set SLV-X Bank : 0x00 */
2563 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
2564 /* Set demod mode */
2565 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, 0x06);
2566 /* Set SLV-T Bank : 0x00 */
2567 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2568 /* Enable demod clock */
2569 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x01);
2570 /* Enable RF level monitor */
2571 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x01);
2572 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x59, 0x01);
2573 /* Enable ADC clock */
2574 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
2576 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x1a);
2577 /* xtal freq 20.5MHz or 24M */
2578 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x43, data
, 2);
2580 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x00);
2581 /* ASCOT setting ON */
2582 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xa5, 0x01, 0x01);
2583 /* FEC Auto Recovery setting */
2584 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x30, 0x01, 0x01);
2585 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x31, 0x00, 0x01);
2586 /* ISDB-T initial setting */
2587 /* Set SLV-T Bank : 0x00 */
2588 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2589 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xce, 0x00, 0x01);
2590 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xcf, 0x00, 0x01);
2591 /* Set SLV-T Bank : 0x10 */
2592 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2593 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x69, 0x04, 0x07);
2594 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x6B, 0x03, 0x07);
2595 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x9D, 0x50, 0xFF);
2596 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xD3, 0x06, 0x1F);
2597 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xED, 0x00, 0x01);
2598 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xE2, 0xCE, 0x80);
2599 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xF2, 0x13, 0x10);
2600 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xDE, 0x2E, 0x3F);
2601 /* Set SLV-T Bank : 0x15 */
2602 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x15);
2603 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xDE, 0x02, 0x03);
2604 /* Set SLV-T Bank : 0x1E */
2605 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x1E);
2606 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x73, 0x68, 0xFF);
2607 /* Set SLV-T Bank : 0x63 */
2608 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x63);
2609 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0x81, 0x00, 0x01);
2611 /* for xtal 24MHz */
2612 /* Set SLV-T Bank : 0x10 */
2613 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2614 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xBF, data24m
, 2);
2615 /* Set SLV-T Bank : 0x60 */
2616 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x60);
2617 cxd2841er_write_regs(priv
, I2C_SLVT
, 0xA8, data24m2
, 3);
2619 cxd2841er_sleep_tc_to_active_i_band(priv
, bandwidth
);
2620 /* Set SLV-T Bank : 0x00 */
2621 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2622 /* Disable HiZ Setting 1 */
2623 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x28);
2624 /* Disable HiZ Setting 2 */
2625 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0x00);
2626 priv
->state
= STATE_ACTIVE_TC
;
2630 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv
*priv
,
2633 u8 data
[2] = { 0x09, 0x54 };
2635 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2636 cxd2841er_set_ts_clock_mode(priv
, SYS_DVBC_ANNEX_A
);
2637 /* Set SLV-X Bank : 0x00 */
2638 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x00, 0x00);
2639 /* Set demod mode */
2640 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x17, 0x04);
2641 /* Set SLV-T Bank : 0x00 */
2642 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2643 /* Enable demod clock */
2644 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2c, 0x01);
2645 /* Disable RF level monitor */
2646 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x2f, 0x00);
2647 /* Enable ADC clock */
2648 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x30, 0x00);
2650 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x41, 0x1a);
2651 /* xtal freq 20.5MHz */
2652 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x43, data
, 2);
2654 cxd2841er_write_reg(priv
, I2C_SLVX
, 0x18, 0x00);
2655 /* Set SLV-T Bank : 0x10 */
2656 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2657 /* IFAGC gain settings */
2658 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xd2, 0x09, 0x1f);
2659 /* Set SLV-T Bank : 0x11 */
2660 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x11);
2661 /* BBAGC TARGET level setting */
2662 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x6a, 0x48);
2663 /* Set SLV-T Bank : 0x10 */
2664 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
2665 /* ASCOT setting ON */
2666 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xa5, 0x01, 0x01);
2667 /* Set SLV-T Bank : 0x40 */
2668 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x40);
2670 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xc3, 0x00, 0x04);
2671 /* Set SLV-T Bank : 0x00 */
2672 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2674 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xce, 0x01, 0x01);
2675 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xcf, 0x01, 0x01);
2677 cxd2841er_sleep_tc_to_active_c_band(priv
, 8000000);
2678 /* Set SLV-T Bank : 0x00 */
2679 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
2680 /* Disable HiZ Setting 1 */
2681 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x80, 0x28);
2682 /* Disable HiZ Setting 2 */
2683 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x81, 0x00);
2684 priv
->state
= STATE_ACTIVE_TC
;
2688 static int cxd2841er_get_frontend(struct dvb_frontend
*fe
,
2689 struct dtv_frontend_properties
*p
)
2691 enum fe_status status
= 0;
2692 u16 strength
= 0, snr
= 0;
2693 u32 errors
= 0, ber
= 0;
2694 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
2696 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2697 if (priv
->state
== STATE_ACTIVE_S
)
2698 cxd2841er_read_status_s(fe
, &status
);
2699 else if (priv
->state
== STATE_ACTIVE_TC
)
2700 cxd2841er_read_status_tc(fe
, &status
);
2702 if (status
& FE_HAS_LOCK
) {
2703 cxd2841er_read_signal_strength(fe
, &strength
);
2704 p
->strength
.len
= 1;
2705 p
->strength
.stat
[0].scale
= FE_SCALE_RELATIVE
;
2706 p
->strength
.stat
[0].uvalue
= strength
;
2707 cxd2841er_read_snr(fe
, &snr
);
2709 p
->cnr
.stat
[0].scale
= FE_SCALE_DECIBEL
;
2710 p
->cnr
.stat
[0].svalue
= snr
;
2711 cxd2841er_read_ucblocks(fe
, &errors
);
2712 p
->block_error
.len
= 1;
2713 p
->block_error
.stat
[0].scale
= FE_SCALE_COUNTER
;
2714 p
->block_error
.stat
[0].uvalue
= errors
;
2715 cxd2841er_read_ber(fe
, &ber
);
2716 p
->post_bit_error
.len
= 1;
2717 p
->post_bit_error
.stat
[0].scale
= FE_SCALE_COUNTER
;
2718 p
->post_bit_error
.stat
[0].uvalue
= ber
;
2720 p
->strength
.len
= 1;
2721 p
->strength
.stat
[0].scale
= FE_SCALE_NOT_AVAILABLE
;
2723 p
->cnr
.stat
[0].scale
= FE_SCALE_NOT_AVAILABLE
;
2724 p
->block_error
.len
= 1;
2725 p
->block_error
.stat
[0].scale
= FE_SCALE_NOT_AVAILABLE
;
2726 p
->post_bit_error
.len
= 1;
2727 p
->post_bit_error
.stat
[0].scale
= FE_SCALE_NOT_AVAILABLE
;
2732 static int cxd2841er_set_frontend_s(struct dvb_frontend
*fe
)
2734 int ret
= 0, i
, timeout
, carr_offset
;
2735 enum fe_status status
;
2736 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
2737 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
2738 u32 symbol_rate
= p
->symbol_rate
/1000;
2740 dev_dbg(&priv
->i2c
->dev
, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
2742 (p
->delivery_system
== SYS_DVBS
? "DVB-S" : "DVB-S2"),
2743 p
->frequency
, symbol_rate
, priv
->xtal
);
2744 switch (priv
->state
) {
2746 ret
= cxd2841er_sleep_s_to_active_s(
2747 priv
, p
->delivery_system
, symbol_rate
);
2749 case STATE_ACTIVE_S
:
2750 ret
= cxd2841er_retune_active(priv
, p
);
2753 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
2754 __func__
, priv
->state
);
2759 dev_dbg(&priv
->i2c
->dev
, "%s(): tune failed\n", __func__
);
2762 if (fe
->ops
.i2c_gate_ctrl
)
2763 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2764 if (fe
->ops
.tuner_ops
.set_params
)
2765 fe
->ops
.tuner_ops
.set_params(fe
);
2766 if (fe
->ops
.i2c_gate_ctrl
)
2767 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2768 cxd2841er_tune_done(priv
);
2769 timeout
= ((3000000 + (symbol_rate
- 1)) / symbol_rate
) + 150;
2770 for (i
= 0; i
< timeout
/ CXD2841ER_DVBS_POLLING_INVL
; i
++) {
2771 usleep_range(CXD2841ER_DVBS_POLLING_INVL
*1000,
2772 (CXD2841ER_DVBS_POLLING_INVL
+ 2) * 1000);
2773 cxd2841er_read_status_s(fe
, &status
);
2774 if (status
& FE_HAS_LOCK
)
2777 if (status
& FE_HAS_LOCK
) {
2778 if (cxd2841er_get_carrier_offset_s_s2(
2779 priv
, &carr_offset
)) {
2783 dev_dbg(&priv
->i2c
->dev
, "%s(): carrier_offset=%d\n",
2784 __func__
, carr_offset
);
2790 static int cxd2841er_set_frontend_tc(struct dvb_frontend
*fe
)
2792 int ret
= 0, timeout
;
2793 enum fe_status status
;
2794 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
2795 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
2797 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2798 if (p
->delivery_system
== SYS_DVBT
) {
2799 priv
->system
= SYS_DVBT
;
2800 switch (priv
->state
) {
2801 case STATE_SLEEP_TC
:
2802 ret
= cxd2841er_sleep_tc_to_active_t(
2803 priv
, p
->bandwidth_hz
);
2805 case STATE_ACTIVE_TC
:
2806 ret
= cxd2841er_retune_active(priv
, p
);
2809 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
2810 __func__
, priv
->state
);
2813 } else if (p
->delivery_system
== SYS_DVBT2
) {
2814 priv
->system
= SYS_DVBT2
;
2815 cxd2841er_dvbt2_set_plp_config(priv
,
2816 (int)(p
->stream_id
> 255), p
->stream_id
);
2817 cxd2841er_dvbt2_set_profile(priv
, DVBT2_PROFILE_BASE
);
2818 switch (priv
->state
) {
2819 case STATE_SLEEP_TC
:
2820 ret
= cxd2841er_sleep_tc_to_active_t2(priv
,
2823 case STATE_ACTIVE_TC
:
2824 ret
= cxd2841er_retune_active(priv
, p
);
2827 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
2828 __func__
, priv
->state
);
2831 } else if (p
->delivery_system
== SYS_ISDBT
) {
2832 priv
->system
= SYS_ISDBT
;
2833 switch (priv
->state
) {
2834 case STATE_SLEEP_TC
:
2835 ret
= cxd2841er_sleep_tc_to_active_i(
2836 priv
, p
->bandwidth_hz
);
2838 case STATE_ACTIVE_TC
:
2839 ret
= cxd2841er_retune_active(priv
, p
);
2842 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
2843 __func__
, priv
->state
);
2846 } else if (p
->delivery_system
== SYS_DVBC_ANNEX_A
||
2847 p
->delivery_system
== SYS_DVBC_ANNEX_C
) {
2848 priv
->system
= SYS_DVBC_ANNEX_A
;
2849 switch (priv
->state
) {
2850 case STATE_SLEEP_TC
:
2851 ret
= cxd2841er_sleep_tc_to_active_c(
2852 priv
, p
->bandwidth_hz
);
2854 case STATE_ACTIVE_TC
:
2855 ret
= cxd2841er_retune_active(priv
, p
);
2858 dev_dbg(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
2859 __func__
, priv
->state
);
2863 dev_dbg(&priv
->i2c
->dev
,
2864 "%s(): invalid delivery system %d\n",
2865 __func__
, p
->delivery_system
);
2870 if (fe
->ops
.i2c_gate_ctrl
)
2871 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2872 if (fe
->ops
.tuner_ops
.set_params
)
2873 fe
->ops
.tuner_ops
.set_params(fe
);
2874 if (fe
->ops
.i2c_gate_ctrl
)
2875 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2876 cxd2841er_tune_done(priv
);
2878 while (timeout
> 0) {
2879 ret
= cxd2841er_read_status_tc(fe
, &status
);
2882 if (status
& FE_HAS_LOCK
)
2888 dev_dbg(&priv
->i2c
->dev
,
2889 "%s(): LOCK wait timeout\n", __func__
);
2894 static int cxd2841er_tune_s(struct dvb_frontend
*fe
,
2896 unsigned int mode_flags
,
2897 unsigned int *delay
,
2898 enum fe_status
*status
)
2900 int ret
, carrier_offset
;
2901 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
2902 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
2904 dev_dbg(&priv
->i2c
->dev
, "%s() re_tune=%d\n", __func__
, re_tune
);
2906 ret
= cxd2841er_set_frontend_s(fe
);
2909 cxd2841er_read_status_s(fe
, status
);
2910 if (*status
& FE_HAS_LOCK
) {
2911 if (cxd2841er_get_carrier_offset_s_s2(
2912 priv
, &carrier_offset
))
2914 p
->frequency
+= carrier_offset
;
2915 ret
= cxd2841er_set_frontend_s(fe
);
2921 return cxd2841er_read_status_s(fe
, status
);
2924 static int cxd2841er_tune_tc(struct dvb_frontend
*fe
,
2926 unsigned int mode_flags
,
2927 unsigned int *delay
,
2928 enum fe_status
*status
)
2930 int ret
, carrier_offset
;
2931 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
2932 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
2934 dev_dbg(&priv
->i2c
->dev
, "%s(): re_tune %d\n", __func__
, re_tune
);
2936 ret
= cxd2841er_set_frontend_tc(fe
);
2939 cxd2841er_read_status_tc(fe
, status
);
2940 if (*status
& FE_HAS_LOCK
) {
2941 switch (priv
->system
) {
2943 ret
= cxd2841er_get_carrier_offset_t(
2944 priv
, p
->bandwidth_hz
,
2948 ret
= cxd2841er_get_carrier_offset_t2(
2949 priv
, p
->bandwidth_hz
,
2952 case SYS_DVBC_ANNEX_A
:
2953 ret
= cxd2841er_get_carrier_offset_c(
2954 priv
, &carrier_offset
);
2957 dev_dbg(&priv
->i2c
->dev
,
2958 "%s(): invalid delivery system %d\n",
2959 __func__
, priv
->system
);
2964 dev_dbg(&priv
->i2c
->dev
, "%s(): carrier offset %d\n",
2965 __func__
, carrier_offset
);
2966 p
->frequency
+= carrier_offset
;
2967 ret
= cxd2841er_set_frontend_tc(fe
);
2973 return cxd2841er_read_status_tc(fe
, status
);
2976 static int cxd2841er_sleep_s(struct dvb_frontend
*fe
)
2978 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
2980 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2981 cxd2841er_active_s_to_sleep_s(fe
->demodulator_priv
);
2982 cxd2841er_sleep_s_to_shutdown(fe
->demodulator_priv
);
2986 static int cxd2841er_sleep_tc(struct dvb_frontend
*fe
)
2988 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
2990 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
2991 if (priv
->state
== STATE_ACTIVE_TC
) {
2992 switch (priv
->system
) {
2994 cxd2841er_active_t_to_sleep_tc(priv
);
2997 cxd2841er_active_t2_to_sleep_tc(priv
);
3000 cxd2841er_active_i_to_sleep_tc(priv
);
3002 case SYS_DVBC_ANNEX_A
:
3003 cxd2841er_active_c_to_sleep_tc(priv
);
3006 dev_warn(&priv
->i2c
->dev
,
3007 "%s(): unknown delivery system %d\n",
3008 __func__
, priv
->system
);
3011 if (priv
->state
!= STATE_SLEEP_TC
) {
3012 dev_err(&priv
->i2c
->dev
, "%s(): invalid state %d\n",
3013 __func__
, priv
->state
);
3016 cxd2841er_sleep_tc_to_shutdown(priv
);
3020 static int cxd2841er_send_burst(struct dvb_frontend
*fe
,
3021 enum fe_sec_mini_cmd burst
)
3024 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3026 dev_dbg(&priv
->i2c
->dev
, "%s(): burst mode %s\n", __func__
,
3027 (burst
== SEC_MINI_A
? "A" : "B"));
3028 if (priv
->state
!= STATE_SLEEP_S
&&
3029 priv
->state
!= STATE_ACTIVE_S
) {
3030 dev_err(&priv
->i2c
->dev
, "%s(): invalid demod state %d\n",
3031 __func__
, priv
->state
);
3034 data
= (burst
== SEC_MINI_A
? 0 : 1);
3035 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xbb);
3036 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x34, 0x01);
3037 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x35, data
);
3041 static int cxd2841er_set_tone(struct dvb_frontend
*fe
,
3042 enum fe_sec_tone_mode tone
)
3045 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3047 dev_dbg(&priv
->i2c
->dev
, "%s(): tone %s\n", __func__
,
3048 (tone
== SEC_TONE_ON
? "On" : "Off"));
3049 if (priv
->state
!= STATE_SLEEP_S
&&
3050 priv
->state
!= STATE_ACTIVE_S
) {
3051 dev_err(&priv
->i2c
->dev
, "%s(): invalid demod state %d\n",
3052 __func__
, priv
->state
);
3055 data
= (tone
== SEC_TONE_ON
? 1 : 0);
3056 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xbb);
3057 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x36, data
);
3061 static int cxd2841er_send_diseqc_msg(struct dvb_frontend
*fe
,
3062 struct dvb_diseqc_master_cmd
*cmd
)
3066 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3068 if (priv
->state
!= STATE_SLEEP_S
&&
3069 priv
->state
!= STATE_ACTIVE_S
) {
3070 dev_err(&priv
->i2c
->dev
, "%s(): invalid demod state %d\n",
3071 __func__
, priv
->state
);
3074 dev_dbg(&priv
->i2c
->dev
,
3075 "%s(): cmd->len %d\n", __func__
, cmd
->msg_len
);
3076 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xbb);
3078 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x33, 0x01);
3079 /* cmd1 length & data */
3080 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x3d, cmd
->msg_len
);
3081 memset(data
, 0, sizeof(data
));
3082 for (i
= 0; i
< cmd
->msg_len
&& i
< sizeof(data
); i
++)
3083 data
[i
] = cmd
->msg
[i
];
3084 cxd2841er_write_regs(priv
, I2C_SLVT
, 0x3e, data
, sizeof(data
));
3085 /* repeat count for cmd1 */
3086 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x37, 1);
3087 /* repeat count for cmd2: always 0 */
3088 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x38, 0);
3089 /* start transmit */
3090 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x32, 0x01);
3091 /* wait for 1 sec timeout */
3092 for (i
= 0; i
< 50; i
++) {
3093 cxd2841er_read_reg(priv
, I2C_SLVT
, 0x10, data
);
3095 dev_dbg(&priv
->i2c
->dev
,
3096 "%s(): DiSEqC cmd has been sent\n", __func__
);
3101 dev_dbg(&priv
->i2c
->dev
,
3102 "%s(): DiSEqC cmd transmit timeout\n", __func__
);
3106 static void cxd2841er_release(struct dvb_frontend
*fe
)
3108 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3110 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
3114 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
3116 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3118 dev_dbg(&priv
->i2c
->dev
, "%s(): enable=%d\n", __func__
, enable
);
3119 cxd2841er_set_reg_bits(
3120 priv
, I2C_SLVX
, 0x8, (enable
? 0x01 : 0x00), 0x01);
3124 static enum dvbfe_algo
cxd2841er_get_algo(struct dvb_frontend
*fe
)
3126 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3128 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
3129 return DVBFE_ALGO_HW
;
3132 static int cxd2841er_init_s(struct dvb_frontend
*fe
)
3134 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3136 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
3137 cxd2841er_shutdown_to_sleep_s(priv
);
3138 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3139 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0xa0);
3140 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xb9, 0x01, 0x01);
3144 static int cxd2841er_init_tc(struct dvb_frontend
*fe
)
3146 struct cxd2841er_priv
*priv
= fe
->demodulator_priv
;
3148 dev_dbg(&priv
->i2c
->dev
, "%s()\n", __func__
);
3149 cxd2841er_shutdown_to_sleep_tc(priv
);
3150 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3151 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x10);
3152 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xcb, 0x40, 0x40);
3153 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3154 cxd2841er_write_reg(priv
, I2C_SLVT
, 0xcd, 0x50);
3155 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3156 cxd2841er_write_reg(priv
, I2C_SLVT
, 0x00, 0x00);
3157 cxd2841er_set_reg_bits(priv
, I2C_SLVT
, 0xc4, 0x00, 0x80);
3161 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops
;
3162 static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops
;
3163 static struct dvb_frontend_ops cxd2841er_dvbc_ops
;
3164 static struct dvb_frontend_ops cxd2841er_isdbt_ops
;
3166 static struct dvb_frontend
*cxd2841er_attach(struct cxd2841er_config
*cfg
,
3167 struct i2c_adapter
*i2c
,
3172 struct cxd2841er_priv
*priv
= NULL
;
3174 /* allocate memory for the internal state */
3175 priv
= kzalloc(sizeof(struct cxd2841er_priv
), GFP_KERNEL
);
3180 priv
->i2c_addr_slvx
= (cfg
->i2c_addr
+ 4) >> 1;
3181 priv
->i2c_addr_slvt
= (cfg
->i2c_addr
) >> 1;
3182 priv
->xtal
= cfg
->xtal
;
3183 /* create dvb_frontend */
3186 memcpy(&priv
->frontend
.ops
,
3187 &cxd2841er_dvbs_s2_ops
,
3188 sizeof(struct dvb_frontend_ops
));
3192 memcpy(&priv
->frontend
.ops
,
3193 &cxd2841er_dvbt_t2_ops
,
3194 sizeof(struct dvb_frontend_ops
));
3198 memcpy(&priv
->frontend
.ops
,
3199 &cxd2841er_isdbt_ops
,
3200 sizeof(struct dvb_frontend_ops
));
3203 case SYS_DVBC_ANNEX_A
:
3204 memcpy(&priv
->frontend
.ops
,
3205 &cxd2841er_dvbc_ops
,
3206 sizeof(struct dvb_frontend_ops
));
3213 priv
->frontend
.demodulator_priv
= priv
;
3214 dev_info(&priv
->i2c
->dev
,
3215 "%s(): attaching CXD2841ER DVB-%s frontend\n",
3217 dev_info(&priv
->i2c
->dev
,
3218 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3219 __func__
, priv
->i2c
,
3220 priv
->i2c_addr_slvx
, priv
->i2c_addr_slvt
);
3221 chip_id
= cxd2841er_chip_id(priv
);
3222 if (chip_id
!= CXD2841ER_CHIP_ID
&& chip_id
!= CXD2854ER_CHIP_ID
) {
3223 dev_err(&priv
->i2c
->dev
, "%s(): invalid chip ID 0x%02x\n",
3225 priv
->frontend
.demodulator_priv
= NULL
;
3229 dev_info(&priv
->i2c
->dev
, "%s(): chip ID 0x%02x OK.\n",
3231 return &priv
->frontend
;
3234 struct dvb_frontend
*cxd2841er_attach_s(struct cxd2841er_config
*cfg
,
3235 struct i2c_adapter
*i2c
)
3237 return cxd2841er_attach(cfg
, i2c
, SYS_DVBS
);
3239 EXPORT_SYMBOL(cxd2841er_attach_s
);
3241 struct dvb_frontend
*cxd2841er_attach_t(struct cxd2841er_config
*cfg
,
3242 struct i2c_adapter
*i2c
)
3244 return cxd2841er_attach(cfg
, i2c
, SYS_DVBT
);
3246 EXPORT_SYMBOL(cxd2841er_attach_t
);
3248 struct dvb_frontend
*cxd2841er_attach_i(struct cxd2841er_config
*cfg
,
3249 struct i2c_adapter
*i2c
)
3251 return cxd2841er_attach(cfg
, i2c
, SYS_ISDBT
);
3253 EXPORT_SYMBOL(cxd2841er_attach_i
);
3255 struct dvb_frontend
*cxd2841er_attach_c(struct cxd2841er_config
*cfg
,
3256 struct i2c_adapter
*i2c
)
3258 return cxd2841er_attach(cfg
, i2c
, SYS_DVBC_ANNEX_A
);
3260 EXPORT_SYMBOL(cxd2841er_attach_c
);
3262 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops
= {
3263 .delsys
= { SYS_DVBS
, SYS_DVBS2
},
3265 .name
= "Sony CXD2841ER DVB-S/S2 demodulator",
3266 .frequency_min
= 500000,
3267 .frequency_max
= 2500000,
3268 .frequency_stepsize
= 0,
3269 .symbol_rate_min
= 1000000,
3270 .symbol_rate_max
= 45000000,
3271 .symbol_rate_tolerance
= 500,
3272 .caps
= FE_CAN_INVERSION_AUTO
|
3276 .init
= cxd2841er_init_s
,
3277 .sleep
= cxd2841er_sleep_s
,
3278 .release
= cxd2841er_release
,
3279 .set_frontend
= cxd2841er_set_frontend_s
,
3280 .get_frontend
= cxd2841er_get_frontend
,
3281 .read_status
= cxd2841er_read_status_s
,
3282 .i2c_gate_ctrl
= cxd2841er_i2c_gate_ctrl
,
3283 .get_frontend_algo
= cxd2841er_get_algo
,
3284 .set_tone
= cxd2841er_set_tone
,
3285 .diseqc_send_burst
= cxd2841er_send_burst
,
3286 .diseqc_send_master_cmd
= cxd2841er_send_diseqc_msg
,
3287 .tune
= cxd2841er_tune_s
3290 static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops
= {
3291 .delsys
= { SYS_DVBT
, SYS_DVBT2
},
3293 .name
= "Sony CXD2841ER DVB-T/T2 demodulator",
3294 .caps
= FE_CAN_FEC_1_2
|
3307 FE_CAN_TRANSMISSION_MODE_AUTO
|
3308 FE_CAN_GUARD_INTERVAL_AUTO
|
3309 FE_CAN_HIERARCHY_AUTO
|
3311 FE_CAN_2G_MODULATION
,
3312 .frequency_min
= 42000000,
3313 .frequency_max
= 1002000000
3315 .init
= cxd2841er_init_tc
,
3316 .sleep
= cxd2841er_sleep_tc
,
3317 .release
= cxd2841er_release
,
3318 .set_frontend
= cxd2841er_set_frontend_tc
,
3319 .get_frontend
= cxd2841er_get_frontend
,
3320 .read_status
= cxd2841er_read_status_tc
,
3321 .tune
= cxd2841er_tune_tc
,
3322 .i2c_gate_ctrl
= cxd2841er_i2c_gate_ctrl
,
3323 .get_frontend_algo
= cxd2841er_get_algo
3326 static struct dvb_frontend_ops cxd2841er_isdbt_ops
= {
3327 .delsys
= { SYS_ISDBT
},
3329 .name
= "Sony CXD2854ER ISDBT demodulator",
3330 .caps
= FE_CAN_FEC_1_2
|
3343 FE_CAN_TRANSMISSION_MODE_AUTO
|
3344 FE_CAN_GUARD_INTERVAL_AUTO
|
3345 FE_CAN_HIERARCHY_AUTO
|
3347 FE_CAN_2G_MODULATION
,
3348 .frequency_min
= 42000000,
3349 .frequency_max
= 1002000000
3351 .init
= cxd2841er_init_tc
,
3352 .sleep
= cxd2841er_sleep_tc
,
3353 .release
= cxd2841er_release
,
3354 .set_frontend
= cxd2841er_set_frontend_tc
,
3355 .get_frontend
= cxd2841er_get_frontend
,
3356 .read_status
= cxd2841er_read_status_tc
,
3357 .tune
= cxd2841er_tune_tc
,
3358 .i2c_gate_ctrl
= cxd2841er_i2c_gate_ctrl
,
3359 .get_frontend_algo
= cxd2841er_get_algo
3362 static struct dvb_frontend_ops cxd2841er_dvbc_ops
= {
3363 .delsys
= { SYS_DVBC_ANNEX_A
},
3365 .name
= "Sony CXD2841ER DVB-C demodulator",
3366 .caps
= FE_CAN_FEC_1_2
|
3378 FE_CAN_INVERSION_AUTO
,
3379 .frequency_min
= 42000000,
3380 .frequency_max
= 1002000000
3382 .init
= cxd2841er_init_tc
,
3383 .sleep
= cxd2841er_sleep_tc
,
3384 .release
= cxd2841er_release
,
3385 .set_frontend
= cxd2841er_set_frontend_tc
,
3386 .get_frontend
= cxd2841er_get_frontend
,
3387 .read_status
= cxd2841er_read_status_tc
,
3388 .tune
= cxd2841er_tune_tc
,
3389 .i2c_gate_ctrl
= cxd2841er_i2c_gate_ctrl
,
3390 .get_frontend_algo
= cxd2841er_get_algo
,
3393 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3394 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
3395 MODULE_LICENSE("GPL");