drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt2.h

   1 /*
   2  * cxd2880_dvbt2.h
   3  * Sony CXD2880 DVB-T2/T tuner + demodulator driver
   4  * DVB-T2 related definitions
   5  *
   6  * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; version 2 of the License.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  13  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  15  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  16  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  20  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along
  24  * with this program; if not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #ifndef CXD2880_DVBT2_H
  28 #define CXD2880_DVBT2_H
  29
  30 #include "cxd2880_common.h"
  31
  32 enum cxd2880_dvbt2_profile {
  33         CXD2880_DVBT2_PROFILE_BASE,
  34         CXD2880_DVBT2_PROFILE_LITE,
  35         CXD2880_DVBT2_PROFILE_ANY
  36 };
  37
  38 enum cxd2880_dvbt2_version {
  39         CXD2880_DVBT2_V111,
  40         CXD2880_DVBT2_V121,
  41         CXD2880_DVBT2_V131
  42 };
  43
  44 enum cxd2880_dvbt2_s1 {
  45         CXD2880_DVBT2_S1_BASE_SISO = 0x00,
  46         CXD2880_DVBT2_S1_BASE_MISO = 0x01,
  47         CXD2880_DVBT2_S1_NON_DVBT2 = 0x02,
  48         CXD2880_DVBT2_S1_LITE_SISO = 0x03,
  49         CXD2880_DVBT2_S1_LITE_MISO = 0x04,
  50         CXD2880_DVBT2_S1_RSVD3 = 0x05,
  51         CXD2880_DVBT2_S1_RSVD4 = 0x06,
  52         CXD2880_DVBT2_S1_RSVD5 = 0x07,
  53         CXD2880_DVBT2_S1_UNKNOWN = 0xFF
  54 };
  55
  56 enum cxd2880_dvbt2_base_s2 {
  57         CXD2880_DVBT2_BASE_S2_M2K_G_ANY = 0x00,
  58         CXD2880_DVBT2_BASE_S2_M8K_G_DVBT = 0x01,
  59         CXD2880_DVBT2_BASE_S2_M4K_G_ANY = 0x02,
  60         CXD2880_DVBT2_BASE_S2_M1K_G_ANY = 0x03,
  61         CXD2880_DVBT2_BASE_S2_M16K_G_ANY = 0x04,
  62         CXD2880_DVBT2_BASE_S2_M32K_G_DVBT = 0x05,
  63         CXD2880_DVBT2_BASE_S2_M8K_G_DVBT2 = 0x06,
  64         CXD2880_DVBT2_BASE_S2_M32K_G_DVBT2 = 0x07,
  65         CXD2880_DVBT2_BASE_S2_UNKNOWN = 0xFF
  66 };
  67
  68 enum cxd2880_dvbt2_lite_s2 {
  69         CXD2880_DVBT2_LITE_S2_M2K_G_ANY = 0x00,
  70         CXD2880_DVBT2_LITE_S2_M8K_G_DVBT = 0x01,
  71         CXD2880_DVBT2_LITE_S2_M4K_G_ANY = 0x02,
  72         CXD2880_DVBT2_LITE_S2_M16K_G_DVBT2 = 0x03,
  73         CXD2880_DVBT2_LITE_S2_M16K_G_DVBT = 0x04,
  74         CXD2880_DVBT2_LITE_S2_RSVD1 = 0x05,
  75         CXD2880_DVBT2_LITE_S2_M8K_G_DVBT2 = 0x06,
  76         CXD2880_DVBT2_LITE_S2_RSVD2 = 0x07,
  77         CXD2880_DVBT2_LITE_S2_UNKNOWN = 0xFF
  78 };
  79
  80 enum cxd2880_dvbt2_guard {
  81         CXD2880_DVBT2_G1_32 = 0x00,
  82         CXD2880_DVBT2_G1_16 = 0x01,
  83         CXD2880_DVBT2_G1_8 = 0x02,
  84         CXD2880_DVBT2_G1_4 = 0x03,
  85         CXD2880_DVBT2_G1_128 = 0x04,
  86         CXD2880_DVBT2_G19_128 = 0x05,
  87         CXD2880_DVBT2_G19_256 = 0x06,
  88         CXD2880_DVBT2_G_RSVD1 = 0x07,
  89         CXD2880_DVBT2_G_UNKNOWN = 0xFF
  90 };
  91
  92 enum cxd2880_dvbt2_mode {
  93         CXD2880_DVBT2_M2K = 0x00,
  94         CXD2880_DVBT2_M8K = 0x01,
  95         CXD2880_DVBT2_M4K = 0x02,
  96         CXD2880_DVBT2_M1K = 0x03,
  97         CXD2880_DVBT2_M16K = 0x04,
  98         CXD2880_DVBT2_M32K = 0x05,
  99         CXD2880_DVBT2_M_RSVD1 = 0x06,
 100         CXD2880_DVBT2_M_RSVD2 = 0x07
 101 };
 102
 103 enum cxd2880_dvbt2_bw {
 104         CXD2880_DVBT2_BW_8 = 0x00,
 105         CXD2880_DVBT2_BW_7 = 0x01,
 106         CXD2880_DVBT2_BW_6 = 0x02,
 107         CXD2880_DVBT2_BW_5 = 0x03,
 108         CXD2880_DVBT2_BW_10 = 0x04,
 109         CXD2880_DVBT2_BW_1_7 = 0x05,
 110         CXD2880_DVBT2_BW_RSVD1 = 0x06,
 111         CXD2880_DVBT2_BW_RSVD2 = 0x07,
 112         CXD2880_DVBT2_BW_RSVD3 = 0x08,
 113         CXD2880_DVBT2_BW_RSVD4 = 0x09,
 114         CXD2880_DVBT2_BW_RSVD5 = 0x0A,
 115         CXD2880_DVBT2_BW_RSVD6 = 0x0B,
 116         CXD2880_DVBT2_BW_RSVD7 = 0x0C,
 117         CXD2880_DVBT2_BW_RSVD8 = 0x0D,
 118         CXD2880_DVBT2_BW_RSVD9 = 0x0E,
 119         CXD2880_DVBT2_BW_RSVD10 = 0x0F,
 120         CXD2880_DVBT2_BW_UNKNOWN = 0xFF
 121 };
 122
 123 enum cxd2880_dvbt2_l1pre_type {
 124         CXD2880_DVBT2_L1PRE_TYPE_TS = 0x00,
 125         CXD2880_DVBT2_L1PRE_TYPE_GS = 0x01,
 126         CXD2880_DVBT2_L1PRE_TYPE_TS_GS = 0x02,
 127         CXD2880_DVBT2_L1PRE_TYPE_RESERVED = 0x03,
 128         CXD2880_DVBT2_L1PRE_TYPE_UNKNOWN = 0xFF
 129 };
 130
 131 enum cxd2880_dvbt2_papr {
 132         CXD2880_DVBT2_PAPR_0 = 0x00,
 133         CXD2880_DVBT2_PAPR_1 = 0x01,
 134         CXD2880_DVBT2_PAPR_2 = 0x02,
 135         CXD2880_DVBT2_PAPR_3 = 0x03,
 136         CXD2880_DVBT2_PAPR_RSVD1 = 0x04,
 137         CXD2880_DVBT2_PAPR_RSVD2 = 0x05,
 138         CXD2880_DVBT2_PAPR_RSVD3 = 0x06,
 139         CXD2880_DVBT2_PAPR_RSVD4 = 0x07,
 140         CXD2880_DVBT2_PAPR_RSVD5 = 0x08,
 141         CXD2880_DVBT2_PAPR_RSVD6 = 0x09,
 142         CXD2880_DVBT2_PAPR_RSVD7 = 0x0A,
 143         CXD2880_DVBT2_PAPR_RSVD8 = 0x0B,
 144         CXD2880_DVBT2_PAPR_RSVD9 = 0x0C,
 145         CXD2880_DVBT2_PAPR_RSVD10 = 0x0D,
 146         CXD2880_DVBT2_PAPR_RSVD11 = 0x0E,
 147         CXD2880_DVBT2_PAPR_RSVD12 = 0x0F,
 148         CXD2880_DVBT2_PAPR_UNKNOWN = 0xFF
 149 };
 150
 151 enum cxd2880_dvbt2_l1post_constell {
 152         CXD2880_DVBT2_L1POST_BPSK = 0x00,
 153         CXD2880_DVBT2_L1POST_QPSK = 0x01,
 154         CXD2880_DVBT2_L1POST_QAM16 = 0x02,
 155         CXD2880_DVBT2_L1POST_QAM64 = 0x03,
 156         CXD2880_DVBT2_L1POST_C_RSVD1 = 0x04,
 157         CXD2880_DVBT2_L1POST_C_RSVD2 = 0x05,
 158         CXD2880_DVBT2_L1POST_C_RSVD3 = 0x06,
 159         CXD2880_DVBT2_L1POST_C_RSVD4 = 0x07,
 160         CXD2880_DVBT2_L1POST_C_RSVD5 = 0x08,
 161         CXD2880_DVBT2_L1POST_C_RSVD6 = 0x09,
 162         CXD2880_DVBT2_L1POST_C_RSVD7 = 0x0A,
 163         CXD2880_DVBT2_L1POST_C_RSVD8 = 0x0B,
 164         CXD2880_DVBT2_L1POST_C_RSVD9 = 0x0C,
 165         CXD2880_DVBT2_L1POST_C_RSVD10 = 0x0D,
 166         CXD2880_DVBT2_L1POST_C_RSVD11 = 0x0E,
 167         CXD2880_DVBT2_L1POST_C_RSVD12 = 0x0F,
 168         CXD2880_DVBT2_L1POST_CONSTELL_UNKNOWN = 0xFF
 169 };
 170
 171 enum cxd2880_dvbt2_l1post_cr {
 172         CXD2880_DVBT2_L1POST_R1_2 = 0x00,
 173         CXD2880_DVBT2_L1POST_R_RSVD1 = 0x01,
 174         CXD2880_DVBT2_L1POST_R_RSVD2 = 0x02,
 175         CXD2880_DVBT2_L1POST_R_RSVD3 = 0x03,
 176         CXD2880_DVBT2_L1POST_R_UNKNOWN = 0xFF
 177 };
 178
 179 enum cxd2880_dvbt2_l1post_fec_type {
 180         CXD2880_DVBT2_L1POST_FEC_LDPC16K = 0x00,
 181         CXD2880_DVBT2_L1POST_FEC_RSVD1 = 0x01,
 182         CXD2880_DVBT2_L1POST_FEC_RSVD2 = 0x02,
 183         CXD2880_DVBT2_L1POST_FEC_RSVD3 = 0x03,
 184         CXD2880_DVBT2_L1POST_FEC_UNKNOWN = 0xFF
 185 };
 186
 187 enum cxd2880_dvbt2_pp {
 188         CXD2880_DVBT2_PP1 = 0x00,
 189         CXD2880_DVBT2_PP2 = 0x01,
 190         CXD2880_DVBT2_PP3 = 0x02,
 191         CXD2880_DVBT2_PP4 = 0x03,
 192         CXD2880_DVBT2_PP5 = 0x04,
 193         CXD2880_DVBT2_PP6 = 0x05,
 194         CXD2880_DVBT2_PP7 = 0x06,
 195         CXD2880_DVBT2_PP8 = 0x07,
 196         CXD2880_DVBT2_PP_RSVD1 = 0x08,
 197         CXD2880_DVBT2_PP_RSVD2 = 0x09,
 198         CXD2880_DVBT2_PP_RSVD3 = 0x0A,
 199         CXD2880_DVBT2_PP_RSVD4 = 0x0B,
 200         CXD2880_DVBT2_PP_RSVD5 = 0x0C,
 201         CXD2880_DVBT2_PP_RSVD6 = 0x0D,
 202         CXD2880_DVBT2_PP_RSVD7 = 0x0E,
 203         CXD2880_DVBT2_PP_RSVD8 = 0x0F,
 204         CXD2880_DVBT2_PP_UNKNOWN = 0xFF
 205 };
 206
 207 enum cxd2880_dvbt2_plp_code_rate {
 208         CXD2880_DVBT2_R1_2 = 0x00,
 209         CXD2880_DVBT2_R3_5 = 0x01,
 210         CXD2880_DVBT2_R2_3 = 0x02,
 211         CXD2880_DVBT2_R3_4 = 0x03,
 212         CXD2880_DVBT2_R4_5 = 0x04,
 213         CXD2880_DVBT2_R5_6 = 0x05,
 214         CXD2880_DVBT2_R1_3 = 0x06,
 215         CXD2880_DVBT2_R2_5 = 0x07,
 216         CXD2880_DVBT2_PLP_CR_UNKNOWN = 0xFF
 217 };
 218
 219 enum cxd2880_dvbt2_plp_constell {
 220         CXD2880_DVBT2_QPSK = 0x00,
 221         CXD2880_DVBT2_QAM16 = 0x01,
 222         CXD2880_DVBT2_QAM64 = 0x02,
 223         CXD2880_DVBT2_QAM256 = 0x03,
 224         CXD2880_DVBT2_CON_RSVD1 = 0x04,
 225         CXD2880_DVBT2_CON_RSVD2 = 0x05,
 226         CXD2880_DVBT2_CON_RSVD3 = 0x06,
 227         CXD2880_DVBT2_CON_RSVD4 = 0x07,
 228         CXD2880_DVBT2_CONSTELL_UNKNOWN = 0xFF
 229 };
 230
 231 enum cxd2880_dvbt2_plp_type {
 232         CXD2880_DVBT2_PLP_TYPE_COMMON = 0x00,
 233         CXD2880_DVBT2_PLP_TYPE_DATA1 = 0x01,
 234         CXD2880_DVBT2_PLP_TYPE_DATA2 = 0x02,
 235         CXD2880_DVBT2_PLP_TYPE_RSVD1 = 0x03,
 236         CXD2880_DVBT2_PLP_TYPE_RSVD2 = 0x04,
 237         CXD2880_DVBT2_PLP_TYPE_RSVD3 = 0x05,
 238         CXD2880_DVBT2_PLP_TYPE_RSVD4 = 0x06,
 239         CXD2880_DVBT2_PLP_TYPE_RSVD5 = 0x07,
 240         CXD2880_DVBT2_PLP_TYPE_UNKNOWN = 0xFF
 241 };
 242
 243 enum cxd2880_dvbt2_plp_payload {
 244         CXD2880_DVBT2_PLP_PAYLOAD_GFPS = 0x00,
 245         CXD2880_DVBT2_PLP_PAYLOAD_GCS = 0x01,
 246         CXD2880_DVBT2_PLP_PAYLOAD_GSE = 0x02,
 247         CXD2880_DVBT2_PLP_PAYLOAD_TS = 0x03,
 248         CXD2880_DVBT2_PLP_PAYLOAD_RSVD1 = 0x04,
 249         CXD2880_DVBT2_PLP_PAYLOAD_RSVD2 = 0x05,
 250         CXD2880_DVBT2_PLP_PAYLOAD_RSVD3 = 0x06,
 251         CXD2880_DVBT2_PLP_PAYLOAD_RSVD4 = 0x07,
 252         CXD2880_DVBT2_PLP_PAYLOAD_RSVD5 = 0x08,
 253         CXD2880_DVBT2_PLP_PAYLOAD_RSVD6 = 0x09,
 254         CXD2880_DVBT2_PLP_PAYLOAD_RSVD7 = 0x0A,
 255         CXD2880_DVBT2_PLP_PAYLOAD_RSVD8 = 0x0B,
 256         CXD2880_DVBT2_PLP_PAYLOAD_RSVD9 = 0x0C,
 257         CXD2880_DVBT2_PLP_PAYLOAD_RSVD10 = 0x0D,
 258         CXD2880_DVBT2_PLP_PAYLOAD_RSVD11 = 0x0E,
 259         CXD2880_DVBT2_PLP_PAYLOAD_RSVD12 = 0x0F,
 260         CXD2880_DVBT2_PLP_PAYLOAD_RSVD13 = 0x10,
 261         CXD2880_DVBT2_PLP_PAYLOAD_RSVD14 = 0x11,
 262         CXD2880_DVBT2_PLP_PAYLOAD_RSVD15 = 0x12,
 263         CXD2880_DVBT2_PLP_PAYLOAD_RSVD16 = 0x13,
 264         CXD2880_DVBT2_PLP_PAYLOAD_RSVD17 = 0x14,
 265         CXD2880_DVBT2_PLP_PAYLOAD_RSVD18 = 0x15,
 266         CXD2880_DVBT2_PLP_PAYLOAD_RSVD19 = 0x16,
 267         CXD2880_DVBT2_PLP_PAYLOAD_RSVD20 = 0x17,
 268         CXD2880_DVBT2_PLP_PAYLOAD_RSVD21 = 0x18,
 269         CXD2880_DVBT2_PLP_PAYLOAD_RSVD22 = 0x19,
 270         CXD2880_DVBT2_PLP_PAYLOAD_RSVD23 = 0x1A,
 271         CXD2880_DVBT2_PLP_PAYLOAD_RSVD24 = 0x1B,
 272         CXD2880_DVBT2_PLP_PAYLOAD_RSVD25 = 0x1C,
 273         CXD2880_DVBT2_PLP_PAYLOAD_RSVD26 = 0x1D,
 274         CXD2880_DVBT2_PLP_PAYLOAD_RSVD27 = 0x1E,
 275         CXD2880_DVBT2_PLP_PAYLOAD_RSVD28 = 0x1F,
 276         CXD2880_DVBT2_PLP_PAYLOAD_UNKNOWN = 0xFF
 277 };
 278
 279 enum cxd2880_dvbt2_plp_fec {
 280         CXD2880_DVBT2_FEC_LDPC_16K = 0x00,
 281         CXD2880_DVBT2_FEC_LDPC_64K = 0x01,
 282         CXD2880_DVBT2_FEC_RSVD1 = 0x02,
 283         CXD2880_DVBT2_FEC_RSVD2 = 0x03,
 284         CXD2880_DVBT2_FEC_UNKNOWN = 0xFF
 285 };
 286
 287 enum cxd2880_dvbt2_plp_mode {
 288         CXD2880_DVBT2_PLP_MODE_NOTSPECIFIED = 0x00,
 289         CXD2880_DVBT2_PLP_MODE_NM = 0x01,
 290         CXD2880_DVBT2_PLP_MODE_HEM = 0x02,
 291         CXD2880_DVBT2_PLP_MODE_RESERVED = 0x03,
 292         CXD2880_DVBT2_PLP_MODE_UNKNOWN = 0xFF
 293 };
 294
 295 enum cxd2880_dvbt2_plp_btype {
 296         CXD2880_DVBT2_PLP_COMMON,
 297         CXD2880_DVBT2_PLP_DATA
 298 };
 299
 300 enum cxd2880_dvbt2_stream {
 301         CXD2880_DVBT2_STREAM_GENERIC_PACKETIZED = 0x00,
 302         CXD2880_DVBT2_STREAM_GENERIC_CONTINUOUS = 0x01,
 303         CXD2880_DVBT2_STREAM_GENERIC_ENCAPSULATED = 0x02,
 304         CXD2880_DVBT2_STREAM_TRANSPORT = 0x03,
 305         CXD2880_DVBT2_STREAM_UNKNOWN = 0xFF
 306 };
 307
 308 struct cxd2880_dvbt2_l1pre {
 309         enum cxd2880_dvbt2_l1pre_type type;
 310         u8 bw_ext;
 311         enum cxd2880_dvbt2_s1 s1;
 312         u8 s2;
 313         u8 mixed;
 314         enum cxd2880_dvbt2_mode fft_mode;
 315         u8 l1_rep;
 316         enum cxd2880_dvbt2_guard gi;
 317         enum cxd2880_dvbt2_papr papr;
 318         enum cxd2880_dvbt2_l1post_constell mod;
 319         enum cxd2880_dvbt2_l1post_cr cr;
 320         enum cxd2880_dvbt2_l1post_fec_type fec;
 321         u32 l1_post_size;
 322         u32 l1_post_info_size;
 323         enum cxd2880_dvbt2_pp pp;
 324         u8 tx_id_availability;
 325         u16 cell_id;
 326         u16 network_id;
 327         u16 sys_id;
 328         u8 num_frames;
 329         u16 num_symbols;
 330         u8 regen;
 331         u8 post_ext;
 332         u8 num_rf_freqs;
 333         u8 rf_idx;
 334         enum cxd2880_dvbt2_version t2_version;
 335         u8 l1_post_scrambled;
 336         u8 t2_base_lite;
 337         u32 crc32;
 338 };
 339
 340 struct cxd2880_dvbt2_plp {
 341         u8 id;
 342         enum cxd2880_dvbt2_plp_type type;
 343         enum cxd2880_dvbt2_plp_payload payload;
 344         u8 ff;
 345         u8 first_rf_idx;
 346         u8 first_frm_idx;
 347         u8 group_id;
 348         enum cxd2880_dvbt2_plp_constell constell;
 349         enum cxd2880_dvbt2_plp_code_rate plp_cr;
 350         u8 rot;
 351         enum cxd2880_dvbt2_plp_fec fec;
 352         u16 num_blocks_max;
 353         u8 frm_int;
 354         u8 til_len;
 355         u8 til_type;
 356         u8 in_band_a_flag;
 357         u8 in_band_b_flag;
 358         u16 rsvd;
 359         enum cxd2880_dvbt2_plp_mode plp_mode;
 360         u8 static_flag;
 361         u8 static_padding_flag;
 362 };
 363
 364 struct cxd2880_dvbt2_l1post {
 365         u16 sub_slices_per_frame;
 366         u8 num_plps;
 367         u8 num_aux;
 368         u8 aux_cfg_rfu;
 369         u8 rf_idx;
 370         u32 freq;
 371         u8 fef_type;
 372         u32 fef_length;
 373         u8 fef_intvl;
 374 };
 375
 376 struct cxd2880_dvbt2_ofdm {
 377         u8 mixed;
 378         u8 is_miso;
 379         enum cxd2880_dvbt2_mode mode;
 380         enum cxd2880_dvbt2_guard gi;
 381         enum cxd2880_dvbt2_pp pp;
 382         u8 bw_ext;
 383         enum cxd2880_dvbt2_papr papr;
 384         u16 num_symbols;
 385 };
 386
 387 struct cxd2880_dvbt2_bbheader {
 388         enum cxd2880_dvbt2_stream stream_input;
 389         u8 is_single_input_stream;
 390         u8 is_constant_coding_modulation;
 391         u8 issy_indicator;
 392         u8 null_packet_deletion;
 393         u8 ext;
 394         u8 input_stream_identifier;
 395         u16 user_packet_length;
 396         u16 data_field_length;
 397         u8 sync_byte;
 398         u32 issy;
 399         enum cxd2880_dvbt2_plp_mode plp_mode;
 400 };
 401
 402 #endif