drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.h

   1 /*
   2  * cxd2880_tnrdmd.h
   3  * Sony CXD2880 DVB-T2/T tuner + demodulator driver
   4  * common control interface
   5  *
   6  * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; version 2 of the License.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  13  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  15  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  16  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  20  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along
  24  * with this program; if not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #ifndef CXD2880_TNRDMD_H
  28 #define CXD2880_TNRDMD_H
  29
  30 #include "cxd2880_common.h"
  31 #include "cxd2880_io.h"
  32 #include "cxd2880_dtv.h"
  33 #include "cxd2880_dvbt.h"
  34 #include "cxd2880_dvbt2.h"
  35
  36 #define CXD2880_TNRDMD_MAX_CFG_MEM_COUNT 100
  37
  38 #define slvt_unfreeze_reg(tnr_dmd) ((void)((tnr_dmd)->io->write_reg\
  39 ((tnr_dmd)->io, CXD2880_IO_TGT_DMD, 0x01, 0x00)))
  40
  41 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_UNDERFLOW     0x0001
  42 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_OVERFLOW      0x0002
  43 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_EMPTY  0x0004
  44 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_FULL   0x0008
  45 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_RRDY    0x0010
  46 #define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_COMMAND      0x0020
  47 #define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_ACCESS       0x0040
  48 #define CXD2880_TNRDMD_INTERRUPT_TYPE_CPU_ERROR     0x0100
  49 #define CXD2880_TNRDMD_INTERRUPT_TYPE_LOCK               0x0200
  50 #define CXD2880_TNRDMD_INTERRUPT_TYPE_INV_LOCK       0x0400
  51 #define CXD2880_TNRDMD_INTERRUPT_TYPE_NOOFDM           0x0800
  52 #define CXD2880_TNRDMD_INTERRUPT_TYPE_EWS                 0x1000
  53 #define CXD2880_TNRDMD_INTERRUPT_TYPE_EEW                 0x2000
  54 #define CXD2880_TNRDMD_INTERRUPT_TYPE_FEC_FAIL       0x4000
  55
  56 #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_L1POST_OK     0x01
  57 #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_DMD_LOCK       0x02
  58 #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_TS_LOCK         0x04
  59
  60 enum cxd2880_tnrdmd_chip_id {
  61         CXD2880_TNRDMD_CHIP_ID_UNKNOWN = 0x00,
  62         CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X = 0x62,
  63         CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11 = 0x6A
  64 };
  65
  66 #define CXD2880_TNRDMD_CHIP_ID_VALID(chip_id) (((chip_id) == \
  67 CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) || \
  68 ((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11))
  69
  70 enum cxd2880_tnrdmd_state {
  71         CXD2880_TNRDMD_STATE_UNKNOWN,
  72         CXD2880_TNRDMD_STATE_SLEEP,
  73         CXD2880_TNRDMD_STATE_ACTIVE,
  74         CXD2880_TNRDMD_STATE_INVALID
  75 };
  76
  77 enum cxd2880_tnrdmd_divermode {
  78         CXD2880_TNRDMD_DIVERMODE_SINGLE,
  79         CXD2880_TNRDMD_DIVERMODE_MAIN,
  80         CXD2880_TNRDMD_DIVERMODE_SUB
  81 };
  82
  83 enum cxd2880_tnrdmd_clockmode {
  84         CXD2880_TNRDMD_CLOCKMODE_UNKNOWN,
  85         CXD2880_TNRDMD_CLOCKMODE_A,
  86         CXD2880_TNRDMD_CLOCKMODE_B,
  87         CXD2880_TNRDMD_CLOCKMODE_C
  88 };
  89
  90 enum cxd2880_tnrdmd_tsout_if {
  91         CXD2880_TNRDMD_TSOUT_IF_TS,
  92         CXD2880_TNRDMD_TSOUT_IF_SPI,
  93         CXD2880_TNRDMD_TSOUT_IF_SDIO
  94 };
  95
  96 enum cxd2880_tnrdmd_xtal_share {
  97         CXD2880_TNRDMD_XTAL_SHARE_NONE,
  98         CXD2880_TNRDMD_XTAL_SHARE_EXTREF,
  99         CXD2880_TNRDMD_XTAL_SHARE_MASTER,
 100         CXD2880_TNRDMD_XTAL_SHARE_SLAVE
 101 };
 102
 103 enum cxd2880_tnrdmd_spectrum_sense {
 104         CXD2880_TNRDMD_SPECTRUM_NORMAL,
 105         CXD2880_TNRDMD_SPECTRUM_INV
 106 };
 107
 108 enum cxd2880_tnrdmd_cfg_id {
 109         CXD2880_TNRDMD_CFG_OUTPUT_SEL_MSB,
 110         CXD2880_TNRDMD_CFG_TSVALID_ACTIVE_HI,
 111         CXD2880_TNRDMD_CFG_TSSYNC_ACTIVE_HI,
 112         CXD2880_TNRDMD_CFG_TSERR_ACTIVE_HI,
 113         CXD2880_TNRDMD_CFG_LATCH_ON_POSEDGE,
 114         CXD2880_TNRDMD_CFG_TSCLK_CONT,
 115         CXD2880_TNRDMD_CFG_TSCLK_MASK,
 116         CXD2880_TNRDMD_CFG_TSVALID_MASK,
 117         CXD2880_TNRDMD_CFG_TSERR_MASK,
 118         CXD2880_TNRDMD_CFG_TSERR_VALID_DIS,
 119         CXD2880_TNRDMD_CFG_TSPIN_CURRENT,
 120         CXD2880_TNRDMD_CFG_TSPIN_PULLUP_MANUAL,
 121         CXD2880_TNRDMD_CFG_TSPIN_PULLUP,
 122         CXD2880_TNRDMD_CFG_TSCLK_FREQ,
 123         CXD2880_TNRDMD_CFG_TSBYTECLK_MANUAL,
 124         CXD2880_TNRDMD_CFG_TS_PACKET_GAP,
 125         CXD2880_TNRDMD_CFG_TS_BACKWARDS_COMPATIBLE,
 126         CXD2880_TNRDMD_CFG_PWM_VALUE,
 127         CXD2880_TNRDMD_CFG_INTERRUPT,
 128         CXD2880_TNRDMD_CFG_INTERRUPT_LOCK_SEL,
 129         CXD2880_TNRDMD_CFG_INTERRUPT_INV_LOCK_SEL,
 130         CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_EMPTY_THRS,
 131         CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_FULL_THRS,
 132         CXD2880_TNRDMD_CFG_TS_BUF_RRDY_THRS,
 133         CXD2880_TNRDMD_CFG_FIXED_CLOCKMODE,
 134         CXD2880_TNRDMD_CFG_CABLE_INPUT,
 135         CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_BASE,
 136         CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_LITE,
 137         CXD2880_TNRDMD_CFG_BLINDTUNE_DVBT2_FIRST,
 138         CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,
 139         CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,
 140         CXD2880_TNRDMD_CFG_DVBT_PER_MES,
 141         CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,
 142         CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,
 143         CXD2880_TNRDMD_CFG_DVBT2_PER_MES,
 144         CXD2880_TNRDMD_CFG_ISDBT_BERPER_PERIOD
 145 };
 146
 147 enum cxd2880_tnrdmd_lock_result {
 148         CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT,
 149         CXD2880_TNRDMD_LOCK_RESULT_LOCKED,
 150         CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED
 151 };
 152
 153 enum cxd2880_tnrdmd_gpio_mode {
 154         CXD2880_TNRDMD_GPIO_MODE_OUTPUT = 0x00,
 155         CXD2880_TNRDMD_GPIO_MODE_INPUT = 0x01,
 156         CXD2880_TNRDMD_GPIO_MODE_INT = 0x02,
 157         CXD2880_TNRDMD_GPIO_MODE_FEC_FAIL = 0x03,
 158         CXD2880_TNRDMD_GPIO_MODE_PWM = 0x04,
 159         CXD2880_TNRDMD_GPIO_MODE_EWS = 0x05,
 160         CXD2880_TNRDMD_GPIO_MODE_EEW = 0x06
 161 };
 162
 163 enum cxd2880_tnrdmd_serial_ts_clk {
 164         CXD2880_TNRDMD_SERIAL_TS_CLK_FULL,
 165         CXD2880_TNRDMD_SERIAL_TS_CLK_HALF
 166 };
 167
 168 struct cxd2880_tnrdmd_cfg_mem {
 169         enum cxd2880_io_tgt tgt;
 170         u8 bank;
 171         u8 address;
 172         u8 value;
 173         u8 bit_mask;
 174 };
 175
 176 struct cxd2880_tnrdmd_pid_cfg {
 177         u8 is_en;
 178         u16 pid;
 179 };
 180
 181 struct cxd2880_tnrdmd_pid_ftr_cfg {
 182         u8 is_negative;
 183         struct cxd2880_tnrdmd_pid_cfg pid_cfg[32];
 184 };
 185
 186 struct cxd2880_tnrdmd_ts_buf_info {
 187         u8 read_ready;
 188         u8 almost_full;
 189         u8 almost_empty;
 190         u8 overflow;
 191         u8 underflow;
 192         u16 packet_num;
 193 };
 194
 195 struct cxd2880_tnrdmd_lna_thrs {
 196         u8 off_on;
 197         u8 on_off;
 198 };
 199
 200 struct cxd2880_tnrdmd_lna_thrs_tbl_air {
 201         struct cxd2880_tnrdmd_lna_thrs thrs[24];
 202 };
 203
 204 struct cxd2880_tnrdmd_lna_thrs_tbl_cable {
 205         struct cxd2880_tnrdmd_lna_thrs thrs[32];
 206 };
 207
 208 struct cxd2880_tnrdmd_create_param {
 209         enum cxd2880_tnrdmd_tsout_if ts_output_if;
 210         u8 en_internal_ldo;
 211         enum cxd2880_tnrdmd_xtal_share xtal_share_type;
 212         u8 xosc_cap;
 213         u8 xosc_i;
 214         u8 is_cxd2881gg;
 215         u8 stationary_use;
 216 };
 217
 218 struct cxd2880_tnrdmd_diver_create_param {
 219         enum cxd2880_tnrdmd_tsout_if ts_output_if;
 220         u8 en_internal_ldo;
 221         u8 xosc_cap_main;
 222         u8 xosc_i_main;
 223         u8 xosc_i_sub;
 224         u8 is_cxd2881gg;
 225         u8 stationary_use;
 226 };
 227
 228 struct cxd2880_tnrdmd {
 229         struct cxd2880_tnrdmd *diver_sub;
 230         struct cxd2880_io *io;
 231         struct cxd2880_tnrdmd_create_param create_param;
 232         enum cxd2880_tnrdmd_divermode diver_mode;
 233         enum cxd2880_tnrdmd_clockmode fixed_clk_mode;
 234         u8 is_cable_input;
 235         u8 en_fef_intmtnt_base;
 236         u8 en_fef_intmtnt_lite;
 237         u8 blind_tune_dvbt2_first;
 238         enum cxd2880_ret (*rf_lvl_cmpstn)(struct cxd2880_tnrdmd *tnr_dmd,
 239                                            int *rf_lvl_db);
 240         struct cxd2880_tnrdmd_lna_thrs_tbl_air *lna_thrs_tbl_air;
 241         struct cxd2880_tnrdmd_lna_thrs_tbl_cable *lna_thrs_tbl_cable;
 242         u8 srl_ts_clk_mod_cnts;
 243         enum cxd2880_tnrdmd_serial_ts_clk srl_ts_clk_frq;
 244         u8 ts_byte_clk_manual_setting;
 245         u8 is_ts_backwards_compatible_mode;
 246         struct cxd2880_tnrdmd_cfg_mem cfg_mem[CXD2880_TNRDMD_MAX_CFG_MEM_COUNT];
 247         u8 cfg_mem_last_entry;
 248         struct cxd2880_tnrdmd_pid_ftr_cfg pid_ftr_cfg;
 249         u8 pid_ftr_cfg_en;
 250         void *user;
 251         enum cxd2880_tnrdmd_chip_id chip_id;
 252         enum cxd2880_tnrdmd_state state;
 253         enum cxd2880_tnrdmd_clockmode clk_mode;
 254         u32 frequency_khz;
 255         enum cxd2880_dtv_sys sys;
 256         enum cxd2880_dtv_bandwidth bandwidth;
 257         u8 scan_mode;
 258         struct cxd2880_atomic cancel;
 259 };
 260
 261 enum cxd2880_ret cxd2880_tnrdmd_create(struct cxd2880_tnrdmd *tnr_dmd,
 262                                        struct cxd2880_io *io,
 263                                        struct cxd2880_tnrdmd_create_param
 264                                        *create_param);
 265
 266 enum cxd2880_ret cxd2880_tnrdmd_diver_create(struct cxd2880_tnrdmd
 267                                              *tnr_dmd_main,
 268                                              struct cxd2880_io *io_main,
 269                                              struct cxd2880_tnrdmd *tnr_dmd_sub,
 270                                              struct cxd2880_io *io_sub,
 271                                              struct
 272                                              cxd2880_tnrdmd_diver_create_param
 273                                              *create_param);
 274
 275 enum cxd2880_ret cxd2880_tnrdmd_init1(struct cxd2880_tnrdmd *tnr_dmd);
 276
 277 enum cxd2880_ret cxd2880_tnrdmd_init2(struct cxd2880_tnrdmd *tnr_dmd);
 278
 279 enum cxd2880_ret cxd2880_tnrdmd_check_internal_cpu_status(struct cxd2880_tnrdmd
 280                                                           *tnr_dmd,
 281                                                           u8 *task_completed);
 282
 283 enum cxd2880_ret cxd2880_tnrdmd_common_tune_setting1(struct cxd2880_tnrdmd
 284                                                      *tnr_dmd,
 285                                                      enum cxd2880_dtv_sys sys,
 286                                                      u32 frequency_khz,
 287                                                      enum cxd2880_dtv_bandwidth
 288                                                      bandwidth, u8 one_seg_opt,
 289                                                      u8 one_seg_opt_shft_dir);
 290
 291 enum cxd2880_ret cxd2880_tnrdmd_common_tune_setting2(struct cxd2880_tnrdmd
 292                                                      *tnr_dmd,
 293                                                      enum cxd2880_dtv_sys sys,
 294                                                      u8 en_fef_intmtnt_ctrl);
 295
 296 enum cxd2880_ret cxd2880_tnrdmd_sleep(struct cxd2880_tnrdmd *tnr_dmd);
 297
 298 enum cxd2880_ret cxd2880_tnrdmd_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
 299                                         enum cxd2880_tnrdmd_cfg_id id,
 300                                         int value);
 301
 302 enum cxd2880_ret cxd2880_tnrdmd_gpio_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
 303                                              u8 id,
 304                                              u8 en,
 305                                              enum cxd2880_tnrdmd_gpio_mode mode,
 306                                              u8 open_drain, u8 invert);
 307
 308 enum cxd2880_ret cxd2880_tnrdmd_gpio_set_cfg_sub(struct cxd2880_tnrdmd *tnr_dmd,
 309                                                  u8 id,
 310                                                  u8 en,
 311                                                  enum cxd2880_tnrdmd_gpio_mode
 312                                                  mode, u8 open_drain,
 313                                                  u8 invert);
 314
 315 enum cxd2880_ret cxd2880_tnrdmd_gpio_read(struct cxd2880_tnrdmd *tnr_dmd,
 316                                           u8 id, u8 *value);
 317
 318 enum cxd2880_ret cxd2880_tnrdmd_gpio_read_sub(struct cxd2880_tnrdmd *tnr_dmd,
 319                                               u8 id, u8 *value);
 320
 321 enum cxd2880_ret cxd2880_tnrdmd_gpio_write(struct cxd2880_tnrdmd *tnr_dmd,
 322                                            u8 id, u8 value);
 323
 324 enum cxd2880_ret cxd2880_tnrdmd_gpio_write_sub(struct cxd2880_tnrdmd *tnr_dmd,
 325                                                u8 id, u8 value);
 326
 327 enum cxd2880_ret cxd2880_tnrdmd_interrupt_read(struct cxd2880_tnrdmd *tnr_dmd,
 328                                                u16 *value);
 329
 330 enum cxd2880_ret cxd2880_tnrdmd_interrupt_clear(struct cxd2880_tnrdmd *tnr_dmd,
 331                                                 u16 value);
 332
 333 enum cxd2880_ret cxd2880_tnrdmd_ts_buf_clear(struct cxd2880_tnrdmd *tnr_dmd,
 334                                              u8 clear_overflow_flag,
 335                                              u8 clear_underflow_flag,
 336                                              u8 clear_buf);
 337
 338 enum cxd2880_ret cxd2880_tnrdmd_chip_id(struct cxd2880_tnrdmd *tnr_dmd,
 339                                         enum cxd2880_tnrdmd_chip_id *chip_id);
 340
 341 enum cxd2880_ret cxd2880_tnrdmd_set_and_save_reg_bits(struct cxd2880_tnrdmd
 342                                                       *tnr_dmd,
 343                                                       enum cxd2880_io_tgt tgt,
 344                                                       u8 bank, u8 address,
 345                                                       u8 value, u8 bit_mask);
 346
 347 enum cxd2880_ret cxd2880_tnrdmd_set_scan_mode(struct cxd2880_tnrdmd *tnr_dmd,
 348                                               enum cxd2880_dtv_sys sys,
 349                                               u8 scan_mode_end);
 350
 351 enum cxd2880_ret cxd2880_tnrdmd_set_pid_ftr(struct cxd2880_tnrdmd *tnr_dmd,
 352                                             struct cxd2880_tnrdmd_pid_ftr_cfg
 353                                             *pid_ftr_cfg);
 354
 355 enum cxd2880_ret cxd2880_tnrdmd_set_rf_lvl_cmpstn(struct cxd2880_tnrdmd
 356                                                   *tnr_dmd,
 357                                                   enum
 358                                                   cxd2880_ret(*rf_lvl_cmpstn)
 359                                                   (struct cxd2880_tnrdmd *,
 360                                                    int *));
 361
 362 enum cxd2880_ret cxd2880_tnrdmd_set_rf_lvl_cmpstn_sub(struct cxd2880_tnrdmd
 363                                                       *tnr_dmd,
 364                                                       enum
 365                                                       cxd2880_ret
 366                                                       (*rf_lvl_cmpstn)(struct
 367                                                                 cxd2880_tnrdmd
 368                                                                 *,
 369                                                                 int *));
 370
 371 enum cxd2880_ret cxd2880_tnrdmd_set_lna_thrs(struct cxd2880_tnrdmd *tnr_dmd,
 372                                              struct
 373                                              cxd2880_tnrdmd_lna_thrs_tbl_air
 374                                              *tbl_air,
 375                                              struct
 376                                              cxd2880_tnrdmd_lna_thrs_tbl_cable
 377                                              *tbl_cable);
 378
 379 enum cxd2880_ret cxd2880_tnrdmd_set_lna_thrs_sub(struct cxd2880_tnrdmd *tnr_dmd,
 380                                          struct
 381                                          cxd2880_tnrdmd_lna_thrs_tbl_air
 382                                          *tbl_air,
 383                                          struct
 384                                          cxd2880_tnrdmd_lna_thrs_tbl_cable
 385                                          *tbl_cable);
 386
 387 enum cxd2880_ret cxd2880_tnrdmd_set_ts_pin_high_low(struct cxd2880_tnrdmd
 388                                                     *tnr_dmd, u8 en, u8 value);
 389
 390 enum cxd2880_ret cxd2880_tnrdmd_set_ts_output(struct cxd2880_tnrdmd *tnr_dmd,
 391                                               u8 en);
 392
 393 enum cxd2880_ret slvt_freeze_reg(struct cxd2880_tnrdmd *tnr_dmd);
 394
 395 #endif