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This is the driver for Sony CXD2880 DVB-T2/T tuner + demodulator. It includes the...
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / cxd2880 / cxd2880_top.c
1 /*
2 * cxd2880_top.c
3 * Sony CXD2880 DVB-T2/T tuner + demodulator driver
4 *
5 * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2 of the License.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include <linux/spi/spi.h>
27
28 #include "dvb_frontend.h"
29
30 #include "cxd2880.h"
31 #include "cxd2880_tnrdmd_mon.h"
32 #include "cxd2880_tnrdmd_dvbt2_mon.h"
33 #include "cxd2880_tnrdmd_dvbt_mon.h"
34 #include "cxd2880_integ_dvbt2.h"
35 #include "cxd2880_integ_dvbt.h"
36 #include "cxd2880_devio_spi.h"
37 #include "cxd2880_spi_device.h"
38 #include "cxd2880_tnrdmd_driver_version.h"
39
40 struct cxd2880_priv {
41 struct cxd2880_tnrdmd tnrdmd;
42 struct spi_device *spi;
43 struct cxd2880_io regio;
44 struct cxd2880_spi_device spi_device;
45 struct cxd2880_spi cxd2880_spi;
46 struct cxd2880_dvbt_tune_param dvbt_tune_param;
47 struct cxd2880_dvbt2_tune_param dvbt2_tune_param;
48 struct mutex *spi_mutex; /* For SPI access exclusive control */
49 };
50
51 /*
52 * return value conversion table
53 */
54 static int return_tbl[] = {
55 0, /* CXD2880_RESULT_OK */
56 -EINVAL, /* CXD2880_RESULT_ERROR_ARG*/
57 -EIO, /* CXD2880_RESULT_ERROR_IO */
58 -EPERM, /* CXD2880_RESULT_ERROR_SW_STATE */
59 -EBUSY, /* CXD2880_RESULT_ERROR_HW_STATE */
60 -ETIME, /* CXD2880_RESULT_ERROR_TIMEOUT */
61 -EAGAIN, /* CXD2880_RESULT_ERROR_UNLOCK */
62 -ERANGE, /* CXD2880_RESULT_ERROR_RANGE */
63 -EOPNOTSUPP, /* CXD2880_RESULT_ERROR_NOSUPPORT */
64 -ECANCELED, /* CXD2880_RESULT_ERROR_CANCEL */
65 -EPERM, /* CXD2880_RESULT_ERROR_OTHER */
66 -EOVERFLOW, /* CXD2880_RESULT_ERROR_OVERFLOW */
67 0, /* CXD2880_RESULT_OK_CONFIRM */
68 };
69
70 static enum cxd2880_ret cxd2880_pre_bit_err_t(
71 struct cxd2880_tnrdmd *tnrdmd, u32 *pre_bit_err,
72 u32 *pre_bit_count)
73 {
74 u8 rdata[2];
75
76 if ((!tnrdmd) || (!pre_bit_err) || (!pre_bit_count))
77 return CXD2880_RESULT_ERROR_ARG;
78
79 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
80 return CXD2880_RESULT_ERROR_ARG;
81
82 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
83 return CXD2880_RESULT_ERROR_SW_STATE;
84
85 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
86 return CXD2880_RESULT_ERROR_SW_STATE;
87
88 if (slvt_freeze_reg(tnrdmd) != CXD2880_RESULT_OK)
89 return CXD2880_RESULT_ERROR_IO;
90
91 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
92 0x00, 0x10) != CXD2880_RESULT_OK) {
93 slvt_unfreeze_reg(tnrdmd);
94 return CXD2880_RESULT_ERROR_IO;
95 }
96
97 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
98 0x39, rdata, 1) != CXD2880_RESULT_OK) {
99 slvt_unfreeze_reg(tnrdmd);
100 return CXD2880_RESULT_ERROR_IO;
101 }
102
103 if ((rdata[0] & 0x01) == 0) {
104 slvt_unfreeze_reg(tnrdmd);
105 return CXD2880_RESULT_ERROR_HW_STATE;
106 }
107
108 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
109 0x22, rdata, 2) != CXD2880_RESULT_OK) {
110 slvt_unfreeze_reg(tnrdmd);
111 return CXD2880_RESULT_ERROR_IO;
112 }
113
114 *pre_bit_err = (rdata[0] << 8) | rdata[1];
115
116 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
117 0x6F, rdata, 1) != CXD2880_RESULT_OK) {
118 slvt_unfreeze_reg(tnrdmd);
119 return CXD2880_RESULT_ERROR_IO;
120 }
121
122 slvt_unfreeze_reg(tnrdmd);
123
124 *pre_bit_count = ((rdata[0] & 0x07) == 0) ?
125 256 : (0x1000 << (rdata[0] & 0x07));
126
127 return CXD2880_RESULT_OK;
128 }
129
130 static enum cxd2880_ret cxd2880_pre_bit_err_t2(
131 struct cxd2880_tnrdmd *tnrdmd, u32 *pre_bit_err,
132 u32 *pre_bit_count)
133 {
134 u32 period_exp = 0;
135 u32 n_ldpc = 0;
136 u8 data[5];
137
138 if ((!tnrdmd) || (!pre_bit_err) || (!pre_bit_count))
139 return CXD2880_RESULT_ERROR_ARG;
140
141 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
142 return CXD2880_RESULT_ERROR_ARG;
143
144 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
145 return CXD2880_RESULT_ERROR_SW_STATE;
146
147 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
148 return CXD2880_RESULT_ERROR_SW_STATE;
149
150 if (slvt_freeze_reg(tnrdmd) != CXD2880_RESULT_OK)
151 return CXD2880_RESULT_ERROR_IO;
152
153 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
154 0x00, 0x0B) != CXD2880_RESULT_OK) {
155 slvt_unfreeze_reg(tnrdmd);
156 return CXD2880_RESULT_ERROR_IO;
157 }
158
159 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
160 0x3C, data, sizeof(data))
161 != CXD2880_RESULT_OK) {
162 slvt_unfreeze_reg(tnrdmd);
163 return CXD2880_RESULT_ERROR_IO;
164 }
165
166 if (!(data[0] & 0x01)) {
167 slvt_unfreeze_reg(tnrdmd);
168 return CXD2880_RESULT_ERROR_HW_STATE;
169 }
170 *pre_bit_err =
171 ((data[1] & 0x0F) << 24) | (data[2] << 16) | (data[3] << 8) | data[4];
172
173 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
174 0xA0, data, 1) != CXD2880_RESULT_OK) {
175 slvt_unfreeze_reg(tnrdmd);
176 return CXD2880_RESULT_ERROR_IO;
177 }
178
179 if (((enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03)) ==
180 CXD2880_DVBT2_FEC_LDPC_16K)
181 n_ldpc = 16200;
182 else
183 n_ldpc = 64800;
184 slvt_unfreeze_reg(tnrdmd);
185
186 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
187 0x00, 0x20) != CXD2880_RESULT_OK)
188 return CXD2880_RESULT_ERROR_IO;
189
190 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
191 0x6F, data, 1) != CXD2880_RESULT_OK)
192 return CXD2880_RESULT_ERROR_IO;
193
194 period_exp = data[0] & 0x0F;
195
196 *pre_bit_count = (1U << period_exp) * n_ldpc;
197
198 return CXD2880_RESULT_OK;
199 }
200
201 static enum cxd2880_ret cxd2880_post_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
202 u32 *post_bit_err,
203 u32 *post_bit_count)
204 {
205 u8 rdata[3];
206 u32 bit_error = 0;
207 u32 period_exp = 0;
208
209 if ((!tnrdmd) || (!post_bit_err) || (!post_bit_count))
210 return CXD2880_RESULT_ERROR_ARG;
211
212 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
213 return CXD2880_RESULT_ERROR_ARG;
214
215 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
216 return CXD2880_RESULT_ERROR_SW_STATE;
217
218 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
219 return CXD2880_RESULT_ERROR_SW_STATE;
220
221 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
222 0x00, 0x0D) != CXD2880_RESULT_OK)
223 return CXD2880_RESULT_ERROR_IO;
224
225 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
226 0x15, rdata, 3) != CXD2880_RESULT_OK)
227 return CXD2880_RESULT_ERROR_IO;
228
229 if ((rdata[0] & 0x40) == 0)
230 return CXD2880_RESULT_ERROR_HW_STATE;
231
232 *post_bit_err = ((rdata[0] & 0x3F) << 16) | (rdata[1] << 8) | rdata[2];
233
234 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
235 0x00, 0x10) != CXD2880_RESULT_OK)
236 return CXD2880_RESULT_ERROR_IO;
237
238 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
239 0x60, rdata, 1) != CXD2880_RESULT_OK)
240 return CXD2880_RESULT_ERROR_IO;
241
242 period_exp = (rdata[0] & 0x1F);
243
244 if ((period_exp <= 11) && (bit_error > (1U << period_exp) * 204 * 8))
245 return CXD2880_RESULT_ERROR_HW_STATE;
246
247 if (period_exp == 11)
248 *post_bit_count = 3342336;
249 else
250 *post_bit_count = (1U << period_exp) * 204 * 81;
251
252 return CXD2880_RESULT_OK;
253 }
254
255 static enum cxd2880_ret cxd2880_post_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
256 u32 *post_bit_err,
257 u32 *post_bit_count)
258 {
259 u32 period_exp = 0;
260 u32 n_bch = 0;
261
262 if ((!tnrdmd) || (!post_bit_err) || (!post_bit_count))
263 return CXD2880_RESULT_ERROR_ARG;
264
265 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
266 return CXD2880_RESULT_ERROR_ARG;
267
268 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
269 return CXD2880_RESULT_ERROR_SW_STATE;
270
271 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
272 return CXD2880_RESULT_ERROR_SW_STATE;
273
274 {
275 u8 data[3];
276 enum cxd2880_dvbt2_plp_fec plp_fec_type =
277 CXD2880_DVBT2_FEC_LDPC_16K;
278 enum cxd2880_dvbt2_plp_code_rate plp_code_rate =
279 CXD2880_DVBT2_R1_2;
280
281 static const u16 n_bch_bits_lookup[2][8] = {
282 {7200, 9720, 10800, 11880, 12600, 13320, 5400, 6480},
283 {32400, 38880, 43200, 48600, 51840, 54000, 21600, 25920}
284 };
285
286 if (slvt_freeze_reg(tnrdmd) != CXD2880_RESULT_OK)
287 return CXD2880_RESULT_ERROR_IO;
288
289 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
290 0x00, 0x0B) != CXD2880_RESULT_OK) {
291 slvt_unfreeze_reg(tnrdmd);
292 return CXD2880_RESULT_ERROR_IO;
293 }
294
295 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
296 0x15, data, 3) != CXD2880_RESULT_OK) {
297 slvt_unfreeze_reg(tnrdmd);
298 return CXD2880_RESULT_ERROR_IO;
299 }
300
301 if (!(data[0] & 0x40)) {
302 slvt_unfreeze_reg(tnrdmd);
303 return CXD2880_RESULT_ERROR_HW_STATE;
304 }
305
306 *post_bit_err =
307 ((data[0] & 0x3F) << 16) | (data[1] << 8) | data[2];
308
309 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
310 0x9D, data, 1) != CXD2880_RESULT_OK) {
311 slvt_unfreeze_reg(tnrdmd);
312 return CXD2880_RESULT_ERROR_IO;
313 }
314
315 plp_code_rate =
316 (enum cxd2880_dvbt2_plp_code_rate)(data[0] & 0x07);
317
318 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
319 0xA0, data, 1) != CXD2880_RESULT_OK) {
320 slvt_unfreeze_reg(tnrdmd);
321 return CXD2880_RESULT_ERROR_IO;
322 }
323
324 plp_fec_type = (enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03);
325
326 slvt_unfreeze_reg(tnrdmd);
327
328 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
329 0x00, 0x20) != CXD2880_RESULT_OK)
330 return CXD2880_RESULT_ERROR_IO;
331
332 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
333 0x72, data, 1) != CXD2880_RESULT_OK)
334 return CXD2880_RESULT_ERROR_IO;
335
336 period_exp = data[0] & 0x0F;
337
338 if ((plp_fec_type > CXD2880_DVBT2_FEC_LDPC_64K) ||
339 (plp_code_rate > CXD2880_DVBT2_R2_5))
340 return CXD2880_RESULT_ERROR_HW_STATE;
341
342 n_bch = n_bch_bits_lookup[plp_fec_type][plp_code_rate];
343 }
344
345 if (*post_bit_err > ((1U << period_exp) * n_bch))
346 return CXD2880_RESULT_ERROR_HW_STATE;
347
348 *post_bit_count = (1U << period_exp) * n_bch;
349
350 return CXD2880_RESULT_OK;
351 }
352
353 static enum cxd2880_ret cxd2880_read_block_err_t(
354 struct cxd2880_tnrdmd *tnrdmd,
355 u32 *block_err,
356 u32 *block_count)
357 {
358 u8 rdata[3];
359
360 if ((!tnrdmd) || (!block_err) || (!block_count))
361 return CXD2880_RESULT_ERROR_ARG;
362
363 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
364 return CXD2880_RESULT_ERROR_ARG;
365
366 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
367 return CXD2880_RESULT_ERROR_SW_STATE;
368
369 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
370 return CXD2880_RESULT_ERROR_SW_STATE;
371
372 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
373 0x00, 0x0D) != CXD2880_RESULT_OK)
374 return CXD2880_RESULT_ERROR_IO;
375
376 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
377 0x18, rdata, 3) != CXD2880_RESULT_OK)
378 return CXD2880_RESULT_ERROR_IO;
379
380 if ((rdata[0] & 0x01) == 0)
381 return CXD2880_RESULT_ERROR_HW_STATE;
382
383 *block_err = (rdata[1] << 8) | rdata[2];
384
385 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
386 0x00, 0x10) != CXD2880_RESULT_OK)
387 return CXD2880_RESULT_ERROR_IO;
388
389 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
390 0x5C, rdata, 1) != CXD2880_RESULT_OK)
391 return CXD2880_RESULT_ERROR_IO;
392
393 *block_count = 1U << (rdata[0] & 0x0F);
394
395 if ((*block_count == 0) || (*block_err > *block_count))
396 return CXD2880_RESULT_ERROR_HW_STATE;
397
398 return CXD2880_RESULT_OK;
399 }
400
401 static enum cxd2880_ret cxd2880_read_block_err_t2(
402 struct cxd2880_tnrdmd *tnrdmd,
403 u32 *block_err,
404 u32 *block_count)
405 {
406 if ((!tnrdmd) || (!block_err) || (!block_count))
407 return CXD2880_RESULT_ERROR_ARG;
408
409 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
410 return CXD2880_RESULT_ERROR_ARG;
411
412 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
413 return CXD2880_RESULT_ERROR_SW_STATE;
414 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
415 return CXD2880_RESULT_ERROR_SW_STATE;
416
417 {
418 u8 rdata[3];
419
420 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
421 0x00, 0x0B) != CXD2880_RESULT_OK)
422 return CXD2880_RESULT_ERROR_IO;
423
424 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
425 0x18, rdata, 3) != CXD2880_RESULT_OK)
426 return CXD2880_RESULT_ERROR_IO;
427
428 if ((rdata[0] & 0x01) == 0)
429 return CXD2880_RESULT_ERROR_HW_STATE;
430
431 *block_err = (rdata[1] << 8) | rdata[2];
432
433 if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
434 0x00, 0x24) != CXD2880_RESULT_OK)
435 return CXD2880_RESULT_ERROR_IO;
436
437 if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
438 0xDC, rdata, 1) != CXD2880_RESULT_OK)
439 return CXD2880_RESULT_ERROR_IO;
440
441 *block_count = 1U << (rdata[0] & 0x0F);
442 }
443
444 if ((*block_count == 0) || (*block_err > *block_count))
445 return CXD2880_RESULT_ERROR_HW_STATE;
446
447 return CXD2880_RESULT_OK;
448 }
449
450 static void cxd2880_release(struct dvb_frontend *fe)
451 {
452 struct cxd2880_priv *priv = NULL;
453
454 if (!fe) {
455 pr_err("%s: invalid arg.\n", __func__);
456 return;
457 }
458 priv = (struct cxd2880_priv *)fe->demodulator_priv;
459 kfree(priv);
460 }
461
462 static int cxd2880_init(struct dvb_frontend *fe)
463 {
464 enum cxd2880_ret ret = CXD2880_RESULT_OK;
465 struct cxd2880_priv *priv = NULL;
466 struct cxd2880_tnrdmd_create_param create_param;
467
468 if (!fe) {
469 pr_err("%s: invalid arg.\n", __func__);
470 return -EINVAL;
471 }
472
473 priv = (struct cxd2880_priv *)fe->demodulator_priv;
474
475 create_param.ts_output_if = CXD2880_TNRDMD_TSOUT_IF_SPI;
476 create_param.xtal_share_type = CXD2880_TNRDMD_XTAL_SHARE_NONE;
477 create_param.en_internal_ldo = 1;
478 create_param.xosc_cap = 18;
479 create_param.xosc_i = 8;
480 create_param.stationary_use = 1;
481
482 mutex_lock(priv->spi_mutex);
483 if (priv->tnrdmd.io != &priv->regio) {
484 ret = cxd2880_tnrdmd_create(&priv->tnrdmd,
485 &priv->regio, &create_param);
486 if (ret != CXD2880_RESULT_OK) {
487 mutex_unlock(priv->spi_mutex);
488 dev_info(&priv->spi->dev,
489 "%s: cxd2880 tnrdmd create failed %d\n",
490 __func__, ret);
491 return return_tbl[ret];
492 }
493 }
494 ret = cxd2880_integ_init(&priv->tnrdmd);
495 if (ret != CXD2880_RESULT_OK) {
496 mutex_unlock(priv->spi_mutex);
497 dev_err(&priv->spi->dev, "%s: cxd2880 integ init failed %d\n",
498 __func__, ret);
499 return return_tbl[ret];
500 }
501 mutex_unlock(priv->spi_mutex);
502
503 dev_dbg(&priv->spi->dev, "%s: OK.\n", __func__);
504
505 return return_tbl[ret];
506 }
507
508 static int cxd2880_sleep(struct dvb_frontend *fe)
509 {
510 enum cxd2880_ret ret = CXD2880_RESULT_OK;
511 struct cxd2880_priv *priv = NULL;
512
513 if (!fe) {
514 pr_err("%s: inavlid arg\n", __func__);
515 return -EINVAL;
516 }
517
518 priv = (struct cxd2880_priv *)fe->demodulator_priv;
519
520 mutex_lock(priv->spi_mutex);
521 ret = cxd2880_tnrdmd_sleep(&priv->tnrdmd);
522 mutex_unlock(priv->spi_mutex);
523
524 dev_dbg(&priv->spi->dev, "%s: tnrdmd_sleep ret %d\n",
525 __func__, ret);
526
527 return return_tbl[ret];
528 }
529
530 static int cxd2880_read_signal_strength(struct dvb_frontend *fe,
531 u16 *strength)
532 {
533 enum cxd2880_ret ret = CXD2880_RESULT_OK;
534 struct cxd2880_priv *priv = NULL;
535 struct dtv_frontend_properties *c = NULL;
536 int level = 0;
537
538 if ((!fe) || (!strength)) {
539 pr_err("%s: inavlid arg\n", __func__);
540 return -EINVAL;
541 }
542
543 priv = (struct cxd2880_priv *)fe->demodulator_priv;
544 c = &fe->dtv_property_cache;
545
546 mutex_lock(priv->spi_mutex);
547 if ((c->delivery_system == SYS_DVBT) ||
548 (c->delivery_system == SYS_DVBT2)) {
549 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &level);
550 } else {
551 dev_dbg(&priv->spi->dev, "%s: invalid system\n", __func__);
552 mutex_unlock(priv->spi_mutex);
553 return -EINVAL;
554 }
555 mutex_unlock(priv->spi_mutex);
556
557 level /= 125;
558 /* -105dBm - -30dBm (-105000/125 = -840, -30000/125 = -240 */
559 level = clamp(level, -840, -240);
560 /* scale value to 0x0000-0xFFFF */
561 *strength = (u16)(((level + 840) * 0xFFFF) / (-240 + 840));
562
563 if (ret != CXD2880_RESULT_OK)
564 dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
565
566 return return_tbl[ret];
567 }
568
569 static int cxd2880_read_snr(struct dvb_frontend *fe, u16 *snr)
570 {
571 enum cxd2880_ret ret = CXD2880_RESULT_OK;
572 int snrvalue = 0;
573 struct cxd2880_priv *priv = NULL;
574 struct dtv_frontend_properties *c = NULL;
575
576 if ((!fe) || (!snr)) {
577 pr_err("%s: inavlid arg\n", __func__);
578 return -EINVAL;
579 }
580
581 priv = (struct cxd2880_priv *)fe->demodulator_priv;
582 c = &fe->dtv_property_cache;
583
584 mutex_lock(priv->spi_mutex);
585 if (c->delivery_system == SYS_DVBT) {
586 ret = cxd2880_tnrdmd_dvbt_mon_snr(&priv->tnrdmd,
587 &snrvalue);
588 } else if (c->delivery_system == SYS_DVBT2) {
589 ret = cxd2880_tnrdmd_dvbt2_mon_snr(&priv->tnrdmd,
590 &snrvalue);
591 } else {
592 dev_err(&priv->spi->dev, "%s: invalid system\n", __func__);
593 mutex_unlock(priv->spi_mutex);
594 return -EINVAL;
595 }
596 mutex_unlock(priv->spi_mutex);
597
598 if (snrvalue < 0)
599 snrvalue = 0;
600 *snr = (u16)snrvalue;
601
602 if (ret != CXD2880_RESULT_OK)
603 dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
604
605 return return_tbl[ret];
606 }
607
608 static int cxd2880_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
609 {
610 enum cxd2880_ret ret = CXD2880_RESULT_OK;
611 struct cxd2880_priv *priv = NULL;
612 struct dtv_frontend_properties *c = NULL;
613
614 if ((!fe) || (!ucblocks)) {
615 pr_err("%s: inavlid arg\n", __func__);
616 return -EINVAL;
617 }
618
619 priv = (struct cxd2880_priv *)fe->demodulator_priv;
620 c = &fe->dtv_property_cache;
621
622 mutex_lock(priv->spi_mutex);
623 if (c->delivery_system == SYS_DVBT) {
624 ret = cxd2880_tnrdmd_dvbt_mon_packet_error_number(
625 &priv->tnrdmd,
626 ucblocks);
627 } else if (c->delivery_system == SYS_DVBT2) {
628 ret = cxd2880_tnrdmd_dvbt2_mon_packet_error_number(
629 &priv->tnrdmd,
630 ucblocks);
631 } else {
632 dev_err(&priv->spi->dev, "%s: invlaid system\n", __func__);
633 mutex_unlock(priv->spi_mutex);
634 return -EINVAL;
635 }
636 mutex_unlock(priv->spi_mutex);
637
638 if (ret != CXD2880_RESULT_OK)
639 dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
640
641 return return_tbl[ret];
642 }
643
644 static int cxd2880_read_ber(struct dvb_frontend *fe, u32 *ber)
645 {
646 enum cxd2880_ret ret = CXD2880_RESULT_OK;
647 struct cxd2880_priv *priv = NULL;
648 struct dtv_frontend_properties *c = NULL;
649
650 if ((!fe) || (!ber)) {
651 pr_err("%s: inavlid arg\n", __func__);
652 return -EINVAL;
653 }
654
655 priv = (struct cxd2880_priv *)fe->demodulator_priv;
656 c = &fe->dtv_property_cache;
657
658 mutex_lock(priv->spi_mutex);
659 if (c->delivery_system == SYS_DVBT) {
660 ret = cxd2880_tnrdmd_dvbt_mon_pre_rsber(&priv->tnrdmd,
661 ber);
662 /* x100 to change unit.(10^7 -> 10^9 */
663 *ber *= 100;
664 } else if (c->delivery_system == SYS_DVBT2) {
665 ret = cxd2880_tnrdmd_dvbt2_mon_pre_bchber(&priv->tnrdmd,
666 ber);
667 } else {
668 dev_err(&priv->spi->dev, "%s: invlaid system\n", __func__);
669 mutex_unlock(priv->spi_mutex);
670 return -EINVAL;
671 }
672 mutex_unlock(priv->spi_mutex);
673
674 if (ret != CXD2880_RESULT_OK)
675 dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
676
677 return return_tbl[ret];
678 }
679
680 static int cxd2880_set_frontend(struct dvb_frontend *fe)
681 {
682 enum cxd2880_ret ret = CXD2880_RESULT_OK;
683 struct dtv_frontend_properties *c;
684 struct cxd2880_priv *priv;
685 enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
686
687 if (!fe) {
688 pr_err("%s: inavlid arg\n", __func__);
689 return -EINVAL;
690 }
691
692 priv = (struct cxd2880_priv *)fe->demodulator_priv;
693 c = &fe->dtv_property_cache;
694
695 switch (c->bandwidth_hz) {
696 case 1712000:
697 bw = CXD2880_DTV_BW_1_7_MHZ;
698 break;
699 case 5000000:
700 bw = CXD2880_DTV_BW_5_MHZ;
701 break;
702 case 6000000:
703 bw = CXD2880_DTV_BW_6_MHZ;
704 break;
705 case 7000000:
706 bw = CXD2880_DTV_BW_7_MHZ;
707 break;
708 case 8000000:
709 bw = CXD2880_DTV_BW_8_MHZ;
710 break;
711 default:
712 return -EINVAL;
713 }
714
715 dev_info(&priv->spi->dev, "%s: sys:%d freq:%d bw:%d\n", __func__,
716 c->delivery_system, c->frequency, bw);
717 mutex_lock(priv->spi_mutex);
718 if (c->delivery_system == SYS_DVBT) {
719 priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT;
720 priv->dvbt_tune_param.center_freq_khz = c->frequency / 1000;
721 priv->dvbt_tune_param.bandwidth = bw;
722 priv->dvbt_tune_param.profile = CXD2880_DVBT_PROFILE_HP;
723 ret = cxd2880_integ_dvbt_tune(&priv->tnrdmd,
724 &priv->dvbt_tune_param);
725 } else if (c->delivery_system == SYS_DVBT2) {
726 priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT2;
727 priv->dvbt2_tune_param.center_freq_khz = c->frequency / 1000;
728 priv->dvbt2_tune_param.bandwidth = bw;
729 priv->dvbt2_tune_param.data_plp_id = (u16)c->stream_id;
730 ret = cxd2880_integ_dvbt2_tune(&priv->tnrdmd,
731 &priv->dvbt2_tune_param);
732 } else {
733 dev_err(&priv->spi->dev, "%s: invalid system\n", __func__);
734 mutex_unlock(priv->spi_mutex);
735 return -EINVAL;
736 }
737 mutex_unlock(priv->spi_mutex);
738 dev_info(&priv->spi->dev, "%s: tune result %d\n", __func__, ret);
739
740 return return_tbl[ret];
741 }
742
743 static int cxd2880_read_status(struct dvb_frontend *fe,
744 enum fe_status *status)
745 {
746 enum cxd2880_ret ret = CXD2880_RESULT_OK;
747 u8 sync = 0;
748 u8 lock = 0;
749 u8 unlock = 0;
750 struct cxd2880_priv *priv = NULL;
751 struct dtv_frontend_properties *c = NULL;
752
753 if ((!fe) || (!status)) {
754 pr_err("%s: invalid arg\n", __func__);
755 return -EINVAL;
756 }
757
758 priv = (struct cxd2880_priv *)fe->demodulator_priv;
759 c = &fe->dtv_property_cache;
760 *status = 0;
761
762 if (priv->tnrdmd.state == CXD2880_TNRDMD_STATE_ACTIVE) {
763 mutex_lock(priv->spi_mutex);
764 if (c->delivery_system == SYS_DVBT) {
765 ret = cxd2880_tnrdmd_dvbt_mon_sync_stat(
766 &priv->tnrdmd,
767 &sync,
768 &lock,
769 &unlock);
770 } else if (c->delivery_system == SYS_DVBT2) {
771 ret = cxd2880_tnrdmd_dvbt2_mon_sync_stat(
772 &priv->tnrdmd,
773 &sync,
774 &lock,
775 &unlock);
776 } else {
777 dev_err(&priv->spi->dev,
778 "%s: invlaid system", __func__);
779 mutex_unlock(priv->spi_mutex);
780 return -EINVAL;
781 }
782
783 mutex_unlock(priv->spi_mutex);
784 if (ret != CXD2880_RESULT_OK) {
785 dev_err(&priv->spi->dev, "%s: failed. sys = %d\n",
786 __func__, priv->tnrdmd.sys);
787 return return_tbl[ret];
788 }
789
790 if (sync == 6) {
791 *status = FE_HAS_SIGNAL |
792 FE_HAS_CARRIER;
793 }
794 if (lock)
795 *status |= FE_HAS_VITERBI |
796 FE_HAS_SYNC |
797 FE_HAS_LOCK;
798 }
799
800 dev_dbg(&priv->spi->dev, "%s: status %d result %d\n", __func__,
801 *status, ret);
802
803 return return_tbl[CXD2880_RESULT_OK];
804 }
805
806 static int cxd2880_tune(struct dvb_frontend *fe,
807 bool retune,
808 unsigned int mode_flags,
809 unsigned int *delay,
810 enum fe_status *status)
811 {
812 int ret = 0;
813
814 if ((!fe) || (!delay) || (!status)) {
815 pr_err("%s: invalid arg.", __func__);
816 return -EINVAL;
817 }
818
819 if (retune) {
820 ret = cxd2880_set_frontend(fe);
821 if (ret) {
822 pr_err("%s: cxd2880_set_frontend failed %d\n",
823 __func__, ret);
824 return ret;
825 }
826 }
827
828 *delay = HZ / 5;
829
830 return cxd2880_read_status(fe, status);
831 }
832
833 static int cxd2880_get_frontend_t(struct dvb_frontend *fe,
834 struct dtv_frontend_properties *c)
835 {
836 enum cxd2880_ret ret = CXD2880_RESULT_OK;
837 int result = 0;
838 struct cxd2880_priv *priv = NULL;
839 enum cxd2880_dvbt_mode mode = CXD2880_DVBT_MODE_2K;
840 enum cxd2880_dvbt_guard guard = CXD2880_DVBT_GUARD_1_32;
841 struct cxd2880_dvbt_tpsinfo tps;
842 enum cxd2880_tnrdmd_spectrum_sense sense;
843 u16 snr = 0;
844 int strength = 0;
845 u32 pre_bit_err = 0, pre_bit_count = 0;
846 u32 post_bit_err = 0, post_bit_count = 0;
847 u32 block_err = 0, block_count = 0;
848
849 if ((!fe) || (!c)) {
850 pr_err("%s: invalid arg\n", __func__);
851 return -EINVAL;
852 }
853
854 priv = (struct cxd2880_priv *)fe->demodulator_priv;
855
856 mutex_lock(priv->spi_mutex);
857 ret = cxd2880_tnrdmd_dvbt_mon_mode_guard(&priv->tnrdmd,
858 &mode, &guard);
859 mutex_unlock(priv->spi_mutex);
860 if (ret == CXD2880_RESULT_OK) {
861 switch (mode) {
862 case CXD2880_DVBT_MODE_2K:
863 c->transmission_mode = TRANSMISSION_MODE_2K;
864 break;
865 case CXD2880_DVBT_MODE_8K:
866 c->transmission_mode = TRANSMISSION_MODE_8K;
867 break;
868 default:
869 c->transmission_mode = TRANSMISSION_MODE_2K;
870 dev_err(&priv->spi->dev, "%s: get invalid mode %d\n",
871 __func__, mode);
872 break;
873 }
874 switch (guard) {
875 case CXD2880_DVBT_GUARD_1_32:
876 c->guard_interval = GUARD_INTERVAL_1_32;
877 break;
878 case CXD2880_DVBT_GUARD_1_16:
879 c->guard_interval = GUARD_INTERVAL_1_16;
880 break;
881 case CXD2880_DVBT_GUARD_1_8:
882 c->guard_interval = GUARD_INTERVAL_1_8;
883 break;
884 case CXD2880_DVBT_GUARD_1_4:
885 c->guard_interval = GUARD_INTERVAL_1_4;
886 break;
887 default:
888 c->guard_interval = GUARD_INTERVAL_1_32;
889 dev_err(&priv->spi->dev, "%s: get invalid guard %d\n",
890 __func__, guard);
891 break;
892 }
893 } else {
894 c->transmission_mode = TRANSMISSION_MODE_2K;
895 c->guard_interval = GUARD_INTERVAL_1_32;
896 dev_dbg(&priv->spi->dev,
897 "%s: ModeGuard err %d\n", __func__, ret);
898 }
899
900 mutex_lock(priv->spi_mutex);
901 ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd, &tps);
902 mutex_unlock(priv->spi_mutex);
903 if (ret == CXD2880_RESULT_OK) {
904 switch (tps.hierarchy) {
905 case CXD2880_DVBT_HIERARCHY_NON:
906 c->hierarchy = HIERARCHY_NONE;
907 break;
908 case CXD2880_DVBT_HIERARCHY_1:
909 c->hierarchy = HIERARCHY_1;
910 break;
911 case CXD2880_DVBT_HIERARCHY_2:
912 c->hierarchy = HIERARCHY_2;
913 break;
914 case CXD2880_DVBT_HIERARCHY_4:
915 c->hierarchy = HIERARCHY_4;
916 break;
917 default:
918 c->hierarchy = HIERARCHY_NONE;
919 dev_err(&priv->spi->dev,
920 "%s: TPSInfo hierarchy invalid %d\n",
921 __func__, tps.hierarchy);
922 break;
923 }
924
925 switch (tps.rate_hp) {
926 case CXD2880_DVBT_CODERATE_1_2:
927 c->code_rate_HP = FEC_1_2;
928 break;
929 case CXD2880_DVBT_CODERATE_2_3:
930 c->code_rate_HP = FEC_2_3;
931 break;
932 case CXD2880_DVBT_CODERATE_3_4:
933 c->code_rate_HP = FEC_3_4;
934 break;
935 case CXD2880_DVBT_CODERATE_5_6:
936 c->code_rate_HP = FEC_5_6;
937 break;
938 case CXD2880_DVBT_CODERATE_7_8:
939 c->code_rate_HP = FEC_7_8;
940 break;
941 default:
942 c->code_rate_HP = FEC_NONE;
943 dev_err(&priv->spi->dev,
944 "%s: TPSInfo rateHP invalid %d\n",
945 __func__, tps.rate_hp);
946 break;
947 }
948 switch (tps.rate_lp) {
949 case CXD2880_DVBT_CODERATE_1_2:
950 c->code_rate_LP = FEC_1_2;
951 break;
952 case CXD2880_DVBT_CODERATE_2_3:
953 c->code_rate_LP = FEC_2_3;
954 break;
955 case CXD2880_DVBT_CODERATE_3_4:
956 c->code_rate_LP = FEC_3_4;
957 break;
958 case CXD2880_DVBT_CODERATE_5_6:
959 c->code_rate_LP = FEC_5_6;
960 break;
961 case CXD2880_DVBT_CODERATE_7_8:
962 c->code_rate_LP = FEC_7_8;
963 break;
964 default:
965 c->code_rate_LP = FEC_NONE;
966 dev_err(&priv->spi->dev,
967 "%s: TPSInfo rateLP invalid %d\n",
968 __func__, tps.rate_lp);
969 break;
970 }
971 switch (tps.constellation) {
972 case CXD2880_DVBT_CONSTELLATION_QPSK:
973 c->modulation = QPSK;
974 break;
975 case CXD2880_DVBT_CONSTELLATION_16QAM:
976 c->modulation = QAM_16;
977 break;
978 case CXD2880_DVBT_CONSTELLATION_64QAM:
979 c->modulation = QAM_64;
980 break;
981 default:
982 c->modulation = QPSK;
983 dev_err(&priv->spi->dev,
984 "%s: TPSInfo constellation invalid %d\n",
985 __func__, tps.constellation);
986 break;
987 }
988 } else {
989 c->hierarchy = HIERARCHY_NONE;
990 c->code_rate_HP = FEC_NONE;
991 c->code_rate_LP = FEC_NONE;
992 c->modulation = QPSK;
993 dev_dbg(&priv->spi->dev,
994 "%s: TPS info err %d\n", __func__, ret);
995 }
996
997 mutex_lock(priv->spi_mutex);
998 ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(&priv->tnrdmd, &sense);
999 mutex_unlock(priv->spi_mutex);
1000 if (ret == CXD2880_RESULT_OK) {
1001 switch (sense) {
1002 case CXD2880_TNRDMD_SPECTRUM_NORMAL:
1003 c->inversion = INVERSION_OFF;
1004 break;
1005 case CXD2880_TNRDMD_SPECTRUM_INV:
1006 c->inversion = INVERSION_ON;
1007 break;
1008 default:
1009 c->inversion = INVERSION_OFF;
1010 dev_err(&priv->spi->dev,
1011 "%s: spectrum sense invalid %d\n",
1012 __func__, sense);
1013 break;
1014 }
1015 } else {
1016 c->inversion = INVERSION_OFF;
1017 dev_dbg(&priv->spi->dev,
1018 "%s: spectrum_sense %d\n", __func__, ret);
1019 }
1020
1021 mutex_lock(priv->spi_mutex);
1022 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
1023 mutex_unlock(priv->spi_mutex);
1024 if (ret == CXD2880_RESULT_OK) {
1025 c->strength.len = 1;
1026 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1027 c->strength.stat[0].svalue = strength;
1028 } else {
1029 c->strength.len = 1;
1030 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1031 dev_dbg(&priv->spi->dev, "%s: mon_rf_lvl %d\n",
1032 __func__, result);
1033 }
1034
1035 result = cxd2880_read_snr(fe, &snr);
1036 if (!result) {
1037 c->cnr.len = 1;
1038 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1039 c->cnr.stat[0].svalue = snr;
1040 } else {
1041 c->cnr.len = 1;
1042 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1043 dev_dbg(&priv->spi->dev, "%s: read_snr %d\n", __func__, result);
1044 }
1045
1046 mutex_lock(priv->spi_mutex);
1047 ret = cxd2880_pre_bit_err_t(&priv->tnrdmd, &pre_bit_err,
1048 &pre_bit_count);
1049 mutex_unlock(priv->spi_mutex);
1050 if (ret == CXD2880_RESULT_OK) {
1051 c->pre_bit_error.len = 1;
1052 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1053 c->pre_bit_error.stat[0].uvalue = pre_bit_err;
1054 c->pre_bit_count.len = 1;
1055 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1056 c->pre_bit_count.stat[0].uvalue = pre_bit_count;
1057 } else {
1058 c->pre_bit_error.len = 1;
1059 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1060 c->pre_bit_count.len = 1;
1061 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1062 dev_dbg(&priv->spi->dev,
1063 "%s: pre_bit_error_t failed %d\n",
1064 __func__, ret);
1065 }
1066
1067 mutex_lock(priv->spi_mutex);
1068 ret = cxd2880_post_bit_err_t(&priv->tnrdmd,
1069 &post_bit_err, &post_bit_count);
1070 mutex_unlock(priv->spi_mutex);
1071 if (ret == CXD2880_RESULT_OK) {
1072 c->post_bit_error.len = 1;
1073 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1074 c->post_bit_error.stat[0].uvalue = post_bit_err;
1075 c->post_bit_count.len = 1;
1076 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1077 c->post_bit_count.stat[0].uvalue = post_bit_count;
1078 } else {
1079 c->post_bit_error.len = 1;
1080 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1081 c->post_bit_count.len = 1;
1082 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1083 dev_dbg(&priv->spi->dev,
1084 "%s: post_bit_err_t %d\n", __func__, ret);
1085 }
1086
1087 mutex_lock(priv->spi_mutex);
1088 ret = cxd2880_read_block_err_t(&priv->tnrdmd,
1089 &block_err, &block_count);
1090 mutex_unlock(priv->spi_mutex);
1091 if (ret == CXD2880_RESULT_OK) {
1092 c->block_error.len = 1;
1093 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1094 c->block_error.stat[0].uvalue = block_err;
1095 c->block_count.len = 1;
1096 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1097 c->block_count.stat[0].uvalue = block_count;
1098 } else {
1099 c->block_error.len = 1;
1100 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1101 c->block_count.len = 1;
1102 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1103 dev_dbg(&priv->spi->dev,
1104 "%s: read_block_err_t %d\n", __func__, ret);
1105 }
1106
1107 return 0;
1108 }
1109
1110 static int cxd2880_get_frontend_t2(struct dvb_frontend *fe,
1111 struct dtv_frontend_properties *c)
1112 {
1113 enum cxd2880_ret ret = CXD2880_RESULT_OK;
1114 int result = 0;
1115 struct cxd2880_priv *priv = NULL;
1116 struct cxd2880_dvbt2_l1pre l1pre;
1117 enum cxd2880_dvbt2_plp_code_rate coderate;
1118 enum cxd2880_dvbt2_plp_constell qam;
1119 enum cxd2880_tnrdmd_spectrum_sense sense;
1120 u16 snr = 0;
1121 int strength = 0;
1122 u32 pre_bit_err = 0, pre_bit_count = 0;
1123 u32 post_bit_err = 0, post_bit_count = 0;
1124 u32 block_err = 0, block_count = 0;
1125
1126 if ((!fe) || (!c)) {
1127 pr_err("%s: invalid arg.\n", __func__);
1128 return -EINVAL;
1129 }
1130
1131 priv = (struct cxd2880_priv *)fe->demodulator_priv;
1132
1133 mutex_lock(priv->spi_mutex);
1134 ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
1135 mutex_unlock(priv->spi_mutex);
1136 if (ret == CXD2880_RESULT_OK) {
1137 switch (l1pre.fft_mode) {
1138 case CXD2880_DVBT2_M2K:
1139 c->transmission_mode = TRANSMISSION_MODE_2K;
1140 break;
1141 case CXD2880_DVBT2_M8K:
1142 c->transmission_mode = TRANSMISSION_MODE_8K;
1143 break;
1144 case CXD2880_DVBT2_M4K:
1145 c->transmission_mode = TRANSMISSION_MODE_4K;
1146 break;
1147 case CXD2880_DVBT2_M1K:
1148 c->transmission_mode = TRANSMISSION_MODE_1K;
1149 break;
1150 case CXD2880_DVBT2_M16K:
1151 c->transmission_mode = TRANSMISSION_MODE_16K;
1152 break;
1153 case CXD2880_DVBT2_M32K:
1154 c->transmission_mode = TRANSMISSION_MODE_32K;
1155 break;
1156 default:
1157 c->transmission_mode = TRANSMISSION_MODE_2K;
1158 dev_err(&priv->spi->dev,
1159 "%s: L1Pre fft_mode invalid %d\n",
1160 __func__, l1pre.fft_mode);
1161 break;
1162 }
1163 switch (l1pre.gi) {
1164 case CXD2880_DVBT2_G1_32:
1165 c->guard_interval = GUARD_INTERVAL_1_32;
1166 break;
1167 case CXD2880_DVBT2_G1_16:
1168 c->guard_interval = GUARD_INTERVAL_1_16;
1169 break;
1170 case CXD2880_DVBT2_G1_8:
1171 c->guard_interval = GUARD_INTERVAL_1_8;
1172 break;
1173 case CXD2880_DVBT2_G1_4:
1174 c->guard_interval = GUARD_INTERVAL_1_4;
1175 break;
1176 case CXD2880_DVBT2_G1_128:
1177 c->guard_interval = GUARD_INTERVAL_1_128;
1178 break;
1179 case CXD2880_DVBT2_G19_128:
1180 c->guard_interval = GUARD_INTERVAL_19_128;
1181 break;
1182 case CXD2880_DVBT2_G19_256:
1183 c->guard_interval = GUARD_INTERVAL_19_256;
1184 break;
1185 default:
1186 c->guard_interval = GUARD_INTERVAL_1_32;
1187 dev_err(&priv->spi->dev,
1188 "%s: L1Pre gi invalid %d\n",
1189 __func__, l1pre.gi);
1190 break;
1191 }
1192 } else {
1193 c->transmission_mode = TRANSMISSION_MODE_2K;
1194 c->guard_interval = GUARD_INTERVAL_1_32;
1195 dev_dbg(&priv->spi->dev,
1196 "%s: L1Pre err %d\n", __func__, ret);
1197 }
1198
1199 mutex_lock(priv->spi_mutex);
1200 ret = cxd2880_tnrdmd_dvbt2_mon_code_rate(&priv->tnrdmd,
1201 CXD2880_DVBT2_PLP_DATA,
1202 &coderate);
1203 mutex_unlock(priv->spi_mutex);
1204 if (ret == CXD2880_RESULT_OK) {
1205 switch (coderate) {
1206 case CXD2880_DVBT2_R1_2:
1207 c->fec_inner = FEC_1_2;
1208 break;
1209 case CXD2880_DVBT2_R3_5:
1210 c->fec_inner = FEC_3_5;
1211 break;
1212 case CXD2880_DVBT2_R2_3:
1213 c->fec_inner = FEC_2_3;
1214 break;
1215 case CXD2880_DVBT2_R3_4:
1216 c->fec_inner = FEC_3_4;
1217 break;
1218 case CXD2880_DVBT2_R4_5:
1219 c->fec_inner = FEC_4_5;
1220 break;
1221 case CXD2880_DVBT2_R5_6:
1222 c->fec_inner = FEC_5_6;
1223 break;
1224 default:
1225 c->fec_inner = FEC_NONE;
1226 dev_err(&priv->spi->dev,
1227 "%s: CodeRate invalid %d\n",
1228 __func__, coderate);
1229 break;
1230 }
1231 } else {
1232 c->fec_inner = FEC_NONE;
1233 dev_dbg(&priv->spi->dev, "%s: CodeRate %d\n", __func__, ret);
1234 }
1235
1236 mutex_lock(priv->spi_mutex);
1237 ret = cxd2880_tnrdmd_dvbt2_mon_qam(&priv->tnrdmd,
1238 CXD2880_DVBT2_PLP_DATA,
1239 &qam);
1240 mutex_unlock(priv->spi_mutex);
1241 if (ret == CXD2880_RESULT_OK) {
1242 switch (qam) {
1243 case CXD2880_DVBT2_QPSK:
1244 c->modulation = QPSK;
1245 break;
1246 case CXD2880_DVBT2_QAM16:
1247 c->modulation = QAM_16;
1248 break;
1249 case CXD2880_DVBT2_QAM64:
1250 c->modulation = QAM_64;
1251 break;
1252 case CXD2880_DVBT2_QAM256:
1253 c->modulation = QAM_256;
1254 break;
1255 default:
1256 c->modulation = QPSK;
1257 dev_err(&priv->spi->dev,
1258 "%s: QAM invalid %d\n",
1259 __func__, qam);
1260 break;
1261 }
1262 } else {
1263 c->modulation = QPSK;
1264 dev_dbg(&priv->spi->dev, "%s: QAM %d\n", __func__, ret);
1265 }
1266
1267 mutex_lock(priv->spi_mutex);
1268 ret = cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(&priv->tnrdmd, &sense);
1269 mutex_unlock(priv->spi_mutex);
1270 if (ret == CXD2880_RESULT_OK) {
1271 switch (sense) {
1272 case CXD2880_TNRDMD_SPECTRUM_NORMAL:
1273 c->inversion = INVERSION_OFF;
1274 break;
1275 case CXD2880_TNRDMD_SPECTRUM_INV:
1276 c->inversion = INVERSION_ON;
1277 break;
1278 default:
1279 c->inversion = INVERSION_OFF;
1280 dev_err(&priv->spi->dev,
1281 "%s: spectrum sense invalid %d\n",
1282 __func__, sense);
1283 break;
1284 }
1285 } else {
1286 c->inversion = INVERSION_OFF;
1287 dev_dbg(&priv->spi->dev,
1288 "%s: SpectrumSense %d\n", __func__, ret);
1289 }
1290
1291 mutex_lock(priv->spi_mutex);
1292 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
1293 mutex_unlock(priv->spi_mutex);
1294 if (ret == CXD2880_RESULT_OK) {
1295 c->strength.len = 1;
1296 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1297 c->strength.stat[0].svalue = strength;
1298 } else {
1299 c->strength.len = 1;
1300 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1301 dev_dbg(&priv->spi->dev,
1302 "%s: mon_rf_lvl %d\n", __func__, ret);
1303 }
1304
1305 result = cxd2880_read_snr(fe, &snr);
1306 if (!result) {
1307 c->cnr.len = 1;
1308 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1309 c->cnr.stat[0].svalue = snr;
1310 } else {
1311 c->cnr.len = 1;
1312 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1313 dev_dbg(&priv->spi->dev, "%s: read_snr %d\n", __func__, result);
1314 }
1315
1316 mutex_lock(priv->spi_mutex);
1317 ret = cxd2880_pre_bit_err_t2(&priv->tnrdmd,
1318 &pre_bit_err,
1319 &pre_bit_count);
1320 mutex_unlock(priv->spi_mutex);
1321 if (ret == CXD2880_RESULT_OK) {
1322 c->pre_bit_error.len = 1;
1323 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1324 c->pre_bit_error.stat[0].uvalue = pre_bit_err;
1325 c->pre_bit_count.len = 1;
1326 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1327 c->pre_bit_count.stat[0].uvalue = pre_bit_count;
1328 } else {
1329 c->pre_bit_error.len = 1;
1330 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1331 c->pre_bit_count.len = 1;
1332 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1333 dev_dbg(&priv->spi->dev,
1334 "%s: read_bit_err_t2 %d\n", __func__, ret);
1335 }
1336
1337 mutex_lock(priv->spi_mutex);
1338 ret = cxd2880_post_bit_err_t2(&priv->tnrdmd,
1339 &post_bit_err, &post_bit_count);
1340 mutex_unlock(priv->spi_mutex);
1341 if (ret == CXD2880_RESULT_OK) {
1342 c->post_bit_error.len = 1;
1343 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1344 c->post_bit_error.stat[0].uvalue = post_bit_err;
1345 c->post_bit_count.len = 1;
1346 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1347 c->post_bit_count.stat[0].uvalue = post_bit_count;
1348 } else {
1349 c->post_bit_error.len = 1;
1350 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1351 c->post_bit_count.len = 1;
1352 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1353 dev_dbg(&priv->spi->dev,
1354 "%s: post_bit_err_t2 %d\n", __func__, ret);
1355 }
1356
1357 mutex_lock(priv->spi_mutex);
1358 ret = cxd2880_read_block_err_t2(&priv->tnrdmd,
1359 &block_err, &block_count);
1360 mutex_unlock(priv->spi_mutex);
1361 if (ret == CXD2880_RESULT_OK) {
1362 c->block_error.len = 1;
1363 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1364 c->block_error.stat[0].uvalue = block_err;
1365 c->block_count.len = 1;
1366 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1367 c->block_count.stat[0].uvalue = block_count;
1368 } else {
1369 c->block_error.len = 1;
1370 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1371 c->block_count.len = 1;
1372 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1373 dev_dbg(&priv->spi->dev,
1374 "%s: read_block_err_t2 %d\n", __func__, ret);
1375 }
1376
1377 return 0;
1378 }
1379
1380 static int cxd2880_get_frontend(struct dvb_frontend *fe,
1381 struct dtv_frontend_properties *props)
1382 {
1383 struct cxd2880_priv *priv = NULL;
1384 int result = 0;
1385
1386 if ((!fe) || (!props)) {
1387 pr_err("%s: invalid arg.", __func__);
1388 return -EINVAL;
1389 }
1390
1391 priv = (struct cxd2880_priv *)fe->demodulator_priv;
1392
1393 dev_dbg(&priv->spi->dev, "%s: system=%d\n", __func__,
1394 fe->dtv_property_cache.delivery_system);
1395 switch (fe->dtv_property_cache.delivery_system) {
1396 case SYS_DVBT:
1397 result = cxd2880_get_frontend_t(fe, props);
1398 break;
1399 case SYS_DVBT2:
1400 result = cxd2880_get_frontend_t2(fe, props);
1401 break;
1402 default:
1403 result = -EINVAL;
1404 break;
1405 }
1406
1407 return result;
1408 }
1409
1410 static enum dvbfe_algo cxd2880_get_frontend_algo(struct dvb_frontend *fe)
1411 {
1412 return DVBFE_ALGO_HW;
1413 }
1414
1415 static struct dvb_frontend_ops cxd2880_dvbt_t2_ops;
1416
1417 struct dvb_frontend *cxd2880_attach(struct dvb_frontend *fe,
1418 struct cxd2880_config *cfg)
1419 {
1420 enum cxd2880_ret ret = CXD2880_RESULT_OK;
1421 enum cxd2880_tnrdmd_chip_id chipid =
1422 CXD2880_TNRDMD_CHIP_ID_UNKNOWN;
1423 static struct cxd2880_priv *priv;
1424 u8 data = 0;
1425
1426 if (!fe) {
1427 pr_err("%s: invalid arg.\n", __func__);
1428 return NULL;
1429 }
1430
1431 priv = kzalloc(sizeof(struct cxd2880_priv), GFP_KERNEL);
1432 if (!priv)
1433 return NULL;
1434
1435 priv->spi = cfg->spi;
1436 priv->spi_mutex = cfg->spi_mutex;
1437 priv->spi_device.spi = cfg->spi;
1438
1439 memcpy(&fe->ops, &cxd2880_dvbt_t2_ops,
1440 sizeof(struct dvb_frontend_ops));
1441
1442 ret = cxd2880_spi_device_initialize(&priv->spi_device,
1443 CXD2880_SPI_MODE_0,
1444 55000000);
1445 if (ret != CXD2880_RESULT_OK) {
1446 dev_err(&priv->spi->dev,
1447 "%s: spi_device_initialize failed. %d\n",
1448 __func__, ret);
1449 kfree(priv);
1450 return NULL;
1451 }
1452
1453 ret = cxd2880_spi_device_create_spi(&priv->cxd2880_spi,
1454 &priv->spi_device);
1455 if (ret != CXD2880_RESULT_OK) {
1456 dev_err(&priv->spi->dev,
1457 "%s: spi_device_create_spi failed. %d\n",
1458 __func__, ret);
1459 kfree(priv);
1460 return NULL;
1461 }
1462
1463 ret = cxd2880_io_spi_create(&priv->regio, &priv->cxd2880_spi, 0);
1464 if (ret != CXD2880_RESULT_OK) {
1465 dev_err(&priv->spi->dev,
1466 "%s: io_spi_create failed. %d\n", __func__, ret);
1467 kfree(priv);
1468 return NULL;
1469 }
1470 if (priv->regio.write_reg(&priv->regio, CXD2880_IO_TGT_SYS, 0x00, 0x00)
1471 != CXD2880_RESULT_OK) {
1472 dev_err(&priv->spi->dev,
1473 "%s: set bank to 0x00 failed.\n", __func__);
1474 kfree(priv);
1475 return NULL;
1476 }
1477 if (priv->regio.read_regs(&priv->regio,
1478 CXD2880_IO_TGT_SYS, 0xFD, &data, 1)
1479 != CXD2880_RESULT_OK) {
1480 dev_err(&priv->spi->dev,
1481 "%s: read chip id failed.\n", __func__);
1482 kfree(priv);
1483 return NULL;
1484 }
1485
1486 chipid = (enum cxd2880_tnrdmd_chip_id)data;
1487 if ((chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) &&
1488 (chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11)) {
1489 dev_err(&priv->spi->dev,
1490 "%s: chip id invalid.\n", __func__);
1491 kfree(priv);
1492 return NULL;
1493 }
1494
1495 fe->demodulator_priv = priv;
1496 dev_info(&priv->spi->dev,
1497 "CXD2880 driver version: Ver %s\n",
1498 CXD2880_TNRDMD_DRIVER_VERSION);
1499
1500 return fe;
1501 }
1502 EXPORT_SYMBOL(cxd2880_attach);
1503
1504 static struct dvb_frontend_ops cxd2880_dvbt_t2_ops = {
1505 .info = {
1506 .name = "Sony CXD2880",
1507 .frequency_min = 174000000,
1508 .frequency_max = 862000000,
1509 .frequency_stepsize = 1000,
1510 .caps = FE_CAN_INVERSION_AUTO |
1511 FE_CAN_FEC_1_2 |
1512 FE_CAN_FEC_2_3 |
1513 FE_CAN_FEC_3_4 |
1514 FE_CAN_FEC_4_5 |
1515 FE_CAN_FEC_5_6 |
1516 FE_CAN_FEC_7_8 |
1517 FE_CAN_FEC_AUTO |
1518 FE_CAN_QPSK |
1519 FE_CAN_QAM_16 |
1520 FE_CAN_QAM_32 |
1521 FE_CAN_QAM_64 |
1522 FE_CAN_QAM_128 |
1523 FE_CAN_QAM_256 |
1524 FE_CAN_QAM_AUTO |
1525 FE_CAN_TRANSMISSION_MODE_AUTO |
1526 FE_CAN_GUARD_INTERVAL_AUTO |
1527 FE_CAN_2G_MODULATION |
1528 FE_CAN_RECOVER |
1529 FE_CAN_MUTE_TS,
1530 },
1531 .delsys = { SYS_DVBT, SYS_DVBT2 },
1532
1533 .release = cxd2880_release,
1534 .init = cxd2880_init,
1535 .sleep = cxd2880_sleep,
1536 .tune = cxd2880_tune,
1537 .set_frontend = cxd2880_set_frontend,
1538 .get_frontend = cxd2880_get_frontend,
1539 .read_status = cxd2880_read_status,
1540 .read_ber = cxd2880_read_ber,
1541 .read_signal_strength = cxd2880_read_signal_strength,
1542 .read_snr = cxd2880_read_snr,
1543 .read_ucblocks = cxd2880_read_ucblocks,
1544 .get_frontend_algo = cxd2880_get_frontend_algo,
1545 };
1546
1547 MODULE_DESCRIPTION(
1548 "Sony CXD2880 DVB-T2/T tuner + demodulator drvier");
1549 MODULE_AUTHOR("Sony Semiconductor Solutions Corporation");
1550 MODULE_LICENSE("GPL v2");
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