drivers/media/dvb-frontends/ds3000.c

   1 /*
   2     Montage Technology DS3000 - DVBS/S2 Demodulator driver
   3     Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
   4
   5     Copyright (C) 2009-2012 TurboSight.com
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/slab.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/firmware.h>
  28
  29 #include <media/dvb_frontend.h>
  30 #include "ts2020.h"
  31 #include "ds3000.h"
  32
  33 static int debug;
  34
  35 #define dprintk(args...) \
  36         do { \
  37                 if (debug) \
  38                         printk(args); \
  39         } while (0)
  40
  41 /* as of March 2009 current DS3000 firmware version is 1.78 */
  42 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
  43 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
  44
  45 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
  46
  47 /* Register values to initialise the demod in DVB-S mode */
  48 static u8 ds3000_dvbs_init_tab[] = {
  49         0x23, 0x05,
  50         0x08, 0x03,
  51         0x0c, 0x00,
  52         0x21, 0x54,
  53         0x25, 0x82,
  54         0x27, 0x31,
  55         0x30, 0x08,
  56         0x31, 0x40,
  57         0x32, 0x32,
  58         0x33, 0x35,
  59         0x35, 0xff,
  60         0x3a, 0x00,
  61         0x37, 0x10,
  62         0x38, 0x10,
  63         0x39, 0x02,
  64         0x42, 0x60,
  65         0x4a, 0x40,
  66         0x4b, 0x04,
  67         0x4d, 0x91,
  68         0x5d, 0xc8,
  69         0x50, 0x77,
  70         0x51, 0x77,
  71         0x52, 0x36,
  72         0x53, 0x36,
  73         0x56, 0x01,
  74         0x63, 0x43,
  75         0x64, 0x30,
  76         0x65, 0x40,
  77         0x68, 0x26,
  78         0x69, 0x4c,
  79         0x70, 0x20,
  80         0x71, 0x70,
  81         0x72, 0x04,
  82         0x73, 0x00,
  83         0x70, 0x40,
  84         0x71, 0x70,
  85         0x72, 0x04,
  86         0x73, 0x00,
  87         0x70, 0x60,
  88         0x71, 0x70,
  89         0x72, 0x04,
  90         0x73, 0x00,
  91         0x70, 0x80,
  92         0x71, 0x70,
  93         0x72, 0x04,
  94         0x73, 0x00,
  95         0x70, 0xa0,
  96         0x71, 0x70,
  97         0x72, 0x04,
  98         0x73, 0x00,
  99         0x70, 0x1f,
 100         0x76, 0x00,
 101         0x77, 0xd1,
 102         0x78, 0x0c,
 103         0x79, 0x80,
 104         0x7f, 0x04,
 105         0x7c, 0x00,
 106         0x80, 0x86,
 107         0x81, 0xa6,
 108         0x85, 0x04,
 109         0xcd, 0xf4,
 110         0x90, 0x33,
 111         0xa0, 0x44,
 112         0xc0, 0x18,
 113         0xc3, 0x10,
 114         0xc4, 0x08,
 115         0xc5, 0x80,
 116         0xc6, 0x80,
 117         0xc7, 0x0a,
 118         0xc8, 0x1a,
 119         0xc9, 0x80,
 120         0xfe, 0x92,
 121         0xe0, 0xf8,
 122         0xe6, 0x8b,
 123         0xd0, 0x40,
 124         0xf8, 0x20,
 125         0xfa, 0x0f,
 126         0xfd, 0x20,
 127         0xad, 0x20,
 128         0xae, 0x07,
 129         0xb8, 0x00,
 130 };
 131
 132 /* Register values to initialise the demod in DVB-S2 mode */
 133 static u8 ds3000_dvbs2_init_tab[] = {
 134         0x23, 0x0f,
 135         0x08, 0x07,
 136         0x0c, 0x00,
 137         0x21, 0x54,
 138         0x25, 0x82,
 139         0x27, 0x31,
 140         0x30, 0x08,
 141         0x31, 0x32,
 142         0x32, 0x32,
 143         0x33, 0x35,
 144         0x35, 0xff,
 145         0x3a, 0x00,
 146         0x37, 0x10,
 147         0x38, 0x10,
 148         0x39, 0x02,
 149         0x42, 0x60,
 150         0x4a, 0x80,
 151         0x4b, 0x04,
 152         0x4d, 0x81,
 153         0x5d, 0x88,
 154         0x50, 0x36,
 155         0x51, 0x36,
 156         0x52, 0x36,
 157         0x53, 0x36,
 158         0x63, 0x60,
 159         0x64, 0x10,
 160         0x65, 0x10,
 161         0x68, 0x04,
 162         0x69, 0x29,
 163         0x70, 0x20,
 164         0x71, 0x70,
 165         0x72, 0x04,
 166         0x73, 0x00,
 167         0x70, 0x40,
 168         0x71, 0x70,
 169         0x72, 0x04,
 170         0x73, 0x00,
 171         0x70, 0x60,
 172         0x71, 0x70,
 173         0x72, 0x04,
 174         0x73, 0x00,
 175         0x70, 0x80,
 176         0x71, 0x70,
 177         0x72, 0x04,
 178         0x73, 0x00,
 179         0x70, 0xa0,
 180         0x71, 0x70,
 181         0x72, 0x04,
 182         0x73, 0x00,
 183         0x70, 0x1f,
 184         0xa0, 0x44,
 185         0xc0, 0x08,
 186         0xc1, 0x10,
 187         0xc2, 0x08,
 188         0xc3, 0x10,
 189         0xc4, 0x08,
 190         0xc5, 0xf0,
 191         0xc6, 0xf0,
 192         0xc7, 0x0a,
 193         0xc8, 0x1a,
 194         0xc9, 0x80,
 195         0xca, 0x23,
 196         0xcb, 0x24,
 197         0xce, 0x74,
 198         0x90, 0x03,
 199         0x76, 0x80,
 200         0x77, 0x42,
 201         0x78, 0x0a,
 202         0x79, 0x80,
 203         0xad, 0x40,
 204         0xae, 0x07,
 205         0x7f, 0xd4,
 206         0x7c, 0x00,
 207         0x80, 0xa8,
 208         0x81, 0xda,
 209         0x7c, 0x01,
 210         0x80, 0xda,
 211         0x81, 0xec,
 212         0x7c, 0x02,
 213         0x80, 0xca,
 214         0x81, 0xeb,
 215         0x7c, 0x03,
 216         0x80, 0xba,
 217         0x81, 0xdb,
 218         0x85, 0x08,
 219         0x86, 0x00,
 220         0x87, 0x02,
 221         0x89, 0x80,
 222         0x8b, 0x44,
 223         0x8c, 0xaa,
 224         0x8a, 0x10,
 225         0xba, 0x00,
 226         0xf5, 0x04,
 227         0xfe, 0x44,
 228         0xd2, 0x32,
 229         0xb8, 0x00,
 230 };
 231
 232 struct ds3000_state {
 233         struct i2c_adapter *i2c;
 234         const struct ds3000_config *config;
 235         struct dvb_frontend frontend;
 236         /* previous uncorrected block counter for DVB-S2 */
 237         u16 prevUCBS2;
 238 };
 239
 240 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
 241 {
 242         u8 buf[] = { reg, data };
 243         struct i2c_msg msg = { .addr = state->config->demod_address,
 244                 .flags = 0, .buf = buf, .len = 2 };
 245         int err;
 246
 247         dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
 248
 249         err = i2c_transfer(state->i2c, &msg, 1);
 250         if (err != 1) {
 251                 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
 252                        __func__, err, reg, data);
 253                 return -EREMOTEIO;
 254         }
 255
 256         return 0;
 257 }
 258
 259 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 260 {
 261         struct ds3000_state *state = fe->demodulator_priv;
 262
 263         if (enable)
 264                 ds3000_writereg(state, 0x03, 0x12);
 265         else
 266                 ds3000_writereg(state, 0x03, 0x02);
 267
 268         return 0;
 269 }
 270
 271 /* I2C write for 8k firmware load */
 272 static int ds3000_writeFW(struct ds3000_state *state, int reg,
 273                                 const u8 *data, u16 len)
 274 {
 275         int i, ret = 0;
 276         struct i2c_msg msg;
 277         u8 *buf;
 278
 279         buf = kmalloc(33, GFP_KERNEL);
 280         if (!buf)
 281                 return -ENOMEM;
 282
 283         *(buf) = reg;
 284
 285         msg.addr = state->config->demod_address;
 286         msg.flags = 0;
 287         msg.buf = buf;
 288         msg.len = 33;
 289
 290         for (i = 0; i < len; i += 32) {
 291                 memcpy(buf + 1, data + i, 32);
 292
 293                 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
 294
 295                 ret = i2c_transfer(state->i2c, &msg, 1);
 296                 if (ret != 1) {
 297                         printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n",
 298                                __func__, ret, reg);
 299                         ret = -EREMOTEIO;
 300                         goto error;
 301                 }
 302         }
 303         ret = 0;
 304
 305 error:
 306         kfree(buf);
 307
 308         return ret;
 309 }
 310
 311 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
 312 {
 313         int ret;
 314         u8 b0[] = { reg };
 315         u8 b1[] = { 0 };
 316         struct i2c_msg msg[] = {
 317                 {
 318                         .addr = state->config->demod_address,
 319                         .flags = 0,
 320                         .buf = b0,
 321                         .len = 1
 322                 }, {
 323                         .addr = state->config->demod_address,
 324                         .flags = I2C_M_RD,
 325                         .buf = b1,
 326                         .len = 1
 327                 }
 328         };
 329
 330         ret = i2c_transfer(state->i2c, msg, 2);
 331
 332         if (ret != 2) {
 333                 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
 334                 return ret;
 335         }
 336
 337         dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
 338
 339         return b1[0];
 340 }
 341
 342 static int ds3000_load_firmware(struct dvb_frontend *fe,
 343                                         const struct firmware *fw);
 344
 345 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
 346 {
 347         struct ds3000_state *state = fe->demodulator_priv;
 348         const struct firmware *fw;
 349         int ret = 0;
 350
 351         dprintk("%s()\n", __func__);
 352
 353         ret = ds3000_readreg(state, 0xb2);
 354         if (ret < 0)
 355                 return ret;
 356
 357         /* Load firmware */
 358         /* request the firmware, this will block until someone uploads it */
 359         printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
 360                                 DS3000_DEFAULT_FIRMWARE);
 361         ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
 362                                 state->i2c->dev.parent);
 363         printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
 364         if (ret) {
 365                 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
 366                        __func__);
 367                 return ret;
 368         }
 369
 370         ret = ds3000_load_firmware(fe, fw);
 371         if (ret)
 372                 printk("%s: Writing firmware to device failed\n", __func__);
 373
 374         release_firmware(fw);
 375
 376         dprintk("%s: Firmware upload %s\n", __func__,
 377                         ret == 0 ? "complete" : "failed");
 378
 379         return ret;
 380 }
 381
 382 static int ds3000_load_firmware(struct dvb_frontend *fe,
 383                                         const struct firmware *fw)
 384 {
 385         struct ds3000_state *state = fe->demodulator_priv;
 386         int ret = 0;
 387
 388         dprintk("%s\n", __func__);
 389         dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
 390                         fw->size,
 391                         fw->data[0],
 392                         fw->data[1],
 393                         fw->data[fw->size - 2],
 394                         fw->data[fw->size - 1]);
 395
 396         /* Begin the firmware load process */
 397         ds3000_writereg(state, 0xb2, 0x01);
 398         /* write the entire firmware */
 399         ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
 400         ds3000_writereg(state, 0xb2, 0x00);
 401
 402         return ret;
 403 }
 404
 405 static int ds3000_set_voltage(struct dvb_frontend *fe,
 406                               enum fe_sec_voltage voltage)
 407 {
 408         struct ds3000_state *state = fe->demodulator_priv;
 409         u8 data;
 410
 411         dprintk("%s(%d)\n", __func__, voltage);
 412
 413         data = ds3000_readreg(state, 0xa2);
 414         data |= 0x03; /* bit0 V/H, bit1 off/on */
 415
 416         switch (voltage) {
 417         case SEC_VOLTAGE_18:
 418                 data &= ~0x03;
 419                 break;
 420         case SEC_VOLTAGE_13:
 421                 data &= ~0x03;
 422                 data |= 0x01;
 423                 break;
 424         case SEC_VOLTAGE_OFF:
 425                 break;
 426         }
 427
 428         ds3000_writereg(state, 0xa2, data);
 429
 430         return 0;
 431 }
 432
 433 static int ds3000_read_status(struct dvb_frontend *fe, enum fe_status *status)
 434 {
 435         struct ds3000_state *state = fe->demodulator_priv;
 436         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 437         int lock;
 438
 439         *status = 0;
 440
 441         switch (c->delivery_system) {
 442         case SYS_DVBS:
 443                 lock = ds3000_readreg(state, 0xd1);
 444                 if ((lock & 0x07) == 0x07)
 445                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 446                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 447                                 FE_HAS_LOCK;
 448
 449                 break;
 450         case SYS_DVBS2:
 451                 lock = ds3000_readreg(state, 0x0d);
 452                 if ((lock & 0x8f) == 0x8f)
 453                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 454                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 455                                 FE_HAS_LOCK;
 456
 457                 break;
 458         default:
 459                 return -EINVAL;
 460         }
 461
 462         if (state->config->set_lock_led)
 463                 state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
 464
 465         dprintk("%s: status = 0x%02x\n", __func__, lock);
 466
 467         return 0;
 468 }
 469
 470 /* read DS3000 BER value */
 471 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
 472 {
 473         struct ds3000_state *state = fe->demodulator_priv;
 474         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 475         u8 data;
 476         u32 ber_reading, lpdc_frames;
 477
 478         dprintk("%s()\n", __func__);
 479
 480         switch (c->delivery_system) {
 481         case SYS_DVBS:
 482                 /* set the number of bytes checked during
 483                 BER estimation */
 484                 ds3000_writereg(state, 0xf9, 0x04);
 485                 /* read BER estimation status */
 486                 data = ds3000_readreg(state, 0xf8);
 487                 /* check if BER estimation is ready */
 488                 if ((data & 0x10) == 0) {
 489                         /* this is the number of error bits,
 490                         to calculate the bit error rate
 491                         divide to 8388608 */
 492                         *ber = (ds3000_readreg(state, 0xf7) << 8) |
 493                                 ds3000_readreg(state, 0xf6);
 494                         /* start counting error bits */
 495                         /* need to be set twice
 496                         otherwise it fails sometimes */
 497                         data |= 0x10;
 498                         ds3000_writereg(state, 0xf8, data);
 499                         ds3000_writereg(state, 0xf8, data);
 500                 } else
 501                         /* used to indicate that BER estimation
 502                         is not ready, i.e. BER is unknown */
 503                         *ber = 0xffffffff;
 504                 break;
 505         case SYS_DVBS2:
 506                 /* read the number of LPDC decoded frames */
 507                 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
 508                                 (ds3000_readreg(state, 0xd6) << 8) |
 509                                 ds3000_readreg(state, 0xd5);
 510                 /* read the number of packets with bad CRC */
 511                 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
 512                                 ds3000_readreg(state, 0xf7);
 513                 if (lpdc_frames > 750) {
 514                         /* clear LPDC frame counters */
 515                         ds3000_writereg(state, 0xd1, 0x01);
 516                         /* clear bad packets counter */
 517                         ds3000_writereg(state, 0xf9, 0x01);
 518                         /* enable bad packets counter */
 519                         ds3000_writereg(state, 0xf9, 0x00);
 520                         /* enable LPDC frame counters */
 521                         ds3000_writereg(state, 0xd1, 0x00);
 522                         *ber = ber_reading;
 523                 } else
 524                         /* used to indicate that BER estimation is not ready,
 525                         i.e. BER is unknown */
 526                         *ber = 0xffffffff;
 527                 break;
 528         default:
 529                 return -EINVAL;
 530         }
 531
 532         return 0;
 533 }
 534
 535 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
 536                                                 u16 *signal_strength)
 537 {
 538         if (fe->ops.tuner_ops.get_rf_strength)
 539                 fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
 540
 541         return 0;
 542 }
 543
 544 /* calculate DS3000 snr value in dB */
 545 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
 546 {
 547         struct ds3000_state *state = fe->demodulator_priv;
 548         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 549         u8 snr_reading, snr_value;
 550         u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
 551         static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
 552                 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
 553                 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
 554                 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
 555         };
 556         static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
 557                 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
 558                 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
 559                 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
 560                 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
 561                 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
 562                 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
 563                 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
 564                 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
 565                 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
 566                 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
 567                 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
 568                 0x49e9, 0x4a20, 0x4a57
 569         };
 570
 571         dprintk("%s()\n", __func__);
 572
 573         switch (c->delivery_system) {
 574         case SYS_DVBS:
 575                 snr_reading = ds3000_readreg(state, 0xff);
 576                 snr_reading /= 8;
 577                 if (snr_reading == 0)
 578                         *snr = 0x0000;
 579                 else {
 580                         if (snr_reading > 20)
 581                                 snr_reading = 20;
 582                         snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
 583                         /* cook the value to be suitable for szap-s2
 584                         human readable output */
 585                         *snr = snr_value * 8 * 655;
 586                 }
 587                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 588                                 snr_reading, *snr);
 589                 break;
 590         case SYS_DVBS2:
 591                 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
 592                                 (ds3000_readreg(state, 0x8d) << 4);
 593                 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
 594                 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
 595                 if (tmp == 0) {
 596                         *snr = 0x0000;
 597                         return 0;
 598                 }
 599                 if (dvbs2_noise_reading == 0) {
 600                         snr_value = 0x0013;
 601                         /* cook the value to be suitable for szap-s2
 602                         human readable output */
 603                         *snr = 0xffff;
 604                         return 0;
 605                 }
 606                 if (tmp > dvbs2_noise_reading) {
 607                         snr_reading = tmp / dvbs2_noise_reading;
 608                         if (snr_reading > 80)
 609                                 snr_reading = 80;
 610                         snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
 611                         /* cook the value to be suitable for szap-s2
 612                         human readable output */
 613                         *snr = snr_value * 5 * 655;
 614                 } else {
 615                         snr_reading = dvbs2_noise_reading / tmp;
 616                         if (snr_reading > 80)
 617                                 snr_reading = 80;
 618                         *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
 619                 }
 620                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 621                                 snr_reading, *snr);
 622                 break;
 623         default:
 624                 return -EINVAL;
 625         }
 626
 627         return 0;
 628 }
 629
 630 /* read DS3000 uncorrected blocks */
 631 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 632 {
 633         struct ds3000_state *state = fe->demodulator_priv;
 634         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 635         u8 data;
 636         u16 _ucblocks;
 637
 638         dprintk("%s()\n", __func__);
 639
 640         switch (c->delivery_system) {
 641         case SYS_DVBS:
 642                 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
 643                                 ds3000_readreg(state, 0xf4);
 644                 data = ds3000_readreg(state, 0xf8);
 645                 /* clear packet counters */
 646                 data &= ~0x20;
 647                 ds3000_writereg(state, 0xf8, data);
 648                 /* enable packet counters */
 649                 data |= 0x20;
 650                 ds3000_writereg(state, 0xf8, data);
 651                 break;
 652         case SYS_DVBS2:
 653                 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
 654                                 ds3000_readreg(state, 0xe1);
 655                 if (_ucblocks > state->prevUCBS2)
 656                         *ucblocks = _ucblocks - state->prevUCBS2;
 657                 else
 658                         *ucblocks = state->prevUCBS2 - _ucblocks;
 659                 state->prevUCBS2 = _ucblocks;
 660                 break;
 661         default:
 662                 return -EINVAL;
 663         }
 664
 665         return 0;
 666 }
 667
 668 static int ds3000_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
 669 {
 670         struct ds3000_state *state = fe->demodulator_priv;
 671         u8 data;
 672
 673         dprintk("%s(%d)\n", __func__, tone);
 674         if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
 675                 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
 676                 return -EINVAL;
 677         }
 678
 679         data = ds3000_readreg(state, 0xa2);
 680         data &= ~0xc0;
 681         ds3000_writereg(state, 0xa2, data);
 682
 683         switch (tone) {
 684         case SEC_TONE_ON:
 685                 dprintk("%s: setting tone on\n", __func__);
 686                 data = ds3000_readreg(state, 0xa1);
 687                 data &= ~0x43;
 688                 data |= 0x04;
 689                 ds3000_writereg(state, 0xa1, data);
 690                 break;
 691         case SEC_TONE_OFF:
 692                 dprintk("%s: setting tone off\n", __func__);
 693                 data = ds3000_readreg(state, 0xa2);
 694                 data |= 0x80;
 695                 ds3000_writereg(state, 0xa2, data);
 696                 break;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
 703                                 struct dvb_diseqc_master_cmd *d)
 704 {
 705         struct ds3000_state *state = fe->demodulator_priv;
 706         int i;
 707         u8 data;
 708
 709         /* Dump DiSEqC message */
 710         dprintk("%s(", __func__);
 711         for (i = 0 ; i < d->msg_len;) {
 712                 dprintk("0x%02x", d->msg[i]);
 713                 if (++i < d->msg_len)
 714                         dprintk(", ");
 715         }
 716
 717         /* enable DiSEqC message send pin */
 718         data = ds3000_readreg(state, 0xa2);
 719         data &= ~0xc0;
 720         ds3000_writereg(state, 0xa2, data);
 721
 722         /* DiSEqC message */
 723         for (i = 0; i < d->msg_len; i++)
 724                 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
 725
 726         data = ds3000_readreg(state, 0xa1);
 727         /* clear DiSEqC message length and status,
 728         enable DiSEqC message send */
 729         data &= ~0xf8;
 730         /* set DiSEqC mode, modulation active during 33 pulses,
 731         set DiSEqC message length */
 732         data |= ((d->msg_len - 1) << 3) | 0x07;
 733         ds3000_writereg(state, 0xa1, data);
 734
 735         /* wait up to 150ms for DiSEqC transmission to complete */
 736         for (i = 0; i < 15; i++) {
 737                 data = ds3000_readreg(state, 0xa1);
 738                 if ((data & 0x40) == 0)
 739                         break;
 740                 msleep(10);
 741         }
 742
 743         /* DiSEqC timeout after 150ms */
 744         if (i == 15) {
 745                 data = ds3000_readreg(state, 0xa1);
 746                 data &= ~0x80;
 747                 data |= 0x40;
 748                 ds3000_writereg(state, 0xa1, data);
 749
 750                 data = ds3000_readreg(state, 0xa2);
 751                 data &= ~0xc0;
 752                 data |= 0x80;
 753                 ds3000_writereg(state, 0xa2, data);
 754
 755                 return -ETIMEDOUT;
 756         }
 757
 758         data = ds3000_readreg(state, 0xa2);
 759         data &= ~0xc0;
 760         data |= 0x80;
 761         ds3000_writereg(state, 0xa2, data);
 762
 763         return 0;
 764 }
 765
 766 /* Send DiSEqC burst */
 767 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
 768                                     enum fe_sec_mini_cmd burst)
 769 {
 770         struct ds3000_state *state = fe->demodulator_priv;
 771         int i;
 772         u8 data;
 773
 774         dprintk("%s()\n", __func__);
 775
 776         data = ds3000_readreg(state, 0xa2);
 777         data &= ~0xc0;
 778         ds3000_writereg(state, 0xa2, data);
 779
 780         /* DiSEqC burst */
 781         if (burst == SEC_MINI_A)
 782                 /* Unmodulated tone burst */
 783                 ds3000_writereg(state, 0xa1, 0x02);
 784         else if (burst == SEC_MINI_B)
 785                 /* Modulated tone burst */
 786                 ds3000_writereg(state, 0xa1, 0x01);
 787         else
 788                 return -EINVAL;
 789
 790         msleep(13);
 791         for (i = 0; i < 5; i++) {
 792                 data = ds3000_readreg(state, 0xa1);
 793                 if ((data & 0x40) == 0)
 794                         break;
 795                 msleep(1);
 796         }
 797
 798         if (i == 5) {
 799                 data = ds3000_readreg(state, 0xa1);
 800                 data &= ~0x80;
 801                 data |= 0x40;
 802                 ds3000_writereg(state, 0xa1, data);
 803
 804                 data = ds3000_readreg(state, 0xa2);
 805                 data &= ~0xc0;
 806                 data |= 0x80;
 807                 ds3000_writereg(state, 0xa2, data);
 808
 809                 return -ETIMEDOUT;
 810         }
 811
 812         data = ds3000_readreg(state, 0xa2);
 813         data &= ~0xc0;
 814         data |= 0x80;
 815         ds3000_writereg(state, 0xa2, data);
 816
 817         return 0;
 818 }
 819
 820 static void ds3000_release(struct dvb_frontend *fe)
 821 {
 822         struct ds3000_state *state = fe->demodulator_priv;
 823
 824         if (state->config->set_lock_led)
 825                 state->config->set_lock_led(fe, 0);
 826
 827         dprintk("%s\n", __func__);
 828         kfree(state);
 829 }
 830
 831 static const struct dvb_frontend_ops ds3000_ops;
 832
 833 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
 834                                     struct i2c_adapter *i2c)
 835 {
 836         struct ds3000_state *state;
 837         int ret;
 838
 839         dprintk("%s\n", __func__);
 840
 841         /* allocate memory for the internal state */
 842         state = kzalloc(sizeof(*state), GFP_KERNEL);
 843         if (!state)
 844                 return NULL;
 845
 846         state->config = config;
 847         state->i2c = i2c;
 848         state->prevUCBS2 = 0;
 849
 850         /* check if the demod is present */
 851         ret = ds3000_readreg(state, 0x00) & 0xfe;
 852         if (ret != 0xe0) {
 853                 kfree(state);
 854                 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
 855                 return NULL;
 856         }
 857
 858         printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
 859                         ds3000_readreg(state, 0x02),
 860                         ds3000_readreg(state, 0x01));
 861
 862         memcpy(&state->frontend.ops, &ds3000_ops,
 863                         sizeof(struct dvb_frontend_ops));
 864         state->frontend.demodulator_priv = state;
 865
 866         /*
 867          * Some devices like T480 starts with voltage on. Be sure
 868          * to turn voltage off during init, as this can otherwise
 869          * interfere with Unicable SCR systems.
 870          */
 871         ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
 872         return &state->frontend;
 873 }
 874 EXPORT_SYMBOL(ds3000_attach);
 875
 876 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
 877                                         s32 carrier_offset_khz)
 878 {
 879         struct ds3000_state *state = fe->demodulator_priv;
 880         s32 tmp;
 881
 882         tmp = carrier_offset_khz;
 883         tmp *= 65536;
 884         tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
 885
 886         if (tmp < 0)
 887                 tmp += 65536;
 888
 889         ds3000_writereg(state, 0x5f, tmp >> 8);
 890         ds3000_writereg(state, 0x5e, tmp & 0xff);
 891
 892         return 0;
 893 }
 894
 895 static int ds3000_set_frontend(struct dvb_frontend *fe)
 896 {
 897         struct ds3000_state *state = fe->demodulator_priv;
 898         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 899
 900         int i;
 901         enum fe_status status;
 902         s32 offset_khz;
 903         u32 frequency;
 904         u16 value;
 905
 906         dprintk("%s() ", __func__);
 907
 908         if (state->config->set_ts_params)
 909                 state->config->set_ts_params(fe, 0);
 910         /* Tune */
 911         if (fe->ops.tuner_ops.set_params)
 912                 fe->ops.tuner_ops.set_params(fe);
 913
 914         /* ds3000 global reset */
 915         ds3000_writereg(state, 0x07, 0x80);
 916         ds3000_writereg(state, 0x07, 0x00);
 917         /* ds3000 build-in uC reset */
 918         ds3000_writereg(state, 0xb2, 0x01);
 919         /* ds3000 software reset */
 920         ds3000_writereg(state, 0x00, 0x01);
 921
 922         switch (c->delivery_system) {
 923         case SYS_DVBS:
 924                 /* initialise the demod in DVB-S mode */
 925                 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
 926                         ds3000_writereg(state,
 927                                 ds3000_dvbs_init_tab[i],
 928                                 ds3000_dvbs_init_tab[i + 1]);
 929                 value = ds3000_readreg(state, 0xfe);
 930                 value &= 0xc0;
 931                 value |= 0x1b;
 932                 ds3000_writereg(state, 0xfe, value);
 933                 break;
 934         case SYS_DVBS2:
 935                 /* initialise the demod in DVB-S2 mode */
 936                 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
 937                         ds3000_writereg(state,
 938                                 ds3000_dvbs2_init_tab[i],
 939                                 ds3000_dvbs2_init_tab[i + 1]);
 940                 if (c->symbol_rate >= 30000000)
 941                         ds3000_writereg(state, 0xfe, 0x54);
 942                 else
 943                         ds3000_writereg(state, 0xfe, 0x98);
 944                 break;
 945         default:
 946                 return -EINVAL;
 947         }
 948
 949         /* enable 27MHz clock output */
 950         ds3000_writereg(state, 0x29, 0x80);
 951         /* enable ac coupling */
 952         ds3000_writereg(state, 0x25, 0x8a);
 953
 954         if ((c->symbol_rate < ds3000_ops.info.symbol_rate_min) ||
 955                         (c->symbol_rate > ds3000_ops.info.symbol_rate_max)) {
 956                 dprintk("%s() symbol_rate %u out of range (%u ... %u)\n",
 957                                 __func__, c->symbol_rate,
 958                                 ds3000_ops.info.symbol_rate_min,
 959                                 ds3000_ops.info.symbol_rate_max);
 960                 return -EINVAL;
 961         }
 962
 963         /* enhance symbol rate performance */
 964         if ((c->symbol_rate / 1000) <= 5000) {
 965                 value = 29777 / (c->symbol_rate / 1000) + 1;
 966                 if (value % 2 != 0)
 967                         value++;
 968                 ds3000_writereg(state, 0xc3, 0x0d);
 969                 ds3000_writereg(state, 0xc8, value);
 970                 ds3000_writereg(state, 0xc4, 0x10);
 971                 ds3000_writereg(state, 0xc7, 0x0e);
 972         } else if ((c->symbol_rate / 1000) <= 10000) {
 973                 value = 92166 / (c->symbol_rate / 1000) + 1;
 974                 if (value % 2 != 0)
 975                         value++;
 976                 ds3000_writereg(state, 0xc3, 0x07);
 977                 ds3000_writereg(state, 0xc8, value);
 978                 ds3000_writereg(state, 0xc4, 0x09);
 979                 ds3000_writereg(state, 0xc7, 0x12);
 980         } else if ((c->symbol_rate / 1000) <= 20000) {
 981                 value = 64516 / (c->symbol_rate / 1000) + 1;
 982                 ds3000_writereg(state, 0xc3, value);
 983                 ds3000_writereg(state, 0xc8, 0x0e);
 984                 ds3000_writereg(state, 0xc4, 0x07);
 985                 ds3000_writereg(state, 0xc7, 0x18);
 986         } else {
 987                 value = 129032 / (c->symbol_rate / 1000) + 1;
 988                 ds3000_writereg(state, 0xc3, value);
 989                 ds3000_writereg(state, 0xc8, 0x0a);
 990                 ds3000_writereg(state, 0xc4, 0x05);
 991                 ds3000_writereg(state, 0xc7, 0x24);
 992         }
 993
 994         /* normalized symbol rate rounded to the closest integer */
 995         value = (((c->symbol_rate / 1000) << 16) +
 996                         (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
 997         ds3000_writereg(state, 0x61, value & 0x00ff);
 998         ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
 999
1000         /* co-channel interference cancellation disabled */
1001         ds3000_writereg(state, 0x56, 0x00);
1002
1003         /* equalizer disabled */
1004         ds3000_writereg(state, 0x76, 0x00);
1005
1006         /*ds3000_writereg(state, 0x08, 0x03);
1007         ds3000_writereg(state, 0xfd, 0x22);
1008         ds3000_writereg(state, 0x08, 0x07);
1009         ds3000_writereg(state, 0xfd, 0x42);
1010         ds3000_writereg(state, 0x08, 0x07);*/
1011
1012         if (state->config->ci_mode) {
1013                 switch (c->delivery_system) {
1014                 case SYS_DVBS:
1015                 default:
1016                         ds3000_writereg(state, 0xfd, 0x80);
1017                 break;
1018                 case SYS_DVBS2:
1019                         ds3000_writereg(state, 0xfd, 0x01);
1020                         break;
1021                 }
1022         }
1023
1024         /* ds3000 out of software reset */
1025         ds3000_writereg(state, 0x00, 0x00);
1026         /* start ds3000 build-in uC */
1027         ds3000_writereg(state, 0xb2, 0x00);
1028
1029         if (fe->ops.tuner_ops.get_frequency) {
1030                 fe->ops.tuner_ops.get_frequency(fe, &frequency);
1031                 offset_khz = frequency - c->frequency;
1032                 ds3000_set_carrier_offset(fe, offset_khz);
1033         }
1034
1035         for (i = 0; i < 30 ; i++) {
1036                 ds3000_read_status(fe, &status);
1037                 if (status & FE_HAS_LOCK)
1038                         break;
1039
1040                 msleep(10);
1041         }
1042
1043         return 0;
1044 }
1045
1046 static int ds3000_tune(struct dvb_frontend *fe,
1047                         bool re_tune,
1048                         unsigned int mode_flags,
1049                         unsigned int *delay,
1050                         enum fe_status *status)
1051 {
1052         if (re_tune) {
1053                 int ret = ds3000_set_frontend(fe);
1054                 if (ret)
1055                         return ret;
1056         }
1057
1058         *delay = HZ / 5;
1059
1060         return ds3000_read_status(fe, status);
1061 }
1062
1063 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1064 {
1065         struct ds3000_state *state = fe->demodulator_priv;
1066
1067         if (state->config->set_lock_led)
1068                 state->config->set_lock_led(fe, 0);
1069
1070         dprintk("%s()\n", __func__);
1071         return DVBFE_ALGO_HW;
1072 }
1073
1074 /*
1075  * Initialise or wake up device
1076  *
1077  * Power config will reset and load initial firmware if required
1078  */
1079 static int ds3000_initfe(struct dvb_frontend *fe)
1080 {
1081         struct ds3000_state *state = fe->demodulator_priv;
1082         int ret;
1083
1084         dprintk("%s()\n", __func__);
1085         /* hard reset */
1086         ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1087         msleep(1);
1088
1089         /* Load the firmware if required */
1090         ret = ds3000_firmware_ondemand(fe);
1091         if (ret != 0) {
1092                 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1093                 return ret;
1094         }
1095
1096         return 0;
1097 }
1098
1099 static const struct dvb_frontend_ops ds3000_ops = {
1100         .delsys = { SYS_DVBS, SYS_DVBS2 },
1101         .info = {
1102                 .name = "Montage Technology DS3000",
1103                 .frequency_min_hz =  950 * MHz,
1104                 .frequency_max_hz = 2150 * MHz,
1105                 .frequency_stepsize_hz = 1011 * kHz,
1106                 .frequency_tolerance_hz = 5 * MHz,
1107                 .symbol_rate_min = 1000000,
1108                 .symbol_rate_max = 45000000,
1109                 .caps = FE_CAN_INVERSION_AUTO |
1110                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1111                         FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1112                         FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1113                         FE_CAN_2G_MODULATION |
1114                         FE_CAN_QPSK | FE_CAN_RECOVER
1115         },
1116
1117         .release = ds3000_release,
1118
1119         .init = ds3000_initfe,
1120         .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
1121         .read_status = ds3000_read_status,
1122         .read_ber = ds3000_read_ber,
1123         .read_signal_strength = ds3000_read_signal_strength,
1124         .read_snr = ds3000_read_snr,
1125         .read_ucblocks = ds3000_read_ucblocks,
1126         .set_voltage = ds3000_set_voltage,
1127         .set_tone = ds3000_set_tone,
1128         .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1129         .diseqc_send_burst = ds3000_diseqc_send_burst,
1130         .get_frontend_algo = ds3000_get_algo,
1131
1132         .set_frontend = ds3000_set_frontend,
1133         .tune = ds3000_tune,
1134 };
1135
1136 module_param(debug, int, 0644);
1137 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1138
1139 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology DS3000 hardware");
1140 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
1141 MODULE_LICENSE("GPL");
1142 MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE);