drivers/media/dvb-frontends/itd1000.c

   1 /*
   2  *  Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
   3  *
   4  *  Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/delay.h>
  21 #include <linux/dvb/frontend.h>
  22 #include <linux/i2c.h>
  23 #include <linux/slab.h>
  24
  25 #include "dvb_frontend.h"
  26
  27 #include "itd1000.h"
  28 #include "itd1000_priv.h"
  29
  30 /* Max transfer size done by I2C transfer functions */
  31 #define MAX_XFER_SIZE  64
  32
  33 static int debug;
  34 module_param(debug, int, 0644);
  35 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
  36
  37 #define itd_dbg(args...)  do { \
  38         if (debug) { \
  39                 printk(KERN_DEBUG   "ITD1000: " args);\
  40         } \
  41 } while (0)
  42
  43 #define itd_warn(args...) do { \
  44         printk(KERN_WARNING "ITD1000: " args); \
  45 } while (0)
  46
  47 #define itd_info(args...) do { \
  48         printk(KERN_INFO    "ITD1000: " args); \
  49 } while (0)
  50
  51 /* don't write more than one byte with flexcop behind */
  52 static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
  53 {
  54         u8 buf[MAX_XFER_SIZE];
  55         struct i2c_msg msg = {
  56                 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
  57         };
  58
  59         if (1 + len > sizeof(buf)) {
  60                 printk(KERN_WARNING
  61                        "itd1000: i2c wr reg=%04x: len=%d is too big!\n",
  62                        reg, len);
  63                 return -EINVAL;
  64         }
  65
  66         buf[0] = reg;
  67         memcpy(&buf[1], v, len);
  68
  69         /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */
  70
  71         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
  72                 printk(KERN_WARNING "itd1000 I2C write failed\n");
  73                 return -EREMOTEIO;
  74         }
  75         return 0;
  76 }
  77
  78 static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
  79 {
  80         u8 val;
  81         struct i2c_msg msg[2] = {
  82                 { .addr = state->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },
  83                 { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
  84         };
  85
  86         /* ugly flexcop workaround */
  87         itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
  88
  89         if (i2c_transfer(state->i2c, msg, 2) != 2) {
  90                 itd_warn("itd1000 I2C read failed\n");
  91                 return -EREMOTEIO;
  92         }
  93         return val;
  94 }
  95
  96 static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
  97 {
  98         int ret = itd1000_write_regs(state, r, &v, 1);
  99         state->shadow[r] = v;
 100         return ret;
 101 }
 102
 103
 104 static struct {
 105         u32 symbol_rate;
 106         u8  pgaext  : 4; /* PLLFH */
 107         u8  bbgvmin : 4; /* BBGVMIN */
 108 } itd1000_lpf_pga[] = {
 109         {        0, 0x8, 0x3 },
 110         {  5200000, 0x8, 0x3 },
 111         { 12200000, 0x4, 0x3 },
 112         { 15400000, 0x2, 0x3 },
 113         { 19800000, 0x2, 0x3 },
 114         { 21500000, 0x2, 0x3 },
 115         { 24500000, 0x2, 0x3 },
 116         { 28400000, 0x2, 0x3 },
 117         { 33400000, 0x2, 0x3 },
 118         { 34400000, 0x1, 0x4 },
 119         { 34400000, 0x1, 0x4 },
 120         { 38400000, 0x1, 0x4 },
 121         { 38400000, 0x1, 0x4 },
 122         { 40400000, 0x1, 0x4 },
 123         { 45400000, 0x1, 0x4 },
 124 };
 125
 126 static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
 127 {
 128         u8 i;
 129         u8 con1    = itd1000_read_reg(state, CON1)    & 0xfd;
 130         u8 pllfh   = itd1000_read_reg(state, PLLFH)   & 0x0f;
 131         u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
 132         u8 bw      = itd1000_read_reg(state, BW)      & 0xf0;
 133
 134         itd_dbg("symbol_rate = %d\n", symbol_rate);
 135
 136         /* not sure what is that ? - starting to download the table */
 137         itd1000_write_reg(state, CON1, con1 | (1 << 1));
 138
 139         for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
 140                 if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
 141                         itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
 142                         itd1000_write_reg(state, PLLFH,   pllfh | (itd1000_lpf_pga[i].pgaext << 4));
 143                         itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
 144                         itd1000_write_reg(state, BW,      bw | (i & 0x0f));
 145                         break;
 146                 }
 147
 148         itd1000_write_reg(state, CON1, con1 | (0 << 1));
 149 }
 150
 151 static struct {
 152         u8 vcorg;
 153         u32 fmax_rg;
 154 } itd1000_vcorg[] = {
 155         {  1,  920000 },
 156         {  2,  971000 },
 157         {  3, 1031000 },
 158         {  4, 1091000 },
 159         {  5, 1171000 },
 160         {  6, 1281000 },
 161         {  7, 1381000 },
 162         {  8,  500000 },        /* this is intentional. */
 163         {  9, 1451000 },
 164         { 10, 1531000 },
 165         { 11, 1631000 },
 166         { 12, 1741000 },
 167         { 13, 1891000 },
 168         { 14, 2071000 },
 169         { 15, 2250000 },
 170 };
 171
 172 static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
 173 {
 174         u8 i;
 175         u8 gvbb_i2c     = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
 176         u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
 177         u8 adcout;
 178
 179         /* reserved bit again (reset ?) */
 180         itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
 181
 182         for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
 183                 if (freq_khz < itd1000_vcorg[i].fmax_rg) {
 184                         itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
 185                         msleep(1);
 186
 187                         adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
 188
 189                         itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
 190
 191                         if (adcout > 13) {
 192                                 if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
 193                                         itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
 194                         } else if (adcout < 2) {
 195                                 if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
 196                                         itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
 197                         }
 198                         break;
 199                 }
 200         }
 201 }
 202
 203 static const struct {
 204         u32 freq;
 205         u8 values[10]; /* RFTR, RFST1 - RFST9 */
 206 } itd1000_fre_values[] = {
 207         { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
 208         { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
 209         { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
 210         { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
 211         { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
 212         { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
 213         { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
 214         { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
 215         { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
 216         { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
 217 };
 218
 219
 220 #define FREF 16
 221
 222 static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
 223 {
 224         int i, j;
 225         u32 plln, pllf;
 226         u64 tmp;
 227
 228         plln = (freq_khz * 1000) / 2 / FREF;
 229
 230         /* Compute the factional part times 1000 */
 231         tmp  = plln % 1000000;
 232         plln /= 1000000;
 233
 234         tmp *= 1048576;
 235         do_div(tmp, 1000000);
 236         pllf = (u32) tmp;
 237
 238         state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
 239         itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
 240
 241         itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
 242         itd1000_write_reg(state, PLLNL, plln & 0xff);
 243         itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
 244         itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
 245         itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
 246
 247         for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
 248                 if (freq_khz <= itd1000_fre_values[i].freq) {
 249                         itd_dbg("fre_values: %d\n", i);
 250                         itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
 251                         for (j = 0; j < 9; j++)
 252                                 itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
 253                         break;
 254                 }
 255         }
 256
 257         itd1000_set_vco(state, freq_khz);
 258 }
 259
 260 static int itd1000_set_parameters(struct dvb_frontend *fe)
 261 {
 262         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 263         struct itd1000_state *state = fe->tuner_priv;
 264         u8 pllcon1;
 265
 266         itd1000_set_lo(state, c->frequency);
 267         itd1000_set_lpf_bw(state, c->symbol_rate);
 268
 269         pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
 270         itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
 271         itd1000_write_reg(state, PLLCON1, pllcon1);
 272
 273         return 0;
 274 }
 275
 276 static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 277 {
 278         struct itd1000_state *state = fe->tuner_priv;
 279         *frequency = state->frequency;
 280         return 0;
 281 }
 282
 283 static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
 284 {
 285         return 0;
 286 }
 287
 288 static u8 itd1000_init_tab[][2] = {
 289         { PLLCON1,       0x65 }, /* Register does not change */
 290         { PLLNH,         0x80 }, /* Bits [7:6] do not change */
 291         { RESERVED_0X6D, 0x3b },
 292         { VCO_CHP2_I2C,  0x12 },
 293         { 0x72,          0xf9 }, /* No such regsister defined */
 294         { RESERVED_0X73, 0xff },
 295         { RESERVED_0X74, 0xb2 },
 296         { RESERVED_0X75, 0xc7 },
 297         { EXTGVBBRF,     0xf0 },
 298         { DIVAGCCK,      0x80 },
 299         { BBTR,          0xa0 },
 300         { RESERVED_0X7E, 0x4f },
 301         { 0x82,          0x88 }, /* No such regsister defined */
 302         { 0x83,          0x80 }, /* No such regsister defined */
 303         { 0x84,          0x80 }, /* No such regsister defined */
 304         { RESERVED_0X85, 0x74 },
 305         { RESERVED_0X86, 0xff },
 306         { RESERVED_0X88, 0x02 },
 307         { RESERVED_0X89, 0x16 },
 308         { RFST0,         0x1f },
 309         { RESERVED_0X94, 0x66 },
 310         { RESERVED_0X95, 0x66 },
 311         { RESERVED_0X96, 0x77 },
 312         { RESERVED_0X97, 0x99 },
 313         { RESERVED_0X98, 0xff },
 314         { RESERVED_0X99, 0xfc },
 315         { RESERVED_0X9A, 0xba },
 316         { RESERVED_0X9B, 0xaa },
 317 };
 318
 319 static u8 itd1000_reinit_tab[][2] = {
 320         { VCO_CHP1_I2C, 0x8a },
 321         { BW,           0x87 },
 322         { GVBB_I2C,     0x03 },
 323         { BBGVMIN,      0x03 },
 324         { CON1,         0x2e },
 325 };
 326
 327
 328 static int itd1000_init(struct dvb_frontend *fe)
 329 {
 330         struct itd1000_state *state = fe->tuner_priv;
 331         int i;
 332
 333         for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
 334                 itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
 335
 336         for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
 337                 itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
 338
 339         return 0;
 340 }
 341
 342 static int itd1000_sleep(struct dvb_frontend *fe)
 343 {
 344         return 0;
 345 }
 346
 347 static void itd1000_release(struct dvb_frontend *fe)
 348 {
 349         kfree(fe->tuner_priv);
 350         fe->tuner_priv = NULL;
 351 }
 352
 353 static const struct dvb_tuner_ops itd1000_tuner_ops = {
 354         .info = {
 355                 .name           = "Integrant ITD1000",
 356                 .frequency_min  = 950000,
 357                 .frequency_max  = 2150000,
 358                 .frequency_step = 125,     /* kHz for QPSK frontends */
 359         },
 360
 361         .release       = itd1000_release,
 362
 363         .init          = itd1000_init,
 364         .sleep         = itd1000_sleep,
 365
 366         .set_params    = itd1000_set_parameters,
 367         .get_frequency = itd1000_get_frequency,
 368         .get_bandwidth = itd1000_get_bandwidth
 369 };
 370
 371
 372 struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
 373 {
 374         struct itd1000_state *state = NULL;
 375         u8 i = 0;
 376
 377         state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
 378         if (state == NULL)
 379                 return NULL;
 380
 381         state->cfg = cfg;
 382         state->i2c = i2c;
 383
 384         i = itd1000_read_reg(state, 0);
 385         if (i != 0) {
 386                 kfree(state);
 387                 return NULL;
 388         }
 389         itd_info("successfully identified (ID: %d)\n", i);
 390
 391         memset(state->shadow, 0xff, sizeof(state->shadow));
 392         for (i = 0x65; i < 0x9c; i++)
 393                 state->shadow[i] = itd1000_read_reg(state, i);
 394
 395         memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
 396
 397         fe->tuner_priv = state;
 398
 399         return fe;
 400 }
 401 EXPORT_SYMBOL(itd1000_attach);
 402
 403 MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
 404 MODULE_DESCRIPTION("Integrant ITD1000 driver");
 405 MODULE_LICENSE("GPL");