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[media] m88ds3103: use own reg update_bits() implementation
[mirror_ubuntu-zesty-kernel.git] / drivers / media / dvb-frontends / m88ds3103.c
1 /*
2 * Montage Technology M88DS3103/M88RS6000 demodulator driver
3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "m88ds3103_priv.h"
18
19 static struct dvb_frontend_ops m88ds3103_ops;
20
21 /* write single register with mask */
22 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
23 u8 reg, u8 mask, u8 val)
24 {
25 int ret;
26 u8 tmp;
27
28 /* no need for read if whole reg is written */
29 if (mask != 0xff) {
30 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
31 if (ret)
32 return ret;
33
34 val &= mask;
35 tmp &= ~mask;
36 val |= tmp;
37 }
38
39 return regmap_bulk_write(dev->regmap, reg, &val, 1);
40 }
41
42 /* write reg val table using reg addr auto increment */
43 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
44 const struct m88ds3103_reg_val *tab, int tab_len)
45 {
46 struct i2c_client *client = dev->client;
47 int ret, i, j;
48 u8 buf[83];
49
50 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
51
52 if (tab_len > 86) {
53 ret = -EINVAL;
54 goto err;
55 }
56
57 for (i = 0, j = 0; i < tab_len; i++, j++) {
58 buf[j] = tab[i].val;
59
60 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
61 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
62 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
63 if (ret)
64 goto err;
65
66 j = -1;
67 }
68 }
69
70 return 0;
71 err:
72 dev_dbg(&client->dev, "failed=%d\n", ret);
73 return ret;
74 }
75
76 /*
77 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
78 */
79 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
80 {
81 struct m88ds3103_dev *dev = fe->demodulator_priv;
82 unsigned tmp;
83 int ret;
84
85 ret = regmap_read(dev->regmap, 0x3f, &tmp);
86 if (ret == 0)
87 *_agc_pwm = tmp;
88 return ret;
89 }
90 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
91
92 static int m88ds3103_read_status(struct dvb_frontend *fe,
93 enum fe_status *status)
94 {
95 struct m88ds3103_dev *dev = fe->demodulator_priv;
96 struct i2c_client *client = dev->client;
97 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
98 int ret, i, itmp;
99 unsigned int utmp;
100 u8 buf[3];
101
102 *status = 0;
103
104 if (!dev->warm) {
105 ret = -EAGAIN;
106 goto err;
107 }
108
109 switch (c->delivery_system) {
110 case SYS_DVBS:
111 ret = regmap_read(dev->regmap, 0xd1, &utmp);
112 if (ret)
113 goto err;
114
115 if ((utmp & 0x07) == 0x07)
116 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
117 FE_HAS_VITERBI | FE_HAS_SYNC |
118 FE_HAS_LOCK;
119 break;
120 case SYS_DVBS2:
121 ret = regmap_read(dev->regmap, 0x0d, &utmp);
122 if (ret)
123 goto err;
124
125 if ((utmp & 0x8f) == 0x8f)
126 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
127 FE_HAS_VITERBI | FE_HAS_SYNC |
128 FE_HAS_LOCK;
129 break;
130 default:
131 dev_dbg(&client->dev, "invalid delivery_system\n");
132 ret = -EINVAL;
133 goto err;
134 }
135
136 dev->fe_status = *status;
137 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
138
139 /* CNR */
140 if (dev->fe_status & FE_HAS_VITERBI) {
141 unsigned int cnr, noise, signal, noise_tot, signal_tot;
142
143 cnr = 0;
144 /* more iterations for more accurate estimation */
145 #define M88DS3103_SNR_ITERATIONS 3
146
147 switch (c->delivery_system) {
148 case SYS_DVBS:
149 itmp = 0;
150
151 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
152 ret = regmap_read(dev->regmap, 0xff, &utmp);
153 if (ret)
154 goto err;
155
156 itmp += utmp;
157 }
158
159 /* use of single register limits max value to 15 dB */
160 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
161 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
162 if (itmp)
163 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
164 break;
165 case SYS_DVBS2:
166 noise_tot = 0;
167 signal_tot = 0;
168
169 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
170 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
171 if (ret)
172 goto err;
173
174 noise = buf[1] << 6; /* [13:6] */
175 noise |= buf[0] & 0x3f; /* [5:0] */
176 noise >>= 2;
177 signal = buf[2] * buf[2];
178 signal >>= 1;
179
180 noise_tot += noise;
181 signal_tot += signal;
182 }
183
184 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
185 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
186
187 /* SNR(X) dB = 10 * log10(X) dB */
188 if (signal > noise) {
189 itmp = signal / noise;
190 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
191 }
192 break;
193 default:
194 dev_dbg(&client->dev, "invalid delivery_system\n");
195 ret = -EINVAL;
196 goto err;
197 }
198
199 if (cnr) {
200 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
201 c->cnr.stat[0].svalue = cnr;
202 } else {
203 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
204 }
205 } else {
206 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
207 }
208
209 /* BER */
210 if (dev->fe_status & FE_HAS_LOCK) {
211 unsigned int utmp, post_bit_error, post_bit_count;
212
213 switch (c->delivery_system) {
214 case SYS_DVBS:
215 ret = regmap_write(dev->regmap, 0xf9, 0x04);
216 if (ret)
217 goto err;
218
219 ret = regmap_read(dev->regmap, 0xf8, &utmp);
220 if (ret)
221 goto err;
222
223 /* measurement ready? */
224 if (!(utmp & 0x10)) {
225 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
226 if (ret)
227 goto err;
228
229 post_bit_error = buf[1] << 8 | buf[0] << 0;
230 post_bit_count = 0x800000;
231 dev->post_bit_error += post_bit_error;
232 dev->post_bit_count += post_bit_count;
233 dev->dvbv3_ber = post_bit_error;
234
235 /* restart measurement */
236 utmp |= 0x10;
237 ret = regmap_write(dev->regmap, 0xf8, utmp);
238 if (ret)
239 goto err;
240 }
241 break;
242 case SYS_DVBS2:
243 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
244 if (ret)
245 goto err;
246
247 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
248
249 /* enough data? */
250 if (utmp > 4000) {
251 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
252 if (ret)
253 goto err;
254
255 post_bit_error = buf[1] << 8 | buf[0] << 0;
256 post_bit_count = 32 * utmp; /* TODO: FEC */
257 dev->post_bit_error += post_bit_error;
258 dev->post_bit_count += post_bit_count;
259 dev->dvbv3_ber = post_bit_error;
260
261 /* restart measurement */
262 ret = regmap_write(dev->regmap, 0xd1, 0x01);
263 if (ret)
264 goto err;
265
266 ret = regmap_write(dev->regmap, 0xf9, 0x01);
267 if (ret)
268 goto err;
269
270 ret = regmap_write(dev->regmap, 0xf9, 0x00);
271 if (ret)
272 goto err;
273
274 ret = regmap_write(dev->regmap, 0xd1, 0x00);
275 if (ret)
276 goto err;
277 }
278 break;
279 default:
280 dev_dbg(&client->dev, "invalid delivery_system\n");
281 ret = -EINVAL;
282 goto err;
283 }
284
285 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
286 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
287 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
288 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
289 } else {
290 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
291 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
292 }
293
294 return 0;
295 err:
296 dev_dbg(&client->dev, "failed=%d\n", ret);
297 return ret;
298 }
299
300 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
301 {
302 struct m88ds3103_dev *dev = fe->demodulator_priv;
303 struct i2c_client *client = dev->client;
304 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
305 int ret, len;
306 const struct m88ds3103_reg_val *init;
307 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
308 u8 buf[3];
309 u16 u16tmp, divide_ratio = 0;
310 u32 tuner_frequency, target_mclk;
311 s32 s32tmp;
312
313 dev_dbg(&client->dev,
314 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
315 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
316 c->inversion, c->pilot, c->rolloff);
317
318 if (!dev->warm) {
319 ret = -EAGAIN;
320 goto err;
321 }
322
323 /* reset */
324 ret = regmap_write(dev->regmap, 0x07, 0x80);
325 if (ret)
326 goto err;
327
328 ret = regmap_write(dev->regmap, 0x07, 0x00);
329 if (ret)
330 goto err;
331
332 /* Disable demod clock path */
333 if (dev->chip_id == M88RS6000_CHIP_ID) {
334 ret = regmap_write(dev->regmap, 0x06, 0xe0);
335 if (ret)
336 goto err;
337 }
338
339 /* program tuner */
340 if (fe->ops.tuner_ops.set_params) {
341 ret = fe->ops.tuner_ops.set_params(fe);
342 if (ret)
343 goto err;
344 }
345
346 if (fe->ops.tuner_ops.get_frequency) {
347 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
348 if (ret)
349 goto err;
350 } else {
351 /*
352 * Use nominal target frequency as tuner driver does not provide
353 * actual frequency used. Carrier offset calculation is not
354 * valid.
355 */
356 tuner_frequency = c->frequency;
357 }
358
359 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
360 if (dev->chip_id == M88RS6000_CHIP_ID) {
361 if (c->symbol_rate > 45010000)
362 dev->mclk_khz = 110250;
363 else
364 dev->mclk_khz = 96000;
365
366 if (c->delivery_system == SYS_DVBS)
367 target_mclk = 96000;
368 else
369 target_mclk = 144000;
370
371 /* Enable demod clock path */
372 ret = regmap_write(dev->regmap, 0x06, 0x00);
373 if (ret)
374 goto err;
375 usleep_range(10000, 20000);
376 } else {
377 /* set M88DS3103 mclk and ts mclk. */
378 dev->mclk_khz = 96000;
379
380 switch (dev->cfg->ts_mode) {
381 case M88DS3103_TS_SERIAL:
382 case M88DS3103_TS_SERIAL_D7:
383 target_mclk = dev->cfg->ts_clk;
384 break;
385 case M88DS3103_TS_PARALLEL:
386 case M88DS3103_TS_CI:
387 if (c->delivery_system == SYS_DVBS)
388 target_mclk = 96000;
389 else {
390 if (c->symbol_rate < 18000000)
391 target_mclk = 96000;
392 else if (c->symbol_rate < 28000000)
393 target_mclk = 144000;
394 else
395 target_mclk = 192000;
396 }
397 break;
398 default:
399 dev_dbg(&client->dev, "invalid ts_mode\n");
400 ret = -EINVAL;
401 goto err;
402 }
403
404 switch (target_mclk) {
405 case 96000:
406 u8tmp1 = 0x02; /* 0b10 */
407 u8tmp2 = 0x01; /* 0b01 */
408 break;
409 case 144000:
410 u8tmp1 = 0x00; /* 0b00 */
411 u8tmp2 = 0x01; /* 0b01 */
412 break;
413 case 192000:
414 u8tmp1 = 0x03; /* 0b11 */
415 u8tmp2 = 0x00; /* 0b00 */
416 break;
417 }
418 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
419 if (ret)
420 goto err;
421 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
422 if (ret)
423 goto err;
424 }
425
426 ret = regmap_write(dev->regmap, 0xb2, 0x01);
427 if (ret)
428 goto err;
429
430 ret = regmap_write(dev->regmap, 0x00, 0x01);
431 if (ret)
432 goto err;
433
434 switch (c->delivery_system) {
435 case SYS_DVBS:
436 if (dev->chip_id == M88RS6000_CHIP_ID) {
437 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
438 init = m88rs6000_dvbs_init_reg_vals;
439 } else {
440 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
441 init = m88ds3103_dvbs_init_reg_vals;
442 }
443 break;
444 case SYS_DVBS2:
445 if (dev->chip_id == M88RS6000_CHIP_ID) {
446 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
447 init = m88rs6000_dvbs2_init_reg_vals;
448 } else {
449 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
450 init = m88ds3103_dvbs2_init_reg_vals;
451 }
452 break;
453 default:
454 dev_dbg(&client->dev, "invalid delivery_system\n");
455 ret = -EINVAL;
456 goto err;
457 }
458
459 /* program init table */
460 if (c->delivery_system != dev->delivery_system) {
461 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
462 if (ret)
463 goto err;
464 }
465
466 if (dev->chip_id == M88RS6000_CHIP_ID) {
467 if ((c->delivery_system == SYS_DVBS2)
468 && ((c->symbol_rate / 1000) <= 5000)) {
469 ret = regmap_write(dev->regmap, 0xc0, 0x04);
470 if (ret)
471 goto err;
472 buf[0] = 0x09;
473 buf[1] = 0x22;
474 buf[2] = 0x88;
475 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
476 if (ret)
477 goto err;
478 }
479 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
480 if (ret)
481 goto err;
482 ret = regmap_write(dev->regmap, 0xf1, 0x01);
483 if (ret)
484 goto err;
485 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
486 if (ret)
487 goto err;
488 }
489
490 switch (dev->cfg->ts_mode) {
491 case M88DS3103_TS_SERIAL:
492 u8tmp1 = 0x00;
493 u8tmp = 0x06;
494 break;
495 case M88DS3103_TS_SERIAL_D7:
496 u8tmp1 = 0x20;
497 u8tmp = 0x06;
498 break;
499 case M88DS3103_TS_PARALLEL:
500 u8tmp = 0x02;
501 break;
502 case M88DS3103_TS_CI:
503 u8tmp = 0x03;
504 break;
505 default:
506 dev_dbg(&client->dev, "invalid ts_mode\n");
507 ret = -EINVAL;
508 goto err;
509 }
510
511 if (dev->cfg->ts_clk_pol)
512 u8tmp |= 0x40;
513
514 /* TS mode */
515 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
516 if (ret)
517 goto err;
518
519 switch (dev->cfg->ts_mode) {
520 case M88DS3103_TS_SERIAL:
521 case M88DS3103_TS_SERIAL_D7:
522 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
523 if (ret)
524 goto err;
525 u8tmp1 = 0;
526 u8tmp2 = 0;
527 break;
528 default:
529 if (dev->cfg->ts_clk) {
530 divide_ratio = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
531 u8tmp1 = divide_ratio / 2;
532 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
533 }
534 }
535
536 dev_dbg(&client->dev,
537 "target_mclk=%d ts_clk=%d divide_ratio=%d\n",
538 target_mclk, dev->cfg->ts_clk, divide_ratio);
539
540 u8tmp1--;
541 u8tmp2--;
542 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
543 u8tmp1 &= 0x3f;
544 /* u8tmp2[5:0] => ea[5:0] */
545 u8tmp2 &= 0x3f;
546
547 ret = regmap_bulk_read(dev->regmap, 0xfe, &u8tmp, 1);
548 if (ret)
549 goto err;
550
551 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
552 ret = regmap_write(dev->regmap, 0xfe, u8tmp);
553 if (ret)
554 goto err;
555
556 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
557 ret = regmap_write(dev->regmap, 0xea, u8tmp);
558 if (ret)
559 goto err;
560
561 if (c->symbol_rate <= 3000000)
562 u8tmp = 0x20;
563 else if (c->symbol_rate <= 10000000)
564 u8tmp = 0x10;
565 else
566 u8tmp = 0x06;
567
568 ret = regmap_write(dev->regmap, 0xc3, 0x08);
569 if (ret)
570 goto err;
571
572 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
573 if (ret)
574 goto err;
575
576 ret = regmap_write(dev->regmap, 0xc4, 0x08);
577 if (ret)
578 goto err;
579
580 ret = regmap_write(dev->regmap, 0xc7, 0x00);
581 if (ret)
582 goto err;
583
584 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, dev->mclk_khz / 2);
585 buf[0] = (u16tmp >> 0) & 0xff;
586 buf[1] = (u16tmp >> 8) & 0xff;
587 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
588 if (ret)
589 goto err;
590
591 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
592 if (ret)
593 goto err;
594
595 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
596 if (ret)
597 goto err;
598
599 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
600 if (ret)
601 goto err;
602
603 dev_dbg(&client->dev, "carrier offset=%d\n",
604 (tuner_frequency - c->frequency));
605
606 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
607 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk_khz);
608 if (s32tmp < 0)
609 s32tmp += 0x10000;
610
611 buf[0] = (s32tmp >> 0) & 0xff;
612 buf[1] = (s32tmp >> 8) & 0xff;
613 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
614 if (ret)
615 goto err;
616
617 ret = regmap_write(dev->regmap, 0x00, 0x00);
618 if (ret)
619 goto err;
620
621 ret = regmap_write(dev->regmap, 0xb2, 0x00);
622 if (ret)
623 goto err;
624
625 dev->delivery_system = c->delivery_system;
626
627 return 0;
628 err:
629 dev_dbg(&client->dev, "failed=%d\n", ret);
630 return ret;
631 }
632
633 static int m88ds3103_init(struct dvb_frontend *fe)
634 {
635 struct m88ds3103_dev *dev = fe->demodulator_priv;
636 struct i2c_client *client = dev->client;
637 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
638 int ret, len, remaining;
639 unsigned int utmp;
640 const struct firmware *fw = NULL;
641 u8 *fw_file;
642
643 dev_dbg(&client->dev, "\n");
644
645 /* set cold state by default */
646 dev->warm = false;
647
648 /* wake up device from sleep */
649 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
650 if (ret)
651 goto err;
652 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
653 if (ret)
654 goto err;
655 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
656 if (ret)
657 goto err;
658
659 /* firmware status */
660 ret = regmap_read(dev->regmap, 0xb9, &utmp);
661 if (ret)
662 goto err;
663
664 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
665
666 if (utmp)
667 goto skip_fw_download;
668
669 /* global reset, global diseqc reset, golbal fec reset */
670 ret = regmap_write(dev->regmap, 0x07, 0xe0);
671 if (ret)
672 goto err;
673 ret = regmap_write(dev->regmap, 0x07, 0x00);
674 if (ret)
675 goto err;
676
677 /* cold state - try to download firmware */
678 dev_info(&client->dev, "found a '%s' in cold state\n",
679 m88ds3103_ops.info.name);
680
681 if (dev->chip_id == M88RS6000_CHIP_ID)
682 fw_file = M88RS6000_FIRMWARE;
683 else
684 fw_file = M88DS3103_FIRMWARE;
685 /* request the firmware, this will block and timeout */
686 ret = request_firmware(&fw, fw_file, &client->dev);
687 if (ret) {
688 dev_err(&client->dev, "firmare file '%s' not found\n", fw_file);
689 goto err;
690 }
691
692 dev_info(&client->dev, "downloading firmware from file '%s'\n",
693 fw_file);
694
695 ret = regmap_write(dev->regmap, 0xb2, 0x01);
696 if (ret)
697 goto error_fw_release;
698
699 for (remaining = fw->size; remaining > 0;
700 remaining -= (dev->cfg->i2c_wr_max - 1)) {
701 len = remaining;
702 if (len > (dev->cfg->i2c_wr_max - 1))
703 len = (dev->cfg->i2c_wr_max - 1);
704
705 ret = regmap_bulk_write(dev->regmap, 0xb0,
706 &fw->data[fw->size - remaining], len);
707 if (ret) {
708 dev_err(&client->dev, "firmware download failed=%d\n",
709 ret);
710 goto error_fw_release;
711 }
712 }
713
714 ret = regmap_write(dev->regmap, 0xb2, 0x00);
715 if (ret)
716 goto error_fw_release;
717
718 release_firmware(fw);
719 fw = NULL;
720
721 ret = regmap_read(dev->regmap, 0xb9, &utmp);
722 if (ret)
723 goto err;
724
725 if (!utmp) {
726 dev_info(&client->dev, "firmware did not run\n");
727 ret = -EFAULT;
728 goto err;
729 }
730
731 dev_info(&client->dev, "found a '%s' in warm state\n",
732 m88ds3103_ops.info.name);
733 dev_info(&client->dev, "firmware version: %X.%X\n",
734 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
735
736 skip_fw_download:
737 /* warm state */
738 dev->warm = true;
739
740 /* init stats here in order signal app which stats are supported */
741 c->cnr.len = 1;
742 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
743 c->post_bit_error.len = 1;
744 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
745 c->post_bit_count.len = 1;
746 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
747
748 return 0;
749 error_fw_release:
750 release_firmware(fw);
751 err:
752 dev_dbg(&client->dev, "failed=%d\n", ret);
753 return ret;
754 }
755
756 static int m88ds3103_sleep(struct dvb_frontend *fe)
757 {
758 struct m88ds3103_dev *dev = fe->demodulator_priv;
759 struct i2c_client *client = dev->client;
760 int ret;
761 unsigned int utmp;
762
763 dev_dbg(&client->dev, "\n");
764
765 dev->fe_status = 0;
766 dev->delivery_system = SYS_UNDEFINED;
767
768 /* TS Hi-Z */
769 if (dev->chip_id == M88RS6000_CHIP_ID)
770 utmp = 0x29;
771 else
772 utmp = 0x27;
773 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
774 if (ret)
775 goto err;
776
777 /* sleep */
778 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
779 if (ret)
780 goto err;
781 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
782 if (ret)
783 goto err;
784 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
785 if (ret)
786 goto err;
787
788 return 0;
789 err:
790 dev_dbg(&client->dev, "failed=%d\n", ret);
791 return ret;
792 }
793
794 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
795 {
796 struct m88ds3103_dev *dev = fe->demodulator_priv;
797 struct i2c_client *client = dev->client;
798 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
799 int ret;
800 u8 buf[3];
801
802 dev_dbg(&client->dev, "\n");
803
804 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
805 ret = 0;
806 goto err;
807 }
808
809 switch (c->delivery_system) {
810 case SYS_DVBS:
811 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
812 if (ret)
813 goto err;
814
815 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
816 if (ret)
817 goto err;
818
819 switch ((buf[0] >> 2) & 0x01) {
820 case 0:
821 c->inversion = INVERSION_OFF;
822 break;
823 case 1:
824 c->inversion = INVERSION_ON;
825 break;
826 }
827
828 switch ((buf[1] >> 5) & 0x07) {
829 case 0:
830 c->fec_inner = FEC_7_8;
831 break;
832 case 1:
833 c->fec_inner = FEC_5_6;
834 break;
835 case 2:
836 c->fec_inner = FEC_3_4;
837 break;
838 case 3:
839 c->fec_inner = FEC_2_3;
840 break;
841 case 4:
842 c->fec_inner = FEC_1_2;
843 break;
844 default:
845 dev_dbg(&client->dev, "invalid fec_inner\n");
846 }
847
848 c->modulation = QPSK;
849
850 break;
851 case SYS_DVBS2:
852 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
853 if (ret)
854 goto err;
855
856 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
857 if (ret)
858 goto err;
859
860 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
861 if (ret)
862 goto err;
863
864 switch ((buf[0] >> 0) & 0x0f) {
865 case 2:
866 c->fec_inner = FEC_2_5;
867 break;
868 case 3:
869 c->fec_inner = FEC_1_2;
870 break;
871 case 4:
872 c->fec_inner = FEC_3_5;
873 break;
874 case 5:
875 c->fec_inner = FEC_2_3;
876 break;
877 case 6:
878 c->fec_inner = FEC_3_4;
879 break;
880 case 7:
881 c->fec_inner = FEC_4_5;
882 break;
883 case 8:
884 c->fec_inner = FEC_5_6;
885 break;
886 case 9:
887 c->fec_inner = FEC_8_9;
888 break;
889 case 10:
890 c->fec_inner = FEC_9_10;
891 break;
892 default:
893 dev_dbg(&client->dev, "invalid fec_inner\n");
894 }
895
896 switch ((buf[0] >> 5) & 0x01) {
897 case 0:
898 c->pilot = PILOT_OFF;
899 break;
900 case 1:
901 c->pilot = PILOT_ON;
902 break;
903 }
904
905 switch ((buf[0] >> 6) & 0x07) {
906 case 0:
907 c->modulation = QPSK;
908 break;
909 case 1:
910 c->modulation = PSK_8;
911 break;
912 case 2:
913 c->modulation = APSK_16;
914 break;
915 case 3:
916 c->modulation = APSK_32;
917 break;
918 default:
919 dev_dbg(&client->dev, "invalid modulation\n");
920 }
921
922 switch ((buf[1] >> 7) & 0x01) {
923 case 0:
924 c->inversion = INVERSION_OFF;
925 break;
926 case 1:
927 c->inversion = INVERSION_ON;
928 break;
929 }
930
931 switch ((buf[2] >> 0) & 0x03) {
932 case 0:
933 c->rolloff = ROLLOFF_35;
934 break;
935 case 1:
936 c->rolloff = ROLLOFF_25;
937 break;
938 case 2:
939 c->rolloff = ROLLOFF_20;
940 break;
941 default:
942 dev_dbg(&client->dev, "invalid rolloff\n");
943 }
944 break;
945 default:
946 dev_dbg(&client->dev, "invalid delivery_system\n");
947 ret = -EINVAL;
948 goto err;
949 }
950
951 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
952 if (ret)
953 goto err;
954
955 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
956 dev->mclk_khz * 1000 / 0x10000;
957
958 return 0;
959 err:
960 dev_dbg(&client->dev, "failed=%d\n", ret);
961 return ret;
962 }
963
964 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
965 {
966 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
967
968 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
969 *snr = div_s64(c->cnr.stat[0].svalue, 100);
970 else
971 *snr = 0;
972
973 return 0;
974 }
975
976 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
977 {
978 struct m88ds3103_dev *dev = fe->demodulator_priv;
979
980 *ber = dev->dvbv3_ber;
981
982 return 0;
983 }
984
985 static int m88ds3103_set_tone(struct dvb_frontend *fe,
986 enum fe_sec_tone_mode fe_sec_tone_mode)
987 {
988 struct m88ds3103_dev *dev = fe->demodulator_priv;
989 struct i2c_client *client = dev->client;
990 int ret;
991 unsigned int utmp, tone, reg_a1_mask;
992
993 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
994
995 if (!dev->warm) {
996 ret = -EAGAIN;
997 goto err;
998 }
999
1000 switch (fe_sec_tone_mode) {
1001 case SEC_TONE_ON:
1002 tone = 0;
1003 reg_a1_mask = 0x47;
1004 break;
1005 case SEC_TONE_OFF:
1006 tone = 1;
1007 reg_a1_mask = 0x00;
1008 break;
1009 default:
1010 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
1011 ret = -EINVAL;
1012 goto err;
1013 }
1014
1015 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
1016 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1017 if (ret)
1018 goto err;
1019
1020 utmp = 1 << 2;
1021 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
1022 if (ret)
1023 goto err;
1024
1025 return 0;
1026 err:
1027 dev_dbg(&client->dev, "failed=%d\n", ret);
1028 return ret;
1029 }
1030
1031 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1032 enum fe_sec_voltage fe_sec_voltage)
1033 {
1034 struct m88ds3103_dev *dev = fe->demodulator_priv;
1035 struct i2c_client *client = dev->client;
1036 int ret;
1037 unsigned int utmp;
1038 bool voltage_sel, voltage_dis;
1039
1040 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1041
1042 if (!dev->warm) {
1043 ret = -EAGAIN;
1044 goto err;
1045 }
1046
1047 switch (fe_sec_voltage) {
1048 case SEC_VOLTAGE_18:
1049 voltage_sel = true;
1050 voltage_dis = false;
1051 break;
1052 case SEC_VOLTAGE_13:
1053 voltage_sel = false;
1054 voltage_dis = false;
1055 break;
1056 case SEC_VOLTAGE_OFF:
1057 voltage_sel = false;
1058 voltage_dis = true;
1059 break;
1060 default:
1061 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1062 ret = -EINVAL;
1063 goto err;
1064 }
1065
1066 /* output pin polarity */
1067 voltage_sel ^= dev->cfg->lnb_hv_pol;
1068 voltage_dis ^= dev->cfg->lnb_en_pol;
1069
1070 utmp = voltage_dis << 1 | voltage_sel << 0;
1071 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1072 if (ret)
1073 goto err;
1074
1075 return 0;
1076 err:
1077 dev_dbg(&client->dev, "failed=%d\n", ret);
1078 return ret;
1079 }
1080
1081 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1082 struct dvb_diseqc_master_cmd *diseqc_cmd)
1083 {
1084 struct m88ds3103_dev *dev = fe->demodulator_priv;
1085 struct i2c_client *client = dev->client;
1086 int ret;
1087 unsigned int utmp;
1088 unsigned long timeout;
1089
1090 dev_dbg(&client->dev, "msg=%*ph\n",
1091 diseqc_cmd->msg_len, diseqc_cmd->msg);
1092
1093 if (!dev->warm) {
1094 ret = -EAGAIN;
1095 goto err;
1096 }
1097
1098 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1099 ret = -EINVAL;
1100 goto err;
1101 }
1102
1103 utmp = dev->cfg->envelope_mode << 5;
1104 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1105 if (ret)
1106 goto err;
1107
1108 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1109 diseqc_cmd->msg_len);
1110 if (ret)
1111 goto err;
1112
1113 ret = regmap_write(dev->regmap, 0xa1,
1114 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1115 if (ret)
1116 goto err;
1117
1118 /* wait DiSEqC TX ready */
1119 #define SEND_MASTER_CMD_TIMEOUT 120
1120 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1121
1122 /* DiSEqC message typical period is 54 ms */
1123 usleep_range(50000, 54000);
1124
1125 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1126 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1127 if (ret)
1128 goto err;
1129 utmp = (utmp >> 6) & 0x1;
1130 }
1131
1132 if (utmp == 0) {
1133 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1134 jiffies_to_msecs(jiffies) -
1135 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1136 } else {
1137 dev_dbg(&client->dev, "diseqc tx timeout\n");
1138
1139 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1140 if (ret)
1141 goto err;
1142 }
1143
1144 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1145 if (ret)
1146 goto err;
1147
1148 if (utmp == 1) {
1149 ret = -ETIMEDOUT;
1150 goto err;
1151 }
1152
1153 return 0;
1154 err:
1155 dev_dbg(&client->dev, "failed=%d\n", ret);
1156 return ret;
1157 }
1158
1159 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1160 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1161 {
1162 struct m88ds3103_dev *dev = fe->demodulator_priv;
1163 struct i2c_client *client = dev->client;
1164 int ret;
1165 unsigned int utmp, burst;
1166 unsigned long timeout;
1167
1168 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1169
1170 if (!dev->warm) {
1171 ret = -EAGAIN;
1172 goto err;
1173 }
1174
1175 utmp = dev->cfg->envelope_mode << 5;
1176 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1177 if (ret)
1178 goto err;
1179
1180 switch (fe_sec_mini_cmd) {
1181 case SEC_MINI_A:
1182 burst = 0x02;
1183 break;
1184 case SEC_MINI_B:
1185 burst = 0x01;
1186 break;
1187 default:
1188 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1189 ret = -EINVAL;
1190 goto err;
1191 }
1192
1193 ret = regmap_write(dev->regmap, 0xa1, burst);
1194 if (ret)
1195 goto err;
1196
1197 /* wait DiSEqC TX ready */
1198 #define SEND_BURST_TIMEOUT 40
1199 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1200
1201 /* DiSEqC ToneBurst period is 12.5 ms */
1202 usleep_range(8500, 12500);
1203
1204 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1205 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1206 if (ret)
1207 goto err;
1208 utmp = (utmp >> 6) & 0x1;
1209 }
1210
1211 if (utmp == 0) {
1212 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1213 jiffies_to_msecs(jiffies) -
1214 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1215 } else {
1216 dev_dbg(&client->dev, "diseqc tx timeout\n");
1217
1218 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1219 if (ret)
1220 goto err;
1221 }
1222
1223 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1224 if (ret)
1225 goto err;
1226
1227 if (utmp == 1) {
1228 ret = -ETIMEDOUT;
1229 goto err;
1230 }
1231
1232 return 0;
1233 err:
1234 dev_dbg(&client->dev, "failed=%d\n", ret);
1235 return ret;
1236 }
1237
1238 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1239 struct dvb_frontend_tune_settings *s)
1240 {
1241 s->min_delay_ms = 3000;
1242
1243 return 0;
1244 }
1245
1246 static void m88ds3103_release(struct dvb_frontend *fe)
1247 {
1248 struct m88ds3103_dev *dev = fe->demodulator_priv;
1249 struct i2c_client *client = dev->client;
1250
1251 i2c_unregister_device(client);
1252 }
1253
1254 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1255 {
1256 struct m88ds3103_dev *dev = mux_priv;
1257 struct i2c_client *client = dev->client;
1258 int ret;
1259 struct i2c_msg msg = {
1260 .addr = client->addr,
1261 .flags = 0,
1262 .len = 2,
1263 .buf = "\x03\x11",
1264 };
1265
1266 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1267 ret = __i2c_transfer(client->adapter, &msg, 1);
1268 if (ret != 1) {
1269 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1270 if (ret >= 0)
1271 ret = -EREMOTEIO;
1272 return ret;
1273 }
1274
1275 return 0;
1276 }
1277
1278 /*
1279 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1280 * proper I2C client for legacy media attach binding.
1281 * New users must use I2C client binding directly!
1282 */
1283 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1284 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1285 {
1286 struct i2c_client *client;
1287 struct i2c_board_info board_info;
1288 struct m88ds3103_platform_data pdata;
1289
1290 pdata.clk = cfg->clock;
1291 pdata.i2c_wr_max = cfg->i2c_wr_max;
1292 pdata.ts_mode = cfg->ts_mode;
1293 pdata.ts_clk = cfg->ts_clk;
1294 pdata.ts_clk_pol = cfg->ts_clk_pol;
1295 pdata.spec_inv = cfg->spec_inv;
1296 pdata.agc = cfg->agc;
1297 pdata.agc_inv = cfg->agc_inv;
1298 pdata.clk_out = cfg->clock_out;
1299 pdata.envelope_mode = cfg->envelope_mode;
1300 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1301 pdata.lnb_en_pol = cfg->lnb_en_pol;
1302 pdata.attach_in_use = true;
1303
1304 memset(&board_info, 0, sizeof(board_info));
1305 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1306 board_info.addr = cfg->i2c_addr;
1307 board_info.platform_data = &pdata;
1308 client = i2c_new_device(i2c, &board_info);
1309 if (!client || !client->dev.driver)
1310 return NULL;
1311
1312 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1313 return pdata.get_dvb_frontend(client);
1314 }
1315 EXPORT_SYMBOL(m88ds3103_attach);
1316
1317 static struct dvb_frontend_ops m88ds3103_ops = {
1318 .delsys = {SYS_DVBS, SYS_DVBS2},
1319 .info = {
1320 .name = "Montage Technology M88DS3103",
1321 .frequency_min = 950000,
1322 .frequency_max = 2150000,
1323 .frequency_tolerance = 5000,
1324 .symbol_rate_min = 1000000,
1325 .symbol_rate_max = 45000000,
1326 .caps = FE_CAN_INVERSION_AUTO |
1327 FE_CAN_FEC_1_2 |
1328 FE_CAN_FEC_2_3 |
1329 FE_CAN_FEC_3_4 |
1330 FE_CAN_FEC_4_5 |
1331 FE_CAN_FEC_5_6 |
1332 FE_CAN_FEC_6_7 |
1333 FE_CAN_FEC_7_8 |
1334 FE_CAN_FEC_8_9 |
1335 FE_CAN_FEC_AUTO |
1336 FE_CAN_QPSK |
1337 FE_CAN_RECOVER |
1338 FE_CAN_2G_MODULATION
1339 },
1340
1341 .release = m88ds3103_release,
1342
1343 .get_tune_settings = m88ds3103_get_tune_settings,
1344
1345 .init = m88ds3103_init,
1346 .sleep = m88ds3103_sleep,
1347
1348 .set_frontend = m88ds3103_set_frontend,
1349 .get_frontend = m88ds3103_get_frontend,
1350
1351 .read_status = m88ds3103_read_status,
1352 .read_snr = m88ds3103_read_snr,
1353 .read_ber = m88ds3103_read_ber,
1354
1355 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1356 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1357
1358 .set_tone = m88ds3103_set_tone,
1359 .set_voltage = m88ds3103_set_voltage,
1360 };
1361
1362 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1363 {
1364 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1365
1366 dev_dbg(&client->dev, "\n");
1367
1368 return &dev->fe;
1369 }
1370
1371 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1372 {
1373 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1374
1375 dev_dbg(&client->dev, "\n");
1376
1377 return dev->i2c_adapter;
1378 }
1379
1380 static int m88ds3103_probe(struct i2c_client *client,
1381 const struct i2c_device_id *id)
1382 {
1383 struct m88ds3103_dev *dev;
1384 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1385 int ret;
1386 unsigned int utmp;
1387
1388 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1389 if (!dev) {
1390 ret = -ENOMEM;
1391 goto err;
1392 }
1393
1394 dev->client = client;
1395 dev->config.clock = pdata->clk;
1396 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1397 dev->config.ts_mode = pdata->ts_mode;
1398 dev->config.ts_clk = pdata->ts_clk;
1399 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1400 dev->config.spec_inv = pdata->spec_inv;
1401 dev->config.agc_inv = pdata->agc_inv;
1402 dev->config.clock_out = pdata->clk_out;
1403 dev->config.envelope_mode = pdata->envelope_mode;
1404 dev->config.agc = pdata->agc;
1405 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1406 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1407 dev->cfg = &dev->config;
1408 /* create regmap */
1409 dev->regmap_config.reg_bits = 8,
1410 dev->regmap_config.val_bits = 8,
1411 dev->regmap_config.lock_arg = dev,
1412 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1413 if (IS_ERR(dev->regmap)) {
1414 ret = PTR_ERR(dev->regmap);
1415 goto err_kfree;
1416 }
1417
1418 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1419 ret = regmap_read(dev->regmap, 0x00, &utmp);
1420 if (ret)
1421 goto err_kfree;
1422
1423 dev->chip_id = utmp >> 1;
1424 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1425
1426 switch (dev->chip_id) {
1427 case M88RS6000_CHIP_ID:
1428 case M88DS3103_CHIP_ID:
1429 break;
1430 default:
1431 goto err_kfree;
1432 }
1433
1434 switch (dev->cfg->clock_out) {
1435 case M88DS3103_CLOCK_OUT_DISABLED:
1436 utmp = 0x80;
1437 break;
1438 case M88DS3103_CLOCK_OUT_ENABLED:
1439 utmp = 0x00;
1440 break;
1441 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1442 utmp = 0x10;
1443 break;
1444 default:
1445 ret = -EINVAL;
1446 goto err_kfree;
1447 }
1448
1449 /* 0x29 register is defined differently for m88rs6000. */
1450 /* set internal tuner address to 0x21 */
1451 if (dev->chip_id == M88RS6000_CHIP_ID)
1452 utmp = 0x00;
1453
1454 ret = regmap_write(dev->regmap, 0x29, utmp);
1455 if (ret)
1456 goto err_kfree;
1457
1458 /* sleep */
1459 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1460 if (ret)
1461 goto err_kfree;
1462 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1463 if (ret)
1464 goto err_kfree;
1465 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1466 if (ret)
1467 goto err_kfree;
1468
1469 /* create mux i2c adapter for tuner */
1470 dev->i2c_adapter = i2c_add_mux_adapter(client->adapter, &client->dev,
1471 dev, 0, 0, 0, m88ds3103_select,
1472 NULL);
1473 if (dev->i2c_adapter == NULL) {
1474 ret = -ENOMEM;
1475 goto err_kfree;
1476 }
1477
1478 /* create dvb_frontend */
1479 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1480 if (dev->chip_id == M88RS6000_CHIP_ID)
1481 strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1482 sizeof(dev->fe.ops.info.name));
1483 if (!pdata->attach_in_use)
1484 dev->fe.ops.release = NULL;
1485 dev->fe.demodulator_priv = dev;
1486 i2c_set_clientdata(client, dev);
1487
1488 /* setup callbacks */
1489 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1490 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1491 return 0;
1492 err_kfree:
1493 kfree(dev);
1494 err:
1495 dev_dbg(&client->dev, "failed=%d\n", ret);
1496 return ret;
1497 }
1498
1499 static int m88ds3103_remove(struct i2c_client *client)
1500 {
1501 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1502
1503 dev_dbg(&client->dev, "\n");
1504
1505 i2c_del_mux_adapter(dev->i2c_adapter);
1506
1507 kfree(dev);
1508 return 0;
1509 }
1510
1511 static const struct i2c_device_id m88ds3103_id_table[] = {
1512 {"m88ds3103", 0},
1513 {}
1514 };
1515 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1516
1517 static struct i2c_driver m88ds3103_driver = {
1518 .driver = {
1519 .name = "m88ds3103",
1520 .suppress_bind_attrs = true,
1521 },
1522 .probe = m88ds3103_probe,
1523 .remove = m88ds3103_remove,
1524 .id_table = m88ds3103_id_table,
1525 };
1526
1527 module_i2c_driver(m88ds3103_driver);
1528
1529 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1530 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1531 MODULE_LICENSE("GPL");
1532 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1533 MODULE_FIRMWARE(M88RS6000_FIRMWARE);
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