drivers/media/dvb-frontends/mb86a20s.c

   1 /*
   2  *   Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
   3  *
   4  *   Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
   5  *   Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
   6  *
   7  *   This program is free software; you can redistribute it and/or
   8  *   modify it under the terms of the GNU General Public License as
   9  *   published by the Free Software Foundation version 2.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  *   General Public License for more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <asm/div64.h>
  19
  20 #include "dvb_frontend.h"
  21 #include "mb86a20s.h"
  22
  23 static int debug = 1;
  24 module_param(debug, int, 0644);
  25 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
  26
  27 struct mb86a20s_state {
  28         struct i2c_adapter *i2c;
  29         const struct mb86a20s_config *config;
  30         u32 last_frequency;
  31
  32         struct dvb_frontend frontend;
  33
  34         u32 estimated_rate[3];
  35
  36         bool need_init;
  37 };
  38
  39 struct regdata {
  40         u8 reg;
  41         u8 data;
  42 };
  43
  44 #define BER_SAMPLING_RATE       1       /* Seconds */
  45
  46 /*
  47  * Initialization sequence: Use whatevere default values that PV SBTVD
  48  * does on its initialisation, obtained via USB snoop
  49  */
  50 static struct regdata mb86a20s_init[] = {
  51         { 0x70, 0x0f },
  52         { 0x70, 0xff },
  53         { 0x08, 0x01 },
  54         { 0x09, 0x3e },
  55         { 0x50, 0xd1 }, { 0x51, 0x22 },
  56         { 0x39, 0x01 },
  57         { 0x71, 0x00 },
  58         { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 },
  59         { 0x28, 0x20 }, { 0x29, 0x33 }, { 0x2a, 0xdf }, { 0x2b, 0xa9 },
  60         { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
  61         { 0x3b, 0x21 },
  62         { 0x3c, 0x3a },
  63         { 0x01, 0x0d },
  64         { 0x04, 0x08 }, { 0x05, 0x05 },
  65         { 0x04, 0x0e }, { 0x05, 0x00 },
  66         { 0x04, 0x0f }, { 0x05, 0x14 },
  67         { 0x04, 0x0b }, { 0x05, 0x8c },
  68         { 0x04, 0x00 }, { 0x05, 0x00 },
  69         { 0x04, 0x01 }, { 0x05, 0x07 },
  70         { 0x04, 0x02 }, { 0x05, 0x0f },
  71         { 0x04, 0x03 }, { 0x05, 0xa0 },
  72         { 0x04, 0x09 }, { 0x05, 0x00 },
  73         { 0x04, 0x0a }, { 0x05, 0xff },
  74         { 0x04, 0x27 }, { 0x05, 0x64 },
  75         { 0x04, 0x28 }, { 0x05, 0x00 },
  76         { 0x04, 0x1e }, { 0x05, 0xff },
  77         { 0x04, 0x29 }, { 0x05, 0x0a },
  78         { 0x04, 0x32 }, { 0x05, 0x0a },
  79         { 0x04, 0x14 }, { 0x05, 0x02 },
  80         { 0x04, 0x04 }, { 0x05, 0x00 },
  81         { 0x04, 0x05 }, { 0x05, 0x22 },
  82         { 0x04, 0x06 }, { 0x05, 0x0e },
  83         { 0x04, 0x07 }, { 0x05, 0xd8 },
  84         { 0x04, 0x12 }, { 0x05, 0x00 },
  85         { 0x04, 0x13 }, { 0x05, 0xff },
  86         { 0x04, 0x15 }, { 0x05, 0x4e },
  87         { 0x04, 0x16 }, { 0x05, 0x20 },
  88
  89         /*
  90          * On this demod, when the bit count reaches the count below,
  91          * it collects the bit error count. The bit counters are initialized
  92          * to 65535 here. This warrants that all of them will be quickly
  93          * calculated when device gets locked. As TMCC is parsed, the values
  94          * will be adjusted later in the driver's code.
  95          */
  96         { 0x52, 0x01 },                         /* Turn on BER before Viterbi */
  97         { 0x50, 0xa7 }, { 0x51, 0x00 },
  98         { 0x50, 0xa8 }, { 0x51, 0xff },
  99         { 0x50, 0xa9 }, { 0x51, 0xff },
 100         { 0x50, 0xaa }, { 0x51, 0x00 },
 101         { 0x50, 0xab }, { 0x51, 0xff },
 102         { 0x50, 0xac }, { 0x51, 0xff },
 103         { 0x50, 0xad }, { 0x51, 0x00 },
 104         { 0x50, 0xae }, { 0x51, 0xff },
 105         { 0x50, 0xaf }, { 0x51, 0xff },
 106
 107         { 0x5e, 0x00 },                         /* Turn off BER after Viterbi */
 108         { 0x50, 0xdc }, { 0x51, 0x01 },
 109         { 0x50, 0xdd }, { 0x51, 0xf4 },
 110         { 0x50, 0xde }, { 0x51, 0x01 },
 111         { 0x50, 0xdf }, { 0x51, 0xf4 },
 112         { 0x50, 0xe0 }, { 0x51, 0x01 },
 113         { 0x50, 0xe1 }, { 0x51, 0xf4 },
 114         { 0x50, 0xb0 }, { 0x51, 0x07 },
 115         { 0x50, 0xb2 }, { 0x51, 0xff },
 116         { 0x50, 0xb3 }, { 0x51, 0xff },
 117         { 0x50, 0xb4 }, { 0x51, 0xff },
 118         { 0x50, 0xb5 }, { 0x51, 0xff },
 119         { 0x50, 0xb6 }, { 0x51, 0xff },
 120         { 0x50, 0xb7 }, { 0x51, 0xff },
 121
 122         { 0x50, 0x50 }, { 0x51, 0x02 },         /* MER manual mode */
 123         { 0x50, 0x51 }, { 0x51, 0x04 },         /* MER symbol 4 */
 124         { 0x45, 0x04 },                         /* CN symbol 4 */
 125         { 0x48, 0x04 },                         /* CN manual mode */
 126
 127         { 0x50, 0xd5 }, { 0x51, 0x01 },         /* Serial */
 128         { 0x50, 0xd6 }, { 0x51, 0x1f },
 129         { 0x50, 0xd2 }, { 0x51, 0x03 },
 130         { 0x50, 0xd7 }, { 0x51, 0x3f },
 131         { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 },
 132         { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c },
 133
 134         { 0x04, 0x40 }, { 0x05, 0x00 },
 135         { 0x28, 0x00 }, { 0x29, 0x10 },
 136         { 0x28, 0x05 }, { 0x29, 0x02 },
 137         { 0x1c, 0x01 },
 138         { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
 139         { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
 140         { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
 141         { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
 142         { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
 143         { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
 144         { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
 145         { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
 146         { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
 147         { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
 148         { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
 149         { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
 150         { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
 151         { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
 152         { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
 153         { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
 154         { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
 155         { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
 156         { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
 157         { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
 158         { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
 159         { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
 160         { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
 161         { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
 162         { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
 163         { 0x50, 0x1e }, { 0x51, 0x5d },
 164         { 0x50, 0x22 }, { 0x51, 0x00 },
 165         { 0x50, 0x23 }, { 0x51, 0xc8 },
 166         { 0x50, 0x24 }, { 0x51, 0x00 },
 167         { 0x50, 0x25 }, { 0x51, 0xf0 },
 168         { 0x50, 0x26 }, { 0x51, 0x00 },
 169         { 0x50, 0x27 }, { 0x51, 0xc3 },
 170         { 0x50, 0x39 }, { 0x51, 0x02 },
 171         { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
 172         { 0xd0, 0x00 },
 173 };
 174
 175 static struct regdata mb86a20s_reset_reception[] = {
 176         { 0x70, 0xf0 },
 177         { 0x70, 0xff },
 178         { 0x08, 0x01 },
 179         { 0x08, 0x00 },
 180 };
 181
 182 static struct regdata mb86a20s_vber_reset[] = {
 183         { 0x53, 0x00 }, /* VBER Counter reset */
 184         { 0x53, 0x07 },
 185 };
 186
 187 static struct regdata mb86a20s_per_reset[] = {
 188         { 0x50, 0xb1 }, /* PER Counter reset */
 189         { 0x51, 0x07 },
 190         { 0x51, 0x00 },
 191 };
 192
 193 /*
 194  * I2C read/write functions and macros
 195  */
 196
 197 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
 198                              u8 i2c_addr, u8 reg, u8 data)
 199 {
 200         u8 buf[] = { reg, data };
 201         struct i2c_msg msg = {
 202                 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
 203         };
 204         int rc;
 205
 206         rc = i2c_transfer(state->i2c, &msg, 1);
 207         if (rc != 1) {
 208                 dev_err(&state->i2c->dev,
 209                         "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
 210                         __func__, rc, reg, data);
 211                 return rc;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
 218                                      u8 i2c_addr, struct regdata *rd, int size)
 219 {
 220         int i, rc;
 221
 222         for (i = 0; i < size; i++) {
 223                 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
 224                                            rd[i].data);
 225                 if (rc < 0)
 226                         return rc;
 227         }
 228         return 0;
 229 }
 230
 231 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
 232                                 u8 i2c_addr, u8 reg)
 233 {
 234         u8 val;
 235         int rc;
 236         struct i2c_msg msg[] = {
 237                 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
 238                 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
 239         };
 240
 241         rc = i2c_transfer(state->i2c, msg, 2);
 242
 243         if (rc != 2) {
 244                 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
 245                         __func__, reg, rc);
 246                 return (rc < 0) ? rc : -EIO;
 247         }
 248
 249         return val;
 250 }
 251
 252 #define mb86a20s_readreg(state, reg) \
 253         mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
 254 #define mb86a20s_writereg(state, reg, val) \
 255         mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
 256 #define mb86a20s_writeregdata(state, regdata) \
 257         mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
 258         regdata, ARRAY_SIZE(regdata))
 259
 260 /*
 261  * Ancillary internal routines (likely compiled inlined)
 262  *
 263  * The functions below assume that gateway lock has already obtained
 264  */
 265
 266 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
 267 {
 268         struct mb86a20s_state *state = fe->demodulator_priv;
 269         int val;
 270
 271         *status = 0;
 272
 273         val = mb86a20s_readreg(state, 0x0a) & 0xf;
 274         if (val < 0)
 275                 return val;
 276
 277         if (val >= 2)
 278                 *status |= FE_HAS_SIGNAL;
 279
 280         if (val >= 4)
 281                 *status |= FE_HAS_CARRIER;
 282
 283         if (val >= 5)
 284                 *status |= FE_HAS_VITERBI;
 285
 286         if (val >= 7)
 287                 *status |= FE_HAS_SYNC;
 288
 289         if (val >= 8)                           /* Maybe 9? */
 290                 *status |= FE_HAS_LOCK;
 291
 292         dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
 293                  __func__, *status, val);
 294
 295         return 0;
 296 }
 297
 298 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
 299 {
 300         struct mb86a20s_state *state = fe->demodulator_priv;
 301         int rc;
 302         unsigned rf_max, rf_min, rf;
 303
 304         /* Does a binary search to get RF strength */
 305         rf_max = 0xfff;
 306         rf_min = 0;
 307         do {
 308                 rf = (rf_max + rf_min) / 2;
 309                 rc = mb86a20s_writereg(state, 0x04, 0x1f);
 310                 if (rc < 0)
 311                         return rc;
 312                 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
 313                 if (rc < 0)
 314                         return rc;
 315                 rc = mb86a20s_writereg(state, 0x04, 0x20);
 316                 if (rc < 0)
 317                         return rc;
 318                 rc = mb86a20s_writereg(state, 0x04, rf);
 319                 if (rc < 0)
 320                         return rc;
 321
 322                 rc = mb86a20s_readreg(state, 0x02);
 323                 if (rc < 0)
 324                         return rc;
 325                 if (rc & 0x08)
 326                         rf_min = (rf_max + rf_min) / 2;
 327                 else
 328                         rf_max = (rf_max + rf_min) / 2;
 329                 if (rf_max - rf_min < 4) {
 330                         rf = (rf_max + rf_min) / 2;
 331
 332                         /* Rescale it from 2^12 (4096) to 2^16 */
 333                         rf <<= (16 - 12);
 334                         dev_dbg(&state->i2c->dev,
 335                                 "%s: signal strength = %d (%d < RF=%d < %d)\n",
 336                                 __func__, rf, rf_min, rf >> 4, rf_max);
 337                         return rf;
 338                 }
 339         } while (1);
 340
 341         return 0;
 342 }
 343
 344 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
 345                                    unsigned layer)
 346 {
 347         int rc;
 348         static unsigned char reg[] = {
 349                 [0] = 0x86,     /* Layer A */
 350                 [1] = 0x8a,     /* Layer B */
 351                 [2] = 0x8e,     /* Layer C */
 352         };
 353
 354         if (layer >= ARRAY_SIZE(reg))
 355                 return -EINVAL;
 356         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 357         if (rc < 0)
 358                 return rc;
 359         rc = mb86a20s_readreg(state, 0x6e);
 360         if (rc < 0)
 361                 return rc;
 362         switch ((rc >> 4) & 0x07) {
 363         case 0:
 364                 return DQPSK;
 365         case 1:
 366                 return QPSK;
 367         case 2:
 368                 return QAM_16;
 369         case 3:
 370                 return QAM_64;
 371         default:
 372                 return QAM_AUTO;
 373         }
 374 }
 375
 376 static int mb86a20s_get_fec(struct mb86a20s_state *state,
 377                             unsigned layer)
 378 {
 379         int rc;
 380
 381         static unsigned char reg[] = {
 382                 [0] = 0x87,     /* Layer A */
 383                 [1] = 0x8b,     /* Layer B */
 384                 [2] = 0x8f,     /* Layer C */
 385         };
 386
 387         if (layer >= ARRAY_SIZE(reg))
 388                 return -EINVAL;
 389         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 390         if (rc < 0)
 391                 return rc;
 392         rc = mb86a20s_readreg(state, 0x6e);
 393         if (rc < 0)
 394                 return rc;
 395         switch ((rc >> 4) & 0x07) {
 396         case 0:
 397                 return FEC_1_2;
 398         case 1:
 399                 return FEC_2_3;
 400         case 2:
 401                 return FEC_3_4;
 402         case 3:
 403                 return FEC_5_6;
 404         case 4:
 405                 return FEC_7_8;
 406         default:
 407                 return FEC_AUTO;
 408         }
 409 }
 410
 411 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
 412                                      unsigned layer)
 413 {
 414         int rc;
 415
 416         static unsigned char reg[] = {
 417                 [0] = 0x88,     /* Layer A */
 418                 [1] = 0x8c,     /* Layer B */
 419                 [2] = 0x90,     /* Layer C */
 420         };
 421
 422         if (layer >= ARRAY_SIZE(reg))
 423                 return -EINVAL;
 424         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 425         if (rc < 0)
 426                 return rc;
 427         rc = mb86a20s_readreg(state, 0x6e);
 428         if (rc < 0)
 429                 return rc;
 430
 431         switch ((rc >> 4) & 0x07) {
 432         case 1:
 433                 return GUARD_INTERVAL_1_4;
 434         case 2:
 435                 return GUARD_INTERVAL_1_8;
 436         case 3:
 437                 return GUARD_INTERVAL_1_16;
 438         case 4:
 439                 return GUARD_INTERVAL_1_32;
 440
 441         default:
 442         case 0:
 443                 return GUARD_INTERVAL_AUTO;
 444         }
 445 }
 446
 447 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
 448                                       unsigned layer)
 449 {
 450         int rc, count;
 451         static unsigned char reg[] = {
 452                 [0] = 0x89,     /* Layer A */
 453                 [1] = 0x8d,     /* Layer B */
 454                 [2] = 0x91,     /* Layer C */
 455         };
 456
 457         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 458
 459         if (layer >= ARRAY_SIZE(reg))
 460                 return -EINVAL;
 461
 462         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 463         if (rc < 0)
 464                 return rc;
 465         rc = mb86a20s_readreg(state, 0x6e);
 466         if (rc < 0)
 467                 return rc;
 468         count = (rc >> 4) & 0x0f;
 469
 470         dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
 471
 472         return count;
 473 }
 474
 475 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
 476 {
 477         struct mb86a20s_state *state = fe->demodulator_priv;
 478         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 479
 480         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 481
 482         /* Fixed parameters */
 483         c->delivery_system = SYS_ISDBT;
 484         c->bandwidth_hz = 6000000;
 485
 486         /* Initialize values that will be later autodetected */
 487         c->isdbt_layer_enabled = 0;
 488         c->transmission_mode = TRANSMISSION_MODE_AUTO;
 489         c->guard_interval = GUARD_INTERVAL_AUTO;
 490         c->isdbt_sb_mode = 0;
 491         c->isdbt_sb_segment_count = 0;
 492 }
 493
 494 /*
 495  * Estimates the bit rate using the per-segment bit rate given by
 496  * ABNT/NBR 15601 spec (table 4).
 497  */
 498 static u32 isdbt_rate[3][5][4] = {
 499         {       /* DQPSK/QPSK */
 500                 {  280850,  312060,  330420,  340430 }, /* 1/2 */
 501                 {  374470,  416080,  440560,  453910 }, /* 2/3 */
 502                 {  421280,  468090,  495630,  510650 }, /* 3/4 */
 503                 {  468090,  520100,  550700,  567390 }, /* 5/6 */
 504                 {  491500,  546110,  578230,  595760 }, /* 7/8 */
 505         }, {    /* QAM16 */
 506                 {  561710,  624130,  660840,  680870 }, /* 1/2 */
 507                 {  748950,  832170,  881120,  907820 }, /* 2/3 */
 508                 {  842570,  936190,  991260, 1021300 }, /* 3/4 */
 509                 {  936190, 1040210, 1101400, 1134780 }, /* 5/6 */
 510                 {  983000, 1092220, 1156470, 1191520 }, /* 7/8 */
 511         }, {    /* QAM64 */
 512                 {  842570,  936190,  991260, 1021300 }, /* 1/2 */
 513                 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
 514                 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
 515                 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
 516                 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
 517         }
 518 };
 519
 520 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
 521                                    u32 modulation, u32 fec, u32 interleaving,
 522                                    u32 segment)
 523 {
 524         struct mb86a20s_state *state = fe->demodulator_priv;
 525         u32 rate;
 526         int m, f, i;
 527
 528         /*
 529          * If modulation/fec/interleaving is not detected, the default is
 530          * to consider the lowest bit rate, to avoid taking too long time
 531          * to get BER.
 532          */
 533         switch (modulation) {
 534         case DQPSK:
 535         case QPSK:
 536         default:
 537                 m = 0;
 538                 break;
 539         case QAM_16:
 540                 m = 1;
 541                 break;
 542         case QAM_64:
 543                 m = 2;
 544                 break;
 545         }
 546
 547         switch (fec) {
 548         default:
 549         case FEC_1_2:
 550         case FEC_AUTO:
 551                 f = 0;
 552                 break;
 553         case FEC_2_3:
 554                 f = 1;
 555                 break;
 556         case FEC_3_4:
 557                 f = 2;
 558                 break;
 559         case FEC_5_6:
 560                 f = 3;
 561                 break;
 562         case FEC_7_8:
 563                 f = 4;
 564                 break;
 565         }
 566
 567         switch (interleaving) {
 568         default:
 569         case GUARD_INTERVAL_1_4:
 570                 i = 0;
 571                 break;
 572         case GUARD_INTERVAL_1_8:
 573                 i = 1;
 574                 break;
 575         case GUARD_INTERVAL_1_16:
 576                 i = 2;
 577                 break;
 578         case GUARD_INTERVAL_1_32:
 579                 i = 3;
 580                 break;
 581         }
 582
 583         /* Samples BER at BER_SAMPLING_RATE seconds */
 584         rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE;
 585
 586         /* Avoids sampling too quickly or to overflow the register */
 587         if (rate < 256)
 588                 rate = 256;
 589         else if (rate > (1 << 24) - 1)
 590                 rate = (1 << 24) - 1;
 591
 592         dev_dbg(&state->i2c->dev,
 593                 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
 594                __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000,
 595                 rate, rate);
 596
 597         state->estimated_rate[i] = rate;
 598 }
 599
 600
 601 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
 602 {
 603         struct mb86a20s_state *state = fe->demodulator_priv;
 604         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 605         int i, rc;
 606
 607         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 608
 609         /* Reset frontend cache to default values */
 610         mb86a20s_reset_frontend_cache(fe);
 611
 612         /* Check for partial reception */
 613         rc = mb86a20s_writereg(state, 0x6d, 0x85);
 614         if (rc < 0)
 615                 return rc;
 616         rc = mb86a20s_readreg(state, 0x6e);
 617         if (rc < 0)
 618                 return rc;
 619         c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
 620
 621         /* Get per-layer data */
 622
 623         for (i = 0; i < 3; i++) {
 624                 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
 625                         __func__, 'A' + i);
 626
 627                 rc = mb86a20s_get_segment_count(state, i);
 628                 if (rc < 0)
 629                         goto noperlayer_error;
 630                 if (rc >= 0 && rc < 14) {
 631                         c->layer[i].segment_count = rc;
 632                 } else {
 633                         c->layer[i].segment_count = 0;
 634                         state->estimated_rate[i] = 0;
 635                         continue;
 636                 }
 637                 c->isdbt_layer_enabled |= 1 << i;
 638                 rc = mb86a20s_get_modulation(state, i);
 639                 if (rc < 0)
 640                         goto noperlayer_error;
 641                 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
 642                         __func__, rc);
 643                 c->layer[i].modulation = rc;
 644                 rc = mb86a20s_get_fec(state, i);
 645                 if (rc < 0)
 646                         goto noperlayer_error;
 647                 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
 648                         __func__, rc);
 649                 c->layer[i].fec = rc;
 650                 rc = mb86a20s_get_interleaving(state, i);
 651                 if (rc < 0)
 652                         goto noperlayer_error;
 653                 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
 654                         __func__, rc);
 655                 c->layer[i].interleaving = rc;
 656                 mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation,
 657                                        c->layer[i].fec,
 658                                        c->layer[i].interleaving,
 659                                        c->layer[i].segment_count);
 660         }
 661
 662         rc = mb86a20s_writereg(state, 0x6d, 0x84);
 663         if (rc < 0)
 664                 return rc;
 665         if ((rc & 0x60) == 0x20) {
 666                 c->isdbt_sb_mode = 1;
 667                 /* At least, one segment should exist */
 668                 if (!c->isdbt_sb_segment_count)
 669                         c->isdbt_sb_segment_count = 1;
 670         }
 671
 672         /* Get transmission mode and guard interval */
 673         rc = mb86a20s_readreg(state, 0x07);
 674         if (rc < 0)
 675                 return rc;
 676         if ((rc & 0x60) == 0x20) {
 677                 switch (rc & 0x0c >> 2) {
 678                 case 0:
 679                         c->transmission_mode = TRANSMISSION_MODE_2K;
 680                         break;
 681                 case 1:
 682                         c->transmission_mode = TRANSMISSION_MODE_4K;
 683                         break;
 684                 case 2:
 685                         c->transmission_mode = TRANSMISSION_MODE_8K;
 686                         break;
 687                 }
 688         }
 689         if (!(rc & 0x10)) {
 690                 switch (rc & 0x3) {
 691                 case 0:
 692                         c->guard_interval = GUARD_INTERVAL_1_4;
 693                         break;
 694                 case 1:
 695                         c->guard_interval = GUARD_INTERVAL_1_8;
 696                         break;
 697                 case 2:
 698                         c->guard_interval = GUARD_INTERVAL_1_16;
 699                         break;
 700                 }
 701         }
 702         return 0;
 703
 704 noperlayer_error:
 705
 706         /* per-layer info is incomplete; discard all per-layer */
 707         c->isdbt_layer_enabled = 0;
 708
 709         return rc;
 710 }
 711
 712 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
 713 {
 714         struct mb86a20s_state *state = fe->demodulator_priv;
 715         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 716         int rc, val;
 717
 718         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 719
 720         /* Reset the counters, if the channel changed */
 721         if (state->last_frequency != c->frequency) {
 722                 memset(&c->strength, 0, sizeof(c->strength));
 723                 memset(&c->cnr, 0, sizeof(c->cnr));
 724                 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
 725                 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
 726                 memset(&c->block_error, 0, sizeof(c->block_error));
 727                 memset(&c->block_count, 0, sizeof(c->block_count));
 728
 729                 state->last_frequency = c->frequency;
 730         }
 731
 732         /* Clear status for most stats */
 733
 734         /* BER counter reset */
 735         rc = mb86a20s_writeregdata(state, mb86a20s_vber_reset);
 736         if (rc < 0)
 737                 goto err;
 738
 739         /* MER, PER counter reset */
 740         rc = mb86a20s_writeregdata(state, mb86a20s_per_reset);
 741         if (rc < 0)
 742                 goto err;
 743
 744         /* CNR counter reset */
 745         rc = mb86a20s_readreg(state, 0x45);
 746         if (rc < 0)
 747                 goto err;
 748         val = rc;
 749         rc = mb86a20s_writereg(state, 0x45, val | 0x10);
 750         if (rc < 0)
 751                 goto err;
 752         rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
 753         if (rc < 0)
 754                 goto err;
 755
 756         /* MER counter reset */
 757         rc = mb86a20s_writereg(state, 0x50, 0x50);
 758         if (rc < 0)
 759                 goto err;
 760         rc = mb86a20s_readreg(state, 0x51);
 761         if (rc < 0)
 762                 goto err;
 763         val = rc;
 764         rc = mb86a20s_writereg(state, 0x51, val | 0x01);
 765         if (rc < 0)
 766                 goto err;
 767         rc = mb86a20s_writereg(state, 0x51, val & 0x06);
 768         if (rc < 0)
 769                 goto err;
 770
 771         goto ok;
 772 err:
 773         dev_err(&state->i2c->dev,
 774                 "%s: Can't reset FE statistics (error %d).\n",
 775                 __func__, rc);
 776 ok:
 777         return rc;
 778 }
 779
 780 static int mb86a20s_get_ber_before_vterbi(struct dvb_frontend *fe,
 781                                           unsigned layer,
 782                                           u32 *error, u32 *count)
 783 {
 784         struct mb86a20s_state *state = fe->demodulator_priv;
 785         int rc;
 786
 787         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 788
 789         if (layer >= 3)
 790                 return -EINVAL;
 791
 792         /* Check if the BER measures are already available */
 793         rc = mb86a20s_readreg(state, 0x54);
 794         if (rc < 0)
 795                 return rc;
 796
 797         /* Check if data is available for that layer */
 798         if (!(rc & (1 << layer))) {
 799                 dev_dbg(&state->i2c->dev,
 800                         "%s: BER for layer %c is not available yet.\n",
 801                         __func__, 'A' + layer);
 802                 return -EBUSY;
 803         }
 804
 805         /* Read Bit Error Count */
 806         rc = mb86a20s_readreg(state, 0x55 + layer * 3);
 807         if (rc < 0)
 808                 return rc;
 809         *error = rc << 16;
 810         rc = mb86a20s_readreg(state, 0x56 + layer * 3);
 811         if (rc < 0)
 812                 return rc;
 813         *error |= rc << 8;
 814         rc = mb86a20s_readreg(state, 0x57 + layer * 3);
 815         if (rc < 0)
 816                 return rc;
 817         *error |= rc;
 818
 819         dev_dbg(&state->i2c->dev,
 820                 "%s: bit error before Viterbi for layer %c: %d.\n",
 821                 __func__, 'A' + layer, *error);
 822
 823         /* Read Bit Count */
 824         rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
 825         if (rc < 0)
 826                 return rc;
 827         rc = mb86a20s_readreg(state, 0x51);
 828         if (rc < 0)
 829                 return rc;
 830         *count = rc << 16;
 831         rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
 832         if (rc < 0)
 833                 return rc;
 834         rc = mb86a20s_readreg(state, 0x51);
 835         if (rc < 0)
 836                 return rc;
 837         *count |= rc << 8;
 838         rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
 839         if (rc < 0)
 840                 return rc;
 841         rc = mb86a20s_readreg(state, 0x51);
 842         if (rc < 0)
 843                 return rc;
 844         *count |= rc;
 845
 846         dev_dbg(&state->i2c->dev,
 847                 "%s: bit count before Viterbi for layer %c: %d.\n",
 848                 __func__, 'A' + layer, *count);
 849
 850
 851         /*
 852          * As we get TMCC data from the frontend, we can better estimate the
 853          * BER bit counters, in order to do the BER measure during a longer
 854          * time. Use those data, if available, to update the bit count
 855          * measure.
 856          */
 857
 858         if (state->estimated_rate[layer]
 859             && state->estimated_rate[layer] != *count) {
 860                 dev_dbg(&state->i2c->dev,
 861                         "%s: updating layer %c counter to %d.\n",
 862                         __func__, 'A' + layer, state->estimated_rate[layer]);
 863                 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
 864                 if (rc < 0)
 865                         return rc;
 866                 rc = mb86a20s_writereg(state, 0x51,
 867                                        state->estimated_rate[layer] >> 16);
 868                 if (rc < 0)
 869                         return rc;
 870                 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
 871                 if (rc < 0)
 872                         return rc;
 873                 rc = mb86a20s_writereg(state, 0x51,
 874                                        state->estimated_rate[layer] >> 8);
 875                 if (rc < 0)
 876                         return rc;
 877                 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
 878                 if (rc < 0)
 879                         return rc;
 880                 rc = mb86a20s_writereg(state, 0x51,
 881                                        state->estimated_rate[layer]);
 882                 if (rc < 0)
 883                         return rc;
 884         }
 885
 886
 887         /* Reset counter to collect new data */
 888         rc = mb86a20s_writereg(state, 0x53, 0x07 & ~(1 << layer));
 889         if (rc < 0)
 890                 return rc;
 891         rc = mb86a20s_writereg(state, 0x53, 0x07);
 892
 893         return 0;
 894 }
 895
 896 struct linear_segments {
 897         unsigned x, y;
 898 };
 899
 900 /*
 901  * All tables below return a dB/1000 measurement
 902  */
 903
 904 static struct linear_segments cnr_to_db_table[] = {
 905         { 19648,     0},
 906         { 18187,  1000},
 907         { 16534,  2000},
 908         { 14823,  3000},
 909         { 13161,  4000},
 910         { 11622,  5000},
 911         { 10279,  6000},
 912         {  9089,  7000},
 913         {  8042,  8000},
 914         {  7137,  9000},
 915         {  6342, 10000},
 916         {  5641, 11000},
 917         {  5030, 12000},
 918         {  4474, 13000},
 919         {  3988, 14000},
 920         {  3556, 15000},
 921         {  3180, 16000},
 922         {  2841, 17000},
 923         {  2541, 18000},
 924         {  2276, 19000},
 925         {  2038, 20000},
 926         {  1800, 21000},
 927         {  1625, 22000},
 928         {  1462, 23000},
 929         {  1324, 24000},
 930         {  1175, 25000},
 931         {  1063, 26000},
 932         {   980, 27000},
 933         {   907, 28000},
 934         {   840, 29000},
 935         {   788, 30000},
 936 };
 937
 938 static struct linear_segments cnr_64qam_table[] = {
 939         { 3922688,     0},
 940         { 3920384,  1000},
 941         { 3902720,  2000},
 942         { 3894784,  3000},
 943         { 3882496,  4000},
 944         { 3872768,  5000},
 945         { 3858944,  6000},
 946         { 3851520,  7000},
 947         { 3838976,  8000},
 948         { 3829248,  9000},
 949         { 3818240, 10000},
 950         { 3806976, 11000},
 951         { 3791872, 12000},
 952         { 3767040, 13000},
 953         { 3720960, 14000},
 954         { 3637504, 15000},
 955         { 3498496, 16000},
 956         { 3296000, 17000},
 957         { 3031040, 18000},
 958         { 2715392, 19000},
 959         { 2362624, 20000},
 960         { 1963264, 21000},
 961         { 1649664, 22000},
 962         { 1366784, 23000},
 963         { 1120768, 24000},
 964         {  890880, 25000},
 965         {  723456, 26000},
 966         {  612096, 27000},
 967         {  518912, 28000},
 968         {  448256, 29000},
 969         {  388864, 30000},
 970 };
 971
 972 static struct linear_segments cnr_16qam_table[] = {
 973         { 5314816,     0},
 974         { 5219072,  1000},
 975         { 5118720,  2000},
 976         { 4998912,  3000},
 977         { 4875520,  4000},
 978         { 4736000,  5000},
 979         { 4604160,  6000},
 980         { 4458752,  7000},
 981         { 4300288,  8000},
 982         { 4092928,  9000},
 983         { 3836160, 10000},
 984         { 3521024, 11000},
 985         { 3155968, 12000},
 986         { 2756864, 13000},
 987         { 2347008, 14000},
 988         { 1955072, 15000},
 989         { 1593600, 16000},
 990         { 1297920, 17000},
 991         { 1043968, 18000},
 992         {  839680, 19000},
 993         {  672256, 20000},
 994         {  523008, 21000},
 995         {  424704, 22000},
 996         {  345088, 23000},
 997         {  280064, 24000},
 998         {  221440, 25000},
 999         {  179712, 26000},
1000         {  151040, 27000},
1001         {  128512, 28000},
1002         {  110080, 29000},
1003         {   95744, 30000},
1004 };
1005
1006 struct linear_segments cnr_qpsk_table[] = {
1007         { 2834176,     0},
1008         { 2683648,  1000},
1009         { 2536960,  2000},
1010         { 2391808,  3000},
1011         { 2133248,  4000},
1012         { 1906176,  5000},
1013         { 1666560,  6000},
1014         { 1422080,  7000},
1015         { 1189632,  8000},
1016         {  976384,  9000},
1017         {  790272, 10000},
1018         {  633344, 11000},
1019         {  505600, 12000},
1020         {  402944, 13000},
1021         {  320768, 14000},
1022         {  255488, 15000},
1023         {  204032, 16000},
1024         {  163072, 17000},
1025         {  130304, 18000},
1026         {  105216, 19000},
1027         {   83456, 20000},
1028         {   65024, 21000},
1029         {   52480, 22000},
1030         {   42752, 23000},
1031         {   34560, 24000},
1032         {   27136, 25000},
1033         {   22016, 26000},
1034         {   18432, 27000},
1035         {   15616, 28000},
1036         {   13312, 29000},
1037         {   11520, 30000},
1038 };
1039
1040 static u32 interpolate_value(u32 value, struct linear_segments *segments,
1041                              unsigned len)
1042 {
1043         u64 tmp64;
1044         u32 dx, dy;
1045         int i, ret;
1046
1047         if (value >= segments[0].x)
1048                 return segments[0].y;
1049         if (value < segments[len-1].x)
1050                 return segments[len-1].y;
1051
1052         for (i = 1; i < len - 1; i++) {
1053                 /* If value is identical, no need to interpolate */
1054                 if (value == segments[i].x)
1055                         return segments[i].y;
1056                 if (value > segments[i].x)
1057                         break;
1058         }
1059
1060         /* Linear interpolation between the two (x,y) points */
1061         dy = segments[i].y - segments[i - 1].y;
1062         dx = segments[i - 1].x - segments[i].x;
1063         tmp64 = value - segments[i].x;
1064         tmp64 *= dy;
1065         do_div(tmp64, dx);
1066         ret = segments[i].y - tmp64;
1067
1068         return ret;
1069 }
1070
1071 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1072 {
1073         struct mb86a20s_state *state = fe->demodulator_priv;
1074         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1075         u32 cnr_linear, cnr;
1076         int rc, val;
1077
1078         /* Check if CNR is available */
1079         rc = mb86a20s_readreg(state, 0x45);
1080         if (rc < 0)
1081                 return rc;
1082
1083         if (!(rc & 0x40)) {
1084                 dev_info(&state->i2c->dev, "%s: CNR is not available yet.\n",
1085                          __func__);
1086                 return -EBUSY;
1087         }
1088         val = rc;
1089
1090         rc = mb86a20s_readreg(state, 0x46);
1091         if (rc < 0)
1092                 return rc;
1093         cnr_linear = rc << 8;
1094
1095         rc = mb86a20s_readreg(state, 0x46);
1096         if (rc < 0)
1097                 return rc;
1098         cnr_linear |= rc;
1099
1100         cnr = interpolate_value(cnr_linear,
1101                                 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1102
1103         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1104         c->cnr.stat[0].svalue = cnr;
1105
1106         dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1107                 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1108
1109         /* CNR counter reset */
1110         rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1111         if (rc < 0)
1112                 return rc;
1113         rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1114
1115         return rc;
1116 }
1117
1118 static int mb86a20s_get_per_layer_CNR(struct dvb_frontend *fe)
1119 {
1120         struct mb86a20s_state *state = fe->demodulator_priv;
1121         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1122         u32 mer, cnr;
1123         int rc, val, i;
1124         struct linear_segments *segs;
1125         unsigned segs_len;
1126
1127         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1128
1129         /* Check if the measures are already available */
1130         rc = mb86a20s_writereg(state, 0x50, 0x5b);
1131         if (rc < 0)
1132                 return rc;
1133         rc = mb86a20s_readreg(state, 0x51);
1134         if (rc < 0)
1135                 return rc;
1136
1137         /* Check if data is available */
1138         if (!(rc & 0x01)) {
1139                 dev_info(&state->i2c->dev,
1140                         "%s: MER measures aren't available yet.\n", __func__);
1141                 return -EBUSY;
1142         }
1143
1144         /* Read all layers */
1145         for (i = 0; i < 3; i++) {
1146                 if (!(c->isdbt_layer_enabled & (1 << i))) {
1147                         c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1148                         continue;
1149                 }
1150
1151                 rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3);
1152                 if (rc < 0)
1153                         return rc;
1154                 rc = mb86a20s_readreg(state, 0x51);
1155                 if (rc < 0)
1156                         return rc;
1157                 mer = rc << 16;
1158                 rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3);
1159                 if (rc < 0)
1160                         return rc;
1161                 rc = mb86a20s_readreg(state, 0x51);
1162                 if (rc < 0)
1163                         return rc;
1164                 mer |= rc << 8;
1165                 rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3);
1166                 if (rc < 0)
1167                         return rc;
1168                 rc = mb86a20s_readreg(state, 0x51);
1169                 if (rc < 0)
1170                         return rc;
1171                 mer |= rc;
1172
1173                 switch (c->layer[i].modulation) {
1174                 case DQPSK:
1175                 case QPSK:
1176                         segs = cnr_qpsk_table;
1177                         segs_len = ARRAY_SIZE(cnr_qpsk_table);
1178                         break;
1179                 case QAM_16:
1180                         segs = cnr_16qam_table;
1181                         segs_len = ARRAY_SIZE(cnr_16qam_table);
1182                         break;
1183                 default:
1184                 case QAM_64:
1185                         segs = cnr_64qam_table;
1186                         segs_len = ARRAY_SIZE(cnr_64qam_table);
1187                         break;
1188                 }
1189                 cnr = interpolate_value(mer, segs, segs_len);
1190
1191                 c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL;
1192                 c->cnr.stat[1 + i].svalue = cnr;
1193
1194                 dev_dbg(&state->i2c->dev,
1195                         "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1196                         __func__, 'A' + i, cnr / 1000, cnr % 1000, mer);
1197
1198         }
1199
1200         /* Start a new MER measurement */
1201         /* MER counter reset */
1202         rc = mb86a20s_writereg(state, 0x50, 0x50);
1203         if (rc < 0)
1204                 return rc;
1205         rc = mb86a20s_readreg(state, 0x51);
1206         if (rc < 0)
1207                 return rc;
1208         val = rc;
1209
1210         rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1211         if (rc < 0)
1212                 return rc;
1213         rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1214         if (rc < 0)
1215                 return rc;
1216
1217         return 0;
1218 }
1219
1220 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1221 {
1222         struct mb86a20s_state *state = fe->demodulator_priv;
1223         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1224         int i;
1225
1226         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1227
1228         /* Fill the length of each status counter */
1229
1230         /* Only global stats */
1231         c->strength.len = 1;
1232
1233         /* Per-layer stats - 3 layers + global */
1234         c->cnr.len = 4;
1235         c->pre_bit_error.len = 4;
1236         c->pre_bit_count.len = 4;
1237         c->block_error.len = 4;
1238         c->block_count.len = 4;
1239
1240         /* Signal is always available */
1241         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1242         c->strength.stat[0].uvalue = 0;
1243
1244         /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1245         for (i = 0; i < 4; i++) {
1246                 c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1247                 c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1248                 c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1249                 c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1250                 c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1251         }
1252 }
1253
1254 static int mb86a20s_get_stats(struct dvb_frontend *fe)
1255 {
1256         struct mb86a20s_state *state = fe->demodulator_priv;
1257         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1258         int rc = 0, i;
1259         u32 bit_error = 0, bit_count = 0;
1260         u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1261         int active_layers = 0, ber_layers = 0;
1262
1263         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1264
1265         mb86a20s_get_main_CNR(fe);
1266
1267         /* Get per-layer stats */
1268         mb86a20s_get_per_layer_CNR(fe);
1269
1270         for (i = 0; i < 3; i++) {
1271                 if (c->isdbt_layer_enabled & (1 << i)) {
1272                         /* Layer is active and has rc segments */
1273                         active_layers++;
1274
1275                         /* Read per-layer BER */
1276                         /* Handle BER before vterbi */
1277                         rc = mb86a20s_get_ber_before_vterbi(fe, i,
1278                                                         &bit_error,
1279                                                         &bit_count);
1280                         if (rc >= 0) {
1281                                 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1282                                 c->pre_bit_error.stat[1 + i].uvalue += bit_error;
1283                                 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1284                                 c->pre_bit_count.stat[1 + i].uvalue += bit_count;
1285                         } else if (rc != -EBUSY) {
1286                                 /*
1287                                         * If an I/O error happened,
1288                                         * measures are now unavailable
1289                                         */
1290                                 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1291                                 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1292                                 dev_err(&state->i2c->dev,
1293                                         "%s: Can't get BER for layer %c (error %d).\n",
1294                                         __func__, 'A' + i, rc);
1295                         }
1296
1297                         if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1298                                 ber_layers++;
1299
1300                         /* Update total BER */
1301                         t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue;
1302                         t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue;
1303                 }
1304         }
1305
1306         /*
1307          * Start showing global count if at least one error count is
1308          * available.
1309          */
1310         if (ber_layers) {
1311                 /*
1312                  * At least one per-layer BER measure was read. We can now
1313                  * calculate the total BER
1314                  *
1315                  * Total Bit Error/Count is calculated as the sum of the
1316                  * bit errors on all active layers.
1317                  */
1318                 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1319                 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1320                 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1321                 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1322         }
1323
1324         return rc;
1325 }
1326
1327 /*
1328  * The functions below are called via DVB callbacks, so they need to
1329  * properly use the I2C gate control
1330  */
1331
1332 static int mb86a20s_initfe(struct dvb_frontend *fe)
1333 {
1334         struct mb86a20s_state *state = fe->demodulator_priv;
1335         int rc;
1336         u8  regD5 = 1;
1337
1338         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1339
1340         if (fe->ops.i2c_gate_ctrl)
1341                 fe->ops.i2c_gate_ctrl(fe, 0);
1342
1343         /* Initialize the frontend */
1344         rc = mb86a20s_writeregdata(state, mb86a20s_init);
1345         if (rc < 0)
1346                 goto err;
1347
1348         if (!state->config->is_serial) {
1349                 regD5 &= ~1;
1350
1351                 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1352                 if (rc < 0)
1353                         goto err;
1354                 rc = mb86a20s_writereg(state, 0x51, regD5);
1355                 if (rc < 0)
1356                         goto err;
1357         }
1358
1359 err:
1360         if (fe->ops.i2c_gate_ctrl)
1361                 fe->ops.i2c_gate_ctrl(fe, 1);
1362
1363         if (rc < 0) {
1364                 state->need_init = true;
1365                 dev_info(&state->i2c->dev,
1366                          "mb86a20s: Init failed. Will try again later\n");
1367         } else {
1368                 state->need_init = false;
1369                 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1370         }
1371         return rc;
1372 }
1373
1374 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1375 {
1376         struct mb86a20s_state *state = fe->demodulator_priv;
1377         int rc;
1378 #if 0
1379         /*
1380          * FIXME: Properly implement the set frontend properties
1381          */
1382         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1383 #endif
1384         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1385
1386         /*
1387          * Gate should already be opened, but it doesn't hurt to
1388          * double-check
1389          */
1390         if (fe->ops.i2c_gate_ctrl)
1391                 fe->ops.i2c_gate_ctrl(fe, 1);
1392         fe->ops.tuner_ops.set_params(fe);
1393
1394         /*
1395          * Make it more reliable: if, for some reason, the initial
1396          * device initialization doesn't happen, initialize it when
1397          * a SBTVD parameters are adjusted.
1398          *
1399          * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1400          * the agc callback logic is not called during DVB attach time,
1401          * causing mb86a20s to not be initialized with Kworld SBTVD.
1402          * So, this hack is needed, in order to make Kworld SBTVD to work.
1403          */
1404         if (state->need_init)
1405                 mb86a20s_initfe(fe);
1406
1407         if (fe->ops.i2c_gate_ctrl)
1408                 fe->ops.i2c_gate_ctrl(fe, 0);
1409
1410         rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1411         mb86a20s_reset_counters(fe);
1412
1413         if (fe->ops.i2c_gate_ctrl)
1414                 fe->ops.i2c_gate_ctrl(fe, 1);
1415
1416         return rc;
1417 }
1418
1419 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1420                                           fe_status_t *status)
1421 {
1422         struct mb86a20s_state *state = fe->demodulator_priv;
1423         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1424         int rc;
1425
1426         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1427
1428         if (fe->ops.i2c_gate_ctrl)
1429                 fe->ops.i2c_gate_ctrl(fe, 0);
1430
1431         /* Get lock */
1432         rc = mb86a20s_read_status(fe, status);
1433         if (!(*status & FE_HAS_LOCK)) {
1434                 mb86a20s_stats_not_ready(fe);
1435                 mb86a20s_reset_frontend_cache(fe);
1436         }
1437         if (rc < 0) {
1438                 dev_err(&state->i2c->dev,
1439                         "%s: Can't read frontend lock status\n", __func__);
1440                 goto error;
1441         }
1442
1443         /* Get signal strength */
1444         rc = mb86a20s_read_signal_strength(fe);
1445         if (rc < 0) {
1446                 dev_err(&state->i2c->dev,
1447                         "%s: Can't reset VBER registers.\n", __func__);
1448                 mb86a20s_stats_not_ready(fe);
1449                 mb86a20s_reset_frontend_cache(fe);
1450
1451                 rc = 0;         /* Status is OK */
1452                 goto error;
1453         }
1454         /* Fill signal strength */
1455         c->strength.stat[0].uvalue = rc;
1456
1457         if (*status & FE_HAS_LOCK) {
1458                 /* Get TMCC info*/
1459                 rc = mb86a20s_get_frontend(fe);
1460                 if (rc < 0) {
1461                         dev_err(&state->i2c->dev,
1462                                 "%s: Can't get FE TMCC data.\n", __func__);
1463                         rc = 0;         /* Status is OK */
1464                         goto error;
1465                 }
1466
1467                 /* Get statistics */
1468                 rc = mb86a20s_get_stats(fe);
1469                 if (rc < 0 && rc != -EBUSY) {
1470                         dev_err(&state->i2c->dev,
1471                                 "%s: Can't get FE statistics.\n", __func__);
1472                         rc = 0;
1473                         goto error;
1474                 }
1475                 rc = 0; /* Don't return EBUSY to userspace */
1476         }
1477         goto ok;
1478
1479 error:
1480         mb86a20s_stats_not_ready(fe);
1481
1482 ok:
1483         if (fe->ops.i2c_gate_ctrl)
1484                 fe->ops.i2c_gate_ctrl(fe, 1);
1485
1486         return rc;
1487 }
1488
1489 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
1490                                                     u16 *strength)
1491 {
1492         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1493
1494
1495         *strength = c->strength.stat[0].uvalue;
1496
1497         return 0;
1498 }
1499
1500 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
1501 {
1502         /*
1503          * get_frontend is now handled together with other stats
1504          * retrival, when read_status() is called, as some statistics
1505          * will depend on the layers detection.
1506          */
1507         return 0;
1508 };
1509
1510 static int mb86a20s_tune(struct dvb_frontend *fe,
1511                         bool re_tune,
1512                         unsigned int mode_flags,
1513                         unsigned int *delay,
1514                         fe_status_t *status)
1515 {
1516         struct mb86a20s_state *state = fe->demodulator_priv;
1517         int rc = 0;
1518
1519         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1520
1521         if (re_tune)
1522                 rc = mb86a20s_set_frontend(fe);
1523
1524         if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1525                 mb86a20s_read_status_and_stats(fe, status);
1526
1527         return rc;
1528 }
1529
1530 static void mb86a20s_release(struct dvb_frontend *fe)
1531 {
1532         struct mb86a20s_state *state = fe->demodulator_priv;
1533
1534         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1535
1536         kfree(state);
1537 }
1538
1539 static struct dvb_frontend_ops mb86a20s_ops;
1540
1541 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
1542                                     struct i2c_adapter *i2c)
1543 {
1544         struct mb86a20s_state *state;
1545         u8      rev;
1546
1547         dev_dbg(&i2c->dev, "%s called.\n", __func__);
1548
1549         /* allocate memory for the internal state */
1550         state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
1551         if (state == NULL) {
1552                 dev_err(&i2c->dev,
1553                         "%s: unable to allocate memory for state\n", __func__);
1554                 goto error;
1555         }
1556
1557         /* setup the state */
1558         state->config = config;
1559         state->i2c = i2c;
1560
1561         /* create dvb_frontend */
1562         memcpy(&state->frontend.ops, &mb86a20s_ops,
1563                 sizeof(struct dvb_frontend_ops));
1564         state->frontend.demodulator_priv = state;
1565
1566         /* Check if it is a mb86a20s frontend */
1567         rev = mb86a20s_readreg(state, 0);
1568
1569         if (rev == 0x13) {
1570                 dev_info(&i2c->dev,
1571                          "Detected a Fujitsu mb86a20s frontend\n");
1572         } else {
1573                 dev_dbg(&i2c->dev,
1574                         "Frontend revision %d is unknown - aborting.\n",
1575                        rev);
1576                 goto error;
1577         }
1578
1579         return &state->frontend;
1580
1581 error:
1582         kfree(state);
1583         return NULL;
1584 }
1585 EXPORT_SYMBOL(mb86a20s_attach);
1586
1587 static struct dvb_frontend_ops mb86a20s_ops = {
1588         .delsys = { SYS_ISDBT },
1589         /* Use dib8000 values per default */
1590         .info = {
1591                 .name = "Fujitsu mb86A20s",
1592                 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER |
1593                         FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1594                         FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1595                         FE_CAN_QPSK     | FE_CAN_QAM_16  | FE_CAN_QAM_64 |
1596                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
1597                         FE_CAN_GUARD_INTERVAL_AUTO    | FE_CAN_HIERARCHY_AUTO,
1598                 /* Actually, those values depend on the used tuner */
1599                 .frequency_min = 45000000,
1600                 .frequency_max = 864000000,
1601                 .frequency_stepsize = 62500,
1602         },
1603
1604         .release = mb86a20s_release,
1605
1606         .init = mb86a20s_initfe,
1607         .set_frontend = mb86a20s_set_frontend,
1608         .get_frontend = mb86a20s_get_frontend_dummy,
1609         .read_status = mb86a20s_read_status_and_stats,
1610         .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
1611         .tune = mb86a20s_tune,
1612 };
1613
1614 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
1615 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1616 MODULE_LICENSE("GPL");