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[media] mb86a20s: add block count measures (PER/UCB)
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / mb86a20s.c
1 /*
2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
3 *
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
19
20 #include "dvb_frontend.h"
21 #include "mb86a20s.h"
22
23 static int debug = 1;
24 module_param(debug, int, 0644);
25 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
26
27 struct mb86a20s_state {
28 struct i2c_adapter *i2c;
29 const struct mb86a20s_config *config;
30 u32 last_frequency;
31
32 struct dvb_frontend frontend;
33
34 u32 estimated_rate[3];
35
36 bool need_init;
37 };
38
39 struct regdata {
40 u8 reg;
41 u8 data;
42 };
43
44 #define BER_SAMPLING_RATE 1 /* Seconds */
45
46 /*
47 * Initialization sequence: Use whatevere default values that PV SBTVD
48 * does on its initialisation, obtained via USB snoop
49 */
50 static struct regdata mb86a20s_init[] = {
51 { 0x70, 0x0f },
52 { 0x70, 0xff },
53 { 0x08, 0x01 },
54 { 0x09, 0x3e },
55 { 0x50, 0xd1 }, { 0x51, 0x22 },
56 { 0x39, 0x01 },
57 { 0x71, 0x00 },
58 { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 },
59 { 0x28, 0x20 }, { 0x29, 0x33 }, { 0x2a, 0xdf }, { 0x2b, 0xa9 },
60 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
61 { 0x3b, 0x21 },
62 { 0x3c, 0x3a },
63 { 0x01, 0x0d },
64 { 0x04, 0x08 }, { 0x05, 0x05 },
65 { 0x04, 0x0e }, { 0x05, 0x00 },
66 { 0x04, 0x0f }, { 0x05, 0x14 },
67 { 0x04, 0x0b }, { 0x05, 0x8c },
68 { 0x04, 0x00 }, { 0x05, 0x00 },
69 { 0x04, 0x01 }, { 0x05, 0x07 },
70 { 0x04, 0x02 }, { 0x05, 0x0f },
71 { 0x04, 0x03 }, { 0x05, 0xa0 },
72 { 0x04, 0x09 }, { 0x05, 0x00 },
73 { 0x04, 0x0a }, { 0x05, 0xff },
74 { 0x04, 0x27 }, { 0x05, 0x64 },
75 { 0x04, 0x28 }, { 0x05, 0x00 },
76 { 0x04, 0x1e }, { 0x05, 0xff },
77 { 0x04, 0x29 }, { 0x05, 0x0a },
78 { 0x04, 0x32 }, { 0x05, 0x0a },
79 { 0x04, 0x14 }, { 0x05, 0x02 },
80 { 0x04, 0x04 }, { 0x05, 0x00 },
81 { 0x04, 0x05 }, { 0x05, 0x22 },
82 { 0x04, 0x06 }, { 0x05, 0x0e },
83 { 0x04, 0x07 }, { 0x05, 0xd8 },
84 { 0x04, 0x12 }, { 0x05, 0x00 },
85 { 0x04, 0x13 }, { 0x05, 0xff },
86 { 0x04, 0x15 }, { 0x05, 0x4e },
87 { 0x04, 0x16 }, { 0x05, 0x20 },
88
89 /*
90 * On this demod, when the bit count reaches the count below,
91 * it collects the bit error count. The bit counters are initialized
92 * to 65535 here. This warrants that all of them will be quickly
93 * calculated when device gets locked. As TMCC is parsed, the values
94 * will be adjusted later in the driver's code.
95 */
96 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
97 { 0x50, 0xa7 }, { 0x51, 0x00 },
98 { 0x50, 0xa8 }, { 0x51, 0xff },
99 { 0x50, 0xa9 }, { 0x51, 0xff },
100 { 0x50, 0xaa }, { 0x51, 0x00 },
101 { 0x50, 0xab }, { 0x51, 0xff },
102 { 0x50, 0xac }, { 0x51, 0xff },
103 { 0x50, 0xad }, { 0x51, 0x00 },
104 { 0x50, 0xae }, { 0x51, 0xff },
105 { 0x50, 0xaf }, { 0x51, 0xff },
106
107 { 0x5e, 0x00 }, /* Turn off BER after Viterbi */
108 { 0x50, 0xdc }, { 0x51, 0x01 },
109 { 0x50, 0xdd }, { 0x51, 0xf4 },
110 { 0x50, 0xde }, { 0x51, 0x01 },
111 { 0x50, 0xdf }, { 0x51, 0xf4 },
112 { 0x50, 0xe0 }, { 0x51, 0x01 },
113 { 0x50, 0xe1 }, { 0x51, 0xf4 },
114
115 /*
116 * On this demod, when the block count reaches the count below,
117 * it collects the block error count. The block counters are initialized
118 * to 127 here. This warrants that all of them will be quickly
119 * calculated when device gets locked. As TMCC is parsed, the values
120 * will be adjusted later in the driver's code.
121 */
122 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
123 { 0x50, 0xb2 }, { 0x51, 0x00 },
124 { 0x50, 0xb3 }, { 0x51, 0x7f },
125 { 0x50, 0xb4 }, { 0x51, 0x00 },
126 { 0x50, 0xb5 }, { 0x51, 0x7f },
127 { 0x50, 0xb6 }, { 0x51, 0x00 },
128 { 0x50, 0xb7 }, { 0x51, 0x7f },
129
130 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
131 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
132 { 0x45, 0x04 }, /* CN symbol 4 */
133 { 0x48, 0x04 }, /* CN manual mode */
134
135 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
136 { 0x50, 0xd6 }, { 0x51, 0x1f },
137 { 0x50, 0xd2 }, { 0x51, 0x03 },
138 { 0x50, 0xd7 }, { 0x51, 0x3f },
139 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 },
140 { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c },
141
142 { 0x04, 0x40 }, { 0x05, 0x00 },
143 { 0x28, 0x00 }, { 0x29, 0x10 },
144 { 0x28, 0x05 }, { 0x29, 0x02 },
145 { 0x1c, 0x01 },
146 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
147 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
148 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
149 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
150 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
151 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
152 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
153 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
154 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
155 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
156 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
157 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
158 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
159 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
160 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
161 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
162 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
163 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
164 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
165 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
166 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
167 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
168 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
169 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
170 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
171 { 0x50, 0x1e }, { 0x51, 0x5d },
172 { 0x50, 0x22 }, { 0x51, 0x00 },
173 { 0x50, 0x23 }, { 0x51, 0xc8 },
174 { 0x50, 0x24 }, { 0x51, 0x00 },
175 { 0x50, 0x25 }, { 0x51, 0xf0 },
176 { 0x50, 0x26 }, { 0x51, 0x00 },
177 { 0x50, 0x27 }, { 0x51, 0xc3 },
178 { 0x50, 0x39 }, { 0x51, 0x02 },
179 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
180 { 0xd0, 0x00 },
181 };
182
183 static struct regdata mb86a20s_reset_reception[] = {
184 { 0x70, 0xf0 },
185 { 0x70, 0xff },
186 { 0x08, 0x01 },
187 { 0x08, 0x00 },
188 };
189
190 static struct regdata mb86a20s_vber_reset[] = {
191 { 0x53, 0x00 }, /* VBER Counter reset */
192 { 0x53, 0x07 },
193 };
194
195 static struct regdata mb86a20s_per_reset[] = {
196 { 0x50, 0xb1 }, /* PER Counter reset */
197 { 0x51, 0x07 },
198 { 0x51, 0x00 },
199 };
200
201 /*
202 * I2C read/write functions and macros
203 */
204
205 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
206 u8 i2c_addr, u8 reg, u8 data)
207 {
208 u8 buf[] = { reg, data };
209 struct i2c_msg msg = {
210 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
211 };
212 int rc;
213
214 rc = i2c_transfer(state->i2c, &msg, 1);
215 if (rc != 1) {
216 dev_err(&state->i2c->dev,
217 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
218 __func__, rc, reg, data);
219 return rc;
220 }
221
222 return 0;
223 }
224
225 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
226 u8 i2c_addr, struct regdata *rd, int size)
227 {
228 int i, rc;
229
230 for (i = 0; i < size; i++) {
231 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
232 rd[i].data);
233 if (rc < 0)
234 return rc;
235 }
236 return 0;
237 }
238
239 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
240 u8 i2c_addr, u8 reg)
241 {
242 u8 val;
243 int rc;
244 struct i2c_msg msg[] = {
245 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
246 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
247 };
248
249 rc = i2c_transfer(state->i2c, msg, 2);
250
251 if (rc != 2) {
252 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
253 __func__, reg, rc);
254 return (rc < 0) ? rc : -EIO;
255 }
256
257 return val;
258 }
259
260 #define mb86a20s_readreg(state, reg) \
261 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
262 #define mb86a20s_writereg(state, reg, val) \
263 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
264 #define mb86a20s_writeregdata(state, regdata) \
265 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
266 regdata, ARRAY_SIZE(regdata))
267
268 /*
269 * Ancillary internal routines (likely compiled inlined)
270 *
271 * The functions below assume that gateway lock has already obtained
272 */
273
274 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
275 {
276 struct mb86a20s_state *state = fe->demodulator_priv;
277 int val;
278
279 *status = 0;
280
281 val = mb86a20s_readreg(state, 0x0a) & 0xf;
282 if (val < 0)
283 return val;
284
285 if (val >= 2)
286 *status |= FE_HAS_SIGNAL;
287
288 if (val >= 4)
289 *status |= FE_HAS_CARRIER;
290
291 if (val >= 5)
292 *status |= FE_HAS_VITERBI;
293
294 if (val >= 7)
295 *status |= FE_HAS_SYNC;
296
297 if (val >= 8) /* Maybe 9? */
298 *status |= FE_HAS_LOCK;
299
300 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
301 __func__, *status, val);
302
303 return 0;
304 }
305
306 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
307 {
308 struct mb86a20s_state *state = fe->demodulator_priv;
309 int rc;
310 unsigned rf_max, rf_min, rf;
311
312 /* Does a binary search to get RF strength */
313 rf_max = 0xfff;
314 rf_min = 0;
315 do {
316 rf = (rf_max + rf_min) / 2;
317 rc = mb86a20s_writereg(state, 0x04, 0x1f);
318 if (rc < 0)
319 return rc;
320 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
321 if (rc < 0)
322 return rc;
323 rc = mb86a20s_writereg(state, 0x04, 0x20);
324 if (rc < 0)
325 return rc;
326 rc = mb86a20s_writereg(state, 0x04, rf);
327 if (rc < 0)
328 return rc;
329
330 rc = mb86a20s_readreg(state, 0x02);
331 if (rc < 0)
332 return rc;
333 if (rc & 0x08)
334 rf_min = (rf_max + rf_min) / 2;
335 else
336 rf_max = (rf_max + rf_min) / 2;
337 if (rf_max - rf_min < 4) {
338 rf = (rf_max + rf_min) / 2;
339
340 /* Rescale it from 2^12 (4096) to 2^16 */
341 rf <<= (16 - 12);
342 dev_dbg(&state->i2c->dev,
343 "%s: signal strength = %d (%d < RF=%d < %d)\n",
344 __func__, rf, rf_min, rf >> 4, rf_max);
345 return rf;
346 }
347 } while (1);
348
349 return 0;
350 }
351
352 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
353 unsigned layer)
354 {
355 int rc;
356 static unsigned char reg[] = {
357 [0] = 0x86, /* Layer A */
358 [1] = 0x8a, /* Layer B */
359 [2] = 0x8e, /* Layer C */
360 };
361
362 if (layer >= ARRAY_SIZE(reg))
363 return -EINVAL;
364 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
365 if (rc < 0)
366 return rc;
367 rc = mb86a20s_readreg(state, 0x6e);
368 if (rc < 0)
369 return rc;
370 switch ((rc >> 4) & 0x07) {
371 case 0:
372 return DQPSK;
373 case 1:
374 return QPSK;
375 case 2:
376 return QAM_16;
377 case 3:
378 return QAM_64;
379 default:
380 return QAM_AUTO;
381 }
382 }
383
384 static int mb86a20s_get_fec(struct mb86a20s_state *state,
385 unsigned layer)
386 {
387 int rc;
388
389 static unsigned char reg[] = {
390 [0] = 0x87, /* Layer A */
391 [1] = 0x8b, /* Layer B */
392 [2] = 0x8f, /* Layer C */
393 };
394
395 if (layer >= ARRAY_SIZE(reg))
396 return -EINVAL;
397 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
398 if (rc < 0)
399 return rc;
400 rc = mb86a20s_readreg(state, 0x6e);
401 if (rc < 0)
402 return rc;
403 switch ((rc >> 4) & 0x07) {
404 case 0:
405 return FEC_1_2;
406 case 1:
407 return FEC_2_3;
408 case 2:
409 return FEC_3_4;
410 case 3:
411 return FEC_5_6;
412 case 4:
413 return FEC_7_8;
414 default:
415 return FEC_AUTO;
416 }
417 }
418
419 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
420 unsigned layer)
421 {
422 int rc;
423
424 static unsigned char reg[] = {
425 [0] = 0x88, /* Layer A */
426 [1] = 0x8c, /* Layer B */
427 [2] = 0x90, /* Layer C */
428 };
429
430 if (layer >= ARRAY_SIZE(reg))
431 return -EINVAL;
432 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
433 if (rc < 0)
434 return rc;
435 rc = mb86a20s_readreg(state, 0x6e);
436 if (rc < 0)
437 return rc;
438
439 switch ((rc >> 4) & 0x07) {
440 case 1:
441 return GUARD_INTERVAL_1_4;
442 case 2:
443 return GUARD_INTERVAL_1_8;
444 case 3:
445 return GUARD_INTERVAL_1_16;
446 case 4:
447 return GUARD_INTERVAL_1_32;
448
449 default:
450 case 0:
451 return GUARD_INTERVAL_AUTO;
452 }
453 }
454
455 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
456 unsigned layer)
457 {
458 int rc, count;
459 static unsigned char reg[] = {
460 [0] = 0x89, /* Layer A */
461 [1] = 0x8d, /* Layer B */
462 [2] = 0x91, /* Layer C */
463 };
464
465 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
466
467 if (layer >= ARRAY_SIZE(reg))
468 return -EINVAL;
469
470 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
471 if (rc < 0)
472 return rc;
473 rc = mb86a20s_readreg(state, 0x6e);
474 if (rc < 0)
475 return rc;
476 count = (rc >> 4) & 0x0f;
477
478 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
479
480 return count;
481 }
482
483 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
484 {
485 struct mb86a20s_state *state = fe->demodulator_priv;
486 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
487
488 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
489
490 /* Fixed parameters */
491 c->delivery_system = SYS_ISDBT;
492 c->bandwidth_hz = 6000000;
493
494 /* Initialize values that will be later autodetected */
495 c->isdbt_layer_enabled = 0;
496 c->transmission_mode = TRANSMISSION_MODE_AUTO;
497 c->guard_interval = GUARD_INTERVAL_AUTO;
498 c->isdbt_sb_mode = 0;
499 c->isdbt_sb_segment_count = 0;
500 }
501
502 /*
503 * Estimates the bit rate using the per-segment bit rate given by
504 * ABNT/NBR 15601 spec (table 4).
505 */
506 static u32 isdbt_rate[3][5][4] = {
507 { /* DQPSK/QPSK */
508 { 280850, 312060, 330420, 340430 }, /* 1/2 */
509 { 374470, 416080, 440560, 453910 }, /* 2/3 */
510 { 421280, 468090, 495630, 510650 }, /* 3/4 */
511 { 468090, 520100, 550700, 567390 }, /* 5/6 */
512 { 491500, 546110, 578230, 595760 }, /* 7/8 */
513 }, { /* QAM16 */
514 { 561710, 624130, 660840, 680870 }, /* 1/2 */
515 { 748950, 832170, 881120, 907820 }, /* 2/3 */
516 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
517 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
518 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
519 }, { /* QAM64 */
520 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
521 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
522 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
523 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
524 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
525 }
526 };
527
528 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
529 u32 modulation, u32 fec, u32 interleaving,
530 u32 segment)
531 {
532 struct mb86a20s_state *state = fe->demodulator_priv;
533 u32 rate;
534 int m, f, i;
535
536 /*
537 * If modulation/fec/interleaving is not detected, the default is
538 * to consider the lowest bit rate, to avoid taking too long time
539 * to get BER.
540 */
541 switch (modulation) {
542 case DQPSK:
543 case QPSK:
544 default:
545 m = 0;
546 break;
547 case QAM_16:
548 m = 1;
549 break;
550 case QAM_64:
551 m = 2;
552 break;
553 }
554
555 switch (fec) {
556 default:
557 case FEC_1_2:
558 case FEC_AUTO:
559 f = 0;
560 break;
561 case FEC_2_3:
562 f = 1;
563 break;
564 case FEC_3_4:
565 f = 2;
566 break;
567 case FEC_5_6:
568 f = 3;
569 break;
570 case FEC_7_8:
571 f = 4;
572 break;
573 }
574
575 switch (interleaving) {
576 default:
577 case GUARD_INTERVAL_1_4:
578 i = 0;
579 break;
580 case GUARD_INTERVAL_1_8:
581 i = 1;
582 break;
583 case GUARD_INTERVAL_1_16:
584 i = 2;
585 break;
586 case GUARD_INTERVAL_1_32:
587 i = 3;
588 break;
589 }
590
591 /* Samples BER at BER_SAMPLING_RATE seconds */
592 rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE;
593
594 /* Avoids sampling too quickly or to overflow the register */
595 if (rate < 256)
596 rate = 256;
597 else if (rate > (1 << 24) - 1)
598 rate = (1 << 24) - 1;
599
600 dev_dbg(&state->i2c->dev,
601 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
602 __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000,
603 rate, rate);
604
605 state->estimated_rate[i] = rate;
606 }
607
608
609 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
610 {
611 struct mb86a20s_state *state = fe->demodulator_priv;
612 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
613 int i, rc;
614
615 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
616
617 /* Reset frontend cache to default values */
618 mb86a20s_reset_frontend_cache(fe);
619
620 /* Check for partial reception */
621 rc = mb86a20s_writereg(state, 0x6d, 0x85);
622 if (rc < 0)
623 return rc;
624 rc = mb86a20s_readreg(state, 0x6e);
625 if (rc < 0)
626 return rc;
627 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
628
629 /* Get per-layer data */
630
631 for (i = 0; i < 3; i++) {
632 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
633 __func__, 'A' + i);
634
635 rc = mb86a20s_get_segment_count(state, i);
636 if (rc < 0)
637 goto noperlayer_error;
638 if (rc >= 0 && rc < 14) {
639 c->layer[i].segment_count = rc;
640 } else {
641 c->layer[i].segment_count = 0;
642 state->estimated_rate[i] = 0;
643 continue;
644 }
645 c->isdbt_layer_enabled |= 1 << i;
646 rc = mb86a20s_get_modulation(state, i);
647 if (rc < 0)
648 goto noperlayer_error;
649 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
650 __func__, rc);
651 c->layer[i].modulation = rc;
652 rc = mb86a20s_get_fec(state, i);
653 if (rc < 0)
654 goto noperlayer_error;
655 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
656 __func__, rc);
657 c->layer[i].fec = rc;
658 rc = mb86a20s_get_interleaving(state, i);
659 if (rc < 0)
660 goto noperlayer_error;
661 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
662 __func__, rc);
663 c->layer[i].interleaving = rc;
664 mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation,
665 c->layer[i].fec,
666 c->layer[i].interleaving,
667 c->layer[i].segment_count);
668 }
669
670 rc = mb86a20s_writereg(state, 0x6d, 0x84);
671 if (rc < 0)
672 return rc;
673 if ((rc & 0x60) == 0x20) {
674 c->isdbt_sb_mode = 1;
675 /* At least, one segment should exist */
676 if (!c->isdbt_sb_segment_count)
677 c->isdbt_sb_segment_count = 1;
678 }
679
680 /* Get transmission mode and guard interval */
681 rc = mb86a20s_readreg(state, 0x07);
682 if (rc < 0)
683 return rc;
684 if ((rc & 0x60) == 0x20) {
685 switch (rc & 0x0c >> 2) {
686 case 0:
687 c->transmission_mode = TRANSMISSION_MODE_2K;
688 break;
689 case 1:
690 c->transmission_mode = TRANSMISSION_MODE_4K;
691 break;
692 case 2:
693 c->transmission_mode = TRANSMISSION_MODE_8K;
694 break;
695 }
696 }
697 if (!(rc & 0x10)) {
698 switch (rc & 0x3) {
699 case 0:
700 c->guard_interval = GUARD_INTERVAL_1_4;
701 break;
702 case 1:
703 c->guard_interval = GUARD_INTERVAL_1_8;
704 break;
705 case 2:
706 c->guard_interval = GUARD_INTERVAL_1_16;
707 break;
708 }
709 }
710 return 0;
711
712 noperlayer_error:
713
714 /* per-layer info is incomplete; discard all per-layer */
715 c->isdbt_layer_enabled = 0;
716
717 return rc;
718 }
719
720 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
721 {
722 struct mb86a20s_state *state = fe->demodulator_priv;
723 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
724 int rc, val;
725
726 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
727
728 /* Reset the counters, if the channel changed */
729 if (state->last_frequency != c->frequency) {
730 memset(&c->strength, 0, sizeof(c->strength));
731 memset(&c->cnr, 0, sizeof(c->cnr));
732 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
733 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
734 memset(&c->block_error, 0, sizeof(c->block_error));
735 memset(&c->block_count, 0, sizeof(c->block_count));
736
737 state->last_frequency = c->frequency;
738 }
739
740 /* Clear status for most stats */
741
742 /* BER counter reset */
743 rc = mb86a20s_writeregdata(state, mb86a20s_vber_reset);
744 if (rc < 0)
745 goto err;
746
747 /* MER, PER counter reset */
748 rc = mb86a20s_writeregdata(state, mb86a20s_per_reset);
749 if (rc < 0)
750 goto err;
751
752 /* CNR counter reset */
753 rc = mb86a20s_readreg(state, 0x45);
754 if (rc < 0)
755 goto err;
756 val = rc;
757 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
758 if (rc < 0)
759 goto err;
760 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
761 if (rc < 0)
762 goto err;
763
764 /* MER counter reset */
765 rc = mb86a20s_writereg(state, 0x50, 0x50);
766 if (rc < 0)
767 goto err;
768 rc = mb86a20s_readreg(state, 0x51);
769 if (rc < 0)
770 goto err;
771 val = rc;
772 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
773 if (rc < 0)
774 goto err;
775 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
776 if (rc < 0)
777 goto err;
778
779 goto ok;
780 err:
781 dev_err(&state->i2c->dev,
782 "%s: Can't reset FE statistics (error %d).\n",
783 __func__, rc);
784 ok:
785 return rc;
786 }
787
788 static int mb86a20s_get_ber_before_vterbi(struct dvb_frontend *fe,
789 unsigned layer,
790 u32 *error, u32 *count)
791 {
792 struct mb86a20s_state *state = fe->demodulator_priv;
793 int rc;
794
795 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
796
797 if (layer >= 3)
798 return -EINVAL;
799
800 /* Check if the BER measures are already available */
801 rc = mb86a20s_readreg(state, 0x54);
802 if (rc < 0)
803 return rc;
804
805 /* Check if data is available for that layer */
806 if (!(rc & (1 << layer))) {
807 dev_dbg(&state->i2c->dev,
808 "%s: BER for layer %c is not available yet.\n",
809 __func__, 'A' + layer);
810 return -EBUSY;
811 }
812
813 /* Read Bit Error Count */
814 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
815 if (rc < 0)
816 return rc;
817 *error = rc << 16;
818 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
819 if (rc < 0)
820 return rc;
821 *error |= rc << 8;
822 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
823 if (rc < 0)
824 return rc;
825 *error |= rc;
826
827 dev_dbg(&state->i2c->dev,
828 "%s: bit error before Viterbi for layer %c: %d.\n",
829 __func__, 'A' + layer, *error);
830
831 /* Read Bit Count */
832 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
833 if (rc < 0)
834 return rc;
835 rc = mb86a20s_readreg(state, 0x51);
836 if (rc < 0)
837 return rc;
838 *count = rc << 16;
839 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
840 if (rc < 0)
841 return rc;
842 rc = mb86a20s_readreg(state, 0x51);
843 if (rc < 0)
844 return rc;
845 *count |= rc << 8;
846 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
847 if (rc < 0)
848 return rc;
849 rc = mb86a20s_readreg(state, 0x51);
850 if (rc < 0)
851 return rc;
852 *count |= rc;
853
854 dev_dbg(&state->i2c->dev,
855 "%s: bit count before Viterbi for layer %c: %d.\n",
856 __func__, 'A' + layer, *count);
857
858
859 /*
860 * As we get TMCC data from the frontend, we can better estimate the
861 * BER bit counters, in order to do the BER measure during a longer
862 * time. Use those data, if available, to update the bit count
863 * measure.
864 */
865
866 if (state->estimated_rate[layer]
867 && state->estimated_rate[layer] != *count) {
868 dev_dbg(&state->i2c->dev,
869 "%s: updating layer %c counter to %d.\n",
870 __func__, 'A' + layer, state->estimated_rate[layer]);
871 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
872 if (rc < 0)
873 return rc;
874 rc = mb86a20s_writereg(state, 0x51,
875 state->estimated_rate[layer] >> 16);
876 if (rc < 0)
877 return rc;
878 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
879 if (rc < 0)
880 return rc;
881 rc = mb86a20s_writereg(state, 0x51,
882 state->estimated_rate[layer] >> 8);
883 if (rc < 0)
884 return rc;
885 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
886 if (rc < 0)
887 return rc;
888 rc = mb86a20s_writereg(state, 0x51,
889 state->estimated_rate[layer]);
890 if (rc < 0)
891 return rc;
892 }
893
894
895 /* Reset counter to collect new data */
896 rc = mb86a20s_writereg(state, 0x53, 0x07 & ~(1 << layer));
897 if (rc < 0)
898 return rc;
899 rc = mb86a20s_writereg(state, 0x53, 0x07);
900
901 return 0;
902 }
903
904 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
905 unsigned layer,
906 u32 *error, u32 *count)
907 {
908 struct mb86a20s_state *state = fe->demodulator_priv;
909 int rc;
910 u32 collect_rate;
911 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
912
913 if (layer >= 3)
914 return -EINVAL;
915
916 /* Check if the PER measures are already available */
917 rc = mb86a20s_writereg(state, 0x50, 0xb8);
918 if (rc < 0)
919 return rc;
920 rc = mb86a20s_readreg(state, 0x51);
921 if (rc < 0)
922 return rc;
923
924 /* Check if data is available for that layer */
925
926 if (!(rc & (1 << layer))) {
927 dev_dbg(&state->i2c->dev,
928 "%s: block counts for layer %c aren't available yet.\n",
929 __func__, 'A' + layer);
930 return -EBUSY;
931 }
932
933 /* Read Packet error Count */
934 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
935 if (rc < 0)
936 return rc;
937 rc = mb86a20s_readreg(state, 0x51);
938 if (rc < 0)
939 return rc;
940 *error = rc << 8;
941 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
942 if (rc < 0)
943 return rc;
944 rc = mb86a20s_readreg(state, 0x51);
945 if (rc < 0)
946 return rc;
947 *error |= rc;
948 dev_err(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
949 __func__, 'A' + layer, *error);
950
951 /* Read Bit Count */
952 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
953 if (rc < 0)
954 return rc;
955 rc = mb86a20s_readreg(state, 0x51);
956 if (rc < 0)
957 return rc;
958 *count = rc << 8;
959 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
960 if (rc < 0)
961 return rc;
962 rc = mb86a20s_readreg(state, 0x51);
963 if (rc < 0)
964 return rc;
965 *count |= rc;
966
967 dev_dbg(&state->i2c->dev,
968 "%s: block count for layer %c: %d.\n",
969 __func__, 'A' + layer, *count);
970
971 /*
972 * As we get TMCC data from the frontend, we can better estimate the
973 * BER bit counters, in order to do the BER measure during a longer
974 * time. Use those data, if available, to update the bit count
975 * measure.
976 */
977
978 if (!state->estimated_rate[layer])
979 goto reset_measurement;
980
981 collect_rate = state->estimated_rate[layer] / 204 / 8;
982
983 if (collect_rate < 32)
984 collect_rate = 32;
985 if (collect_rate > 65535)
986 collect_rate = 65535;
987
988 if (collect_rate != *count) {
989 dev_dbg(&state->i2c->dev,
990 "%s: updating PER counter on layer %c to %d.\n",
991 __func__, 'A' + layer, collect_rate);
992 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
993 if (rc < 0)
994 return rc;
995 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
996 if (rc < 0)
997 return rc;
998 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
999 if (rc < 0)
1000 return rc;
1001 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1002 if (rc < 0)
1003 return rc;
1004 }
1005
1006 reset_measurement:
1007 /* Reset counter to collect new data */
1008 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1009 if (rc < 0)
1010 return rc;
1011 rc = mb86a20s_writereg(state, 0x51, (1 << layer));
1012 if (rc < 0)
1013 return rc;
1014 rc = mb86a20s_writereg(state, 0x51, 0x00);
1015 if (rc < 0)
1016 return rc;
1017
1018 return 0;
1019 }
1020
1021 struct linear_segments {
1022 unsigned x, y;
1023 };
1024
1025 /*
1026 * All tables below return a dB/1000 measurement
1027 */
1028
1029 static struct linear_segments cnr_to_db_table[] = {
1030 { 19648, 0},
1031 { 18187, 1000},
1032 { 16534, 2000},
1033 { 14823, 3000},
1034 { 13161, 4000},
1035 { 11622, 5000},
1036 { 10279, 6000},
1037 { 9089, 7000},
1038 { 8042, 8000},
1039 { 7137, 9000},
1040 { 6342, 10000},
1041 { 5641, 11000},
1042 { 5030, 12000},
1043 { 4474, 13000},
1044 { 3988, 14000},
1045 { 3556, 15000},
1046 { 3180, 16000},
1047 { 2841, 17000},
1048 { 2541, 18000},
1049 { 2276, 19000},
1050 { 2038, 20000},
1051 { 1800, 21000},
1052 { 1625, 22000},
1053 { 1462, 23000},
1054 { 1324, 24000},
1055 { 1175, 25000},
1056 { 1063, 26000},
1057 { 980, 27000},
1058 { 907, 28000},
1059 { 840, 29000},
1060 { 788, 30000},
1061 };
1062
1063 static struct linear_segments cnr_64qam_table[] = {
1064 { 3922688, 0},
1065 { 3920384, 1000},
1066 { 3902720, 2000},
1067 { 3894784, 3000},
1068 { 3882496, 4000},
1069 { 3872768, 5000},
1070 { 3858944, 6000},
1071 { 3851520, 7000},
1072 { 3838976, 8000},
1073 { 3829248, 9000},
1074 { 3818240, 10000},
1075 { 3806976, 11000},
1076 { 3791872, 12000},
1077 { 3767040, 13000},
1078 { 3720960, 14000},
1079 { 3637504, 15000},
1080 { 3498496, 16000},
1081 { 3296000, 17000},
1082 { 3031040, 18000},
1083 { 2715392, 19000},
1084 { 2362624, 20000},
1085 { 1963264, 21000},
1086 { 1649664, 22000},
1087 { 1366784, 23000},
1088 { 1120768, 24000},
1089 { 890880, 25000},
1090 { 723456, 26000},
1091 { 612096, 27000},
1092 { 518912, 28000},
1093 { 448256, 29000},
1094 { 388864, 30000},
1095 };
1096
1097 static struct linear_segments cnr_16qam_table[] = {
1098 { 5314816, 0},
1099 { 5219072, 1000},
1100 { 5118720, 2000},
1101 { 4998912, 3000},
1102 { 4875520, 4000},
1103 { 4736000, 5000},
1104 { 4604160, 6000},
1105 { 4458752, 7000},
1106 { 4300288, 8000},
1107 { 4092928, 9000},
1108 { 3836160, 10000},
1109 { 3521024, 11000},
1110 { 3155968, 12000},
1111 { 2756864, 13000},
1112 { 2347008, 14000},
1113 { 1955072, 15000},
1114 { 1593600, 16000},
1115 { 1297920, 17000},
1116 { 1043968, 18000},
1117 { 839680, 19000},
1118 { 672256, 20000},
1119 { 523008, 21000},
1120 { 424704, 22000},
1121 { 345088, 23000},
1122 { 280064, 24000},
1123 { 221440, 25000},
1124 { 179712, 26000},
1125 { 151040, 27000},
1126 { 128512, 28000},
1127 { 110080, 29000},
1128 { 95744, 30000},
1129 };
1130
1131 struct linear_segments cnr_qpsk_table[] = {
1132 { 2834176, 0},
1133 { 2683648, 1000},
1134 { 2536960, 2000},
1135 { 2391808, 3000},
1136 { 2133248, 4000},
1137 { 1906176, 5000},
1138 { 1666560, 6000},
1139 { 1422080, 7000},
1140 { 1189632, 8000},
1141 { 976384, 9000},
1142 { 790272, 10000},
1143 { 633344, 11000},
1144 { 505600, 12000},
1145 { 402944, 13000},
1146 { 320768, 14000},
1147 { 255488, 15000},
1148 { 204032, 16000},
1149 { 163072, 17000},
1150 { 130304, 18000},
1151 { 105216, 19000},
1152 { 83456, 20000},
1153 { 65024, 21000},
1154 { 52480, 22000},
1155 { 42752, 23000},
1156 { 34560, 24000},
1157 { 27136, 25000},
1158 { 22016, 26000},
1159 { 18432, 27000},
1160 { 15616, 28000},
1161 { 13312, 29000},
1162 { 11520, 30000},
1163 };
1164
1165 static u32 interpolate_value(u32 value, struct linear_segments *segments,
1166 unsigned len)
1167 {
1168 u64 tmp64;
1169 u32 dx, dy;
1170 int i, ret;
1171
1172 if (value >= segments[0].x)
1173 return segments[0].y;
1174 if (value < segments[len-1].x)
1175 return segments[len-1].y;
1176
1177 for (i = 1; i < len - 1; i++) {
1178 /* If value is identical, no need to interpolate */
1179 if (value == segments[i].x)
1180 return segments[i].y;
1181 if (value > segments[i].x)
1182 break;
1183 }
1184
1185 /* Linear interpolation between the two (x,y) points */
1186 dy = segments[i].y - segments[i - 1].y;
1187 dx = segments[i - 1].x - segments[i].x;
1188 tmp64 = value - segments[i].x;
1189 tmp64 *= dy;
1190 do_div(tmp64, dx);
1191 ret = segments[i].y - tmp64;
1192
1193 return ret;
1194 }
1195
1196 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1197 {
1198 struct mb86a20s_state *state = fe->demodulator_priv;
1199 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1200 u32 cnr_linear, cnr;
1201 int rc, val;
1202
1203 /* Check if CNR is available */
1204 rc = mb86a20s_readreg(state, 0x45);
1205 if (rc < 0)
1206 return rc;
1207
1208 if (!(rc & 0x40)) {
1209 dev_info(&state->i2c->dev, "%s: CNR is not available yet.\n",
1210 __func__);
1211 return -EBUSY;
1212 }
1213 val = rc;
1214
1215 rc = mb86a20s_readreg(state, 0x46);
1216 if (rc < 0)
1217 return rc;
1218 cnr_linear = rc << 8;
1219
1220 rc = mb86a20s_readreg(state, 0x46);
1221 if (rc < 0)
1222 return rc;
1223 cnr_linear |= rc;
1224
1225 cnr = interpolate_value(cnr_linear,
1226 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1227
1228 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1229 c->cnr.stat[0].svalue = cnr;
1230
1231 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1232 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1233
1234 /* CNR counter reset */
1235 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1236 if (rc < 0)
1237 return rc;
1238 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1239
1240 return rc;
1241 }
1242
1243 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1244 {
1245 struct mb86a20s_state *state = fe->demodulator_priv;
1246 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1247 u32 mer, cnr;
1248 int rc, val, i;
1249 struct linear_segments *segs;
1250 unsigned segs_len;
1251
1252 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1253
1254 /* Check if the measures are already available */
1255 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1256 if (rc < 0)
1257 return rc;
1258 rc = mb86a20s_readreg(state, 0x51);
1259 if (rc < 0)
1260 return rc;
1261
1262 /* Check if data is available */
1263 if (!(rc & 0x01)) {
1264 dev_info(&state->i2c->dev,
1265 "%s: MER measures aren't available yet.\n", __func__);
1266 return -EBUSY;
1267 }
1268
1269 /* Read all layers */
1270 for (i = 0; i < 3; i++) {
1271 if (!(c->isdbt_layer_enabled & (1 << i))) {
1272 c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1273 continue;
1274 }
1275
1276 rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3);
1277 if (rc < 0)
1278 return rc;
1279 rc = mb86a20s_readreg(state, 0x51);
1280 if (rc < 0)
1281 return rc;
1282 mer = rc << 16;
1283 rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3);
1284 if (rc < 0)
1285 return rc;
1286 rc = mb86a20s_readreg(state, 0x51);
1287 if (rc < 0)
1288 return rc;
1289 mer |= rc << 8;
1290 rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3);
1291 if (rc < 0)
1292 return rc;
1293 rc = mb86a20s_readreg(state, 0x51);
1294 if (rc < 0)
1295 return rc;
1296 mer |= rc;
1297
1298 switch (c->layer[i].modulation) {
1299 case DQPSK:
1300 case QPSK:
1301 segs = cnr_qpsk_table;
1302 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1303 break;
1304 case QAM_16:
1305 segs = cnr_16qam_table;
1306 segs_len = ARRAY_SIZE(cnr_16qam_table);
1307 break;
1308 default:
1309 case QAM_64:
1310 segs = cnr_64qam_table;
1311 segs_len = ARRAY_SIZE(cnr_64qam_table);
1312 break;
1313 }
1314 cnr = interpolate_value(mer, segs, segs_len);
1315
1316 c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL;
1317 c->cnr.stat[1 + i].svalue = cnr;
1318
1319 dev_dbg(&state->i2c->dev,
1320 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1321 __func__, 'A' + i, cnr / 1000, cnr % 1000, mer);
1322
1323 }
1324
1325 /* Start a new MER measurement */
1326 /* MER counter reset */
1327 rc = mb86a20s_writereg(state, 0x50, 0x50);
1328 if (rc < 0)
1329 return rc;
1330 rc = mb86a20s_readreg(state, 0x51);
1331 if (rc < 0)
1332 return rc;
1333 val = rc;
1334
1335 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1336 if (rc < 0)
1337 return rc;
1338 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1339 if (rc < 0)
1340 return rc;
1341
1342 return 0;
1343 }
1344
1345 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1346 {
1347 struct mb86a20s_state *state = fe->demodulator_priv;
1348 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1349 int i;
1350
1351 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1352
1353 /* Fill the length of each status counter */
1354
1355 /* Only global stats */
1356 c->strength.len = 1;
1357
1358 /* Per-layer stats - 3 layers + global */
1359 c->cnr.len = 4;
1360 c->pre_bit_error.len = 4;
1361 c->pre_bit_count.len = 4;
1362 c->block_error.len = 4;
1363 c->block_count.len = 4;
1364
1365 /* Signal is always available */
1366 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1367 c->strength.stat[0].uvalue = 0;
1368
1369 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1370 for (i = 0; i < 4; i++) {
1371 c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1372 c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1373 c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1374 c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1375 c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1376 }
1377 }
1378
1379 static int mb86a20s_get_stats(struct dvb_frontend *fe)
1380 {
1381 struct mb86a20s_state *state = fe->demodulator_priv;
1382 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1383 int rc = 0, i;
1384 u32 bit_error = 0, bit_count = 0;
1385 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1386 u32 block_error = 0, block_count = 0;
1387 u32 t_block_error = 0, t_block_count = 0;
1388 int active_layers = 0, ber_layers = 0, per_layers = 0;
1389
1390 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1391
1392 mb86a20s_get_main_CNR(fe);
1393
1394 /* Get per-layer stats */
1395 mb86a20s_get_blk_error_layer_CNR(fe);
1396
1397 for (i = 0; i < 3; i++) {
1398 if (c->isdbt_layer_enabled & (1 << i)) {
1399 /* Layer is active and has rc segments */
1400 active_layers++;
1401
1402 /* Read per-layer BER */
1403 /* Handle BER before vterbi */
1404 rc = mb86a20s_get_ber_before_vterbi(fe, i,
1405 &bit_error,
1406 &bit_count);
1407 if (rc >= 0) {
1408 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1409 c->pre_bit_error.stat[1 + i].uvalue += bit_error;
1410 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1411 c->pre_bit_count.stat[1 + i].uvalue += bit_count;
1412 } else if (rc != -EBUSY) {
1413 /*
1414 * If an I/O error happened,
1415 * measures are now unavailable
1416 */
1417 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1418 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1419 dev_err(&state->i2c->dev,
1420 "%s: Can't get BER for layer %c (error %d).\n",
1421 __func__, 'A' + i, rc);
1422 }
1423
1424 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1425 ber_layers++;
1426
1427 /* Handle Block errors for PER/UCB reports */
1428 rc = mb86a20s_get_blk_error(fe, i,
1429 &block_error,
1430 &block_count);
1431 if (rc >= 0) {
1432 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1433 c->block_error.stat[1 + i].uvalue += block_error;
1434 c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1435 c->block_count.stat[1 + i].uvalue += block_count;
1436 } else if (rc != -EBUSY) {
1437 /*
1438 * If an I/O error happened,
1439 * measures are now unavailable
1440 */
1441 c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1442 c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1443 dev_err(&state->i2c->dev,
1444 "%s: Can't get PER for layer %c (error %d).\n",
1445 __func__, 'A' + i, rc);
1446
1447 }
1448
1449 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1450 per_layers++;
1451
1452 /* Update total BER */
1453 t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue;
1454 t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue;
1455
1456 /* Update total PER */
1457 t_block_error += c->block_error.stat[1 + i].uvalue;
1458 t_block_count += c->block_count.stat[1 + i].uvalue;
1459 }
1460 }
1461
1462 /*
1463 * Start showing global count if at least one error count is
1464 * available.
1465 */
1466 if (ber_layers) {
1467 /*
1468 * At least one per-layer BER measure was read. We can now
1469 * calculate the total BER
1470 *
1471 * Total Bit Error/Count is calculated as the sum of the
1472 * bit errors on all active layers.
1473 */
1474 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1475 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1476 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1477 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1478 }
1479
1480 if (per_layers) {
1481 /*
1482 * At least one per-layer UCB measure was read. We can now
1483 * calculate the total UCB
1484 *
1485 * Total block Error/Count is calculated as the sum of the
1486 * block errors on all active layers.
1487 */
1488 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1489 c->block_error.stat[0].uvalue = t_block_error;
1490 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1491 c->block_count.stat[0].uvalue = t_block_count;
1492 }
1493
1494 return rc;
1495 }
1496
1497 /*
1498 * The functions below are called via DVB callbacks, so they need to
1499 * properly use the I2C gate control
1500 */
1501
1502 static int mb86a20s_initfe(struct dvb_frontend *fe)
1503 {
1504 struct mb86a20s_state *state = fe->demodulator_priv;
1505 int rc;
1506 u8 regD5 = 1;
1507
1508 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1509
1510 if (fe->ops.i2c_gate_ctrl)
1511 fe->ops.i2c_gate_ctrl(fe, 0);
1512
1513 /* Initialize the frontend */
1514 rc = mb86a20s_writeregdata(state, mb86a20s_init);
1515 if (rc < 0)
1516 goto err;
1517
1518 if (!state->config->is_serial) {
1519 regD5 &= ~1;
1520
1521 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1522 if (rc < 0)
1523 goto err;
1524 rc = mb86a20s_writereg(state, 0x51, regD5);
1525 if (rc < 0)
1526 goto err;
1527 }
1528
1529 err:
1530 if (fe->ops.i2c_gate_ctrl)
1531 fe->ops.i2c_gate_ctrl(fe, 1);
1532
1533 if (rc < 0) {
1534 state->need_init = true;
1535 dev_info(&state->i2c->dev,
1536 "mb86a20s: Init failed. Will try again later\n");
1537 } else {
1538 state->need_init = false;
1539 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1540 }
1541 return rc;
1542 }
1543
1544 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1545 {
1546 struct mb86a20s_state *state = fe->demodulator_priv;
1547 int rc;
1548 #if 0
1549 /*
1550 * FIXME: Properly implement the set frontend properties
1551 */
1552 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1553 #endif
1554 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1555
1556 /*
1557 * Gate should already be opened, but it doesn't hurt to
1558 * double-check
1559 */
1560 if (fe->ops.i2c_gate_ctrl)
1561 fe->ops.i2c_gate_ctrl(fe, 1);
1562 fe->ops.tuner_ops.set_params(fe);
1563
1564 /*
1565 * Make it more reliable: if, for some reason, the initial
1566 * device initialization doesn't happen, initialize it when
1567 * a SBTVD parameters are adjusted.
1568 *
1569 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1570 * the agc callback logic is not called during DVB attach time,
1571 * causing mb86a20s to not be initialized with Kworld SBTVD.
1572 * So, this hack is needed, in order to make Kworld SBTVD to work.
1573 */
1574 if (state->need_init)
1575 mb86a20s_initfe(fe);
1576
1577 if (fe->ops.i2c_gate_ctrl)
1578 fe->ops.i2c_gate_ctrl(fe, 0);
1579
1580 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1581 mb86a20s_reset_counters(fe);
1582
1583 if (fe->ops.i2c_gate_ctrl)
1584 fe->ops.i2c_gate_ctrl(fe, 1);
1585
1586 return rc;
1587 }
1588
1589 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1590 fe_status_t *status)
1591 {
1592 struct mb86a20s_state *state = fe->demodulator_priv;
1593 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1594 int rc;
1595
1596 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1597
1598 if (fe->ops.i2c_gate_ctrl)
1599 fe->ops.i2c_gate_ctrl(fe, 0);
1600
1601 /* Get lock */
1602 rc = mb86a20s_read_status(fe, status);
1603 if (!(*status & FE_HAS_LOCK)) {
1604 mb86a20s_stats_not_ready(fe);
1605 mb86a20s_reset_frontend_cache(fe);
1606 }
1607 if (rc < 0) {
1608 dev_err(&state->i2c->dev,
1609 "%s: Can't read frontend lock status\n", __func__);
1610 goto error;
1611 }
1612
1613 /* Get signal strength */
1614 rc = mb86a20s_read_signal_strength(fe);
1615 if (rc < 0) {
1616 dev_err(&state->i2c->dev,
1617 "%s: Can't reset VBER registers.\n", __func__);
1618 mb86a20s_stats_not_ready(fe);
1619 mb86a20s_reset_frontend_cache(fe);
1620
1621 rc = 0; /* Status is OK */
1622 goto error;
1623 }
1624 /* Fill signal strength */
1625 c->strength.stat[0].uvalue = rc;
1626
1627 if (*status & FE_HAS_LOCK) {
1628 /* Get TMCC info*/
1629 rc = mb86a20s_get_frontend(fe);
1630 if (rc < 0) {
1631 dev_err(&state->i2c->dev,
1632 "%s: Can't get FE TMCC data.\n", __func__);
1633 rc = 0; /* Status is OK */
1634 goto error;
1635 }
1636
1637 /* Get statistics */
1638 rc = mb86a20s_get_stats(fe);
1639 if (rc < 0 && rc != -EBUSY) {
1640 dev_err(&state->i2c->dev,
1641 "%s: Can't get FE statistics.\n", __func__);
1642 rc = 0;
1643 goto error;
1644 }
1645 rc = 0; /* Don't return EBUSY to userspace */
1646 }
1647 goto ok;
1648
1649 error:
1650 mb86a20s_stats_not_ready(fe);
1651
1652 ok:
1653 if (fe->ops.i2c_gate_ctrl)
1654 fe->ops.i2c_gate_ctrl(fe, 1);
1655
1656 return rc;
1657 }
1658
1659 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
1660 u16 *strength)
1661 {
1662 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1663
1664
1665 *strength = c->strength.stat[0].uvalue;
1666
1667 return 0;
1668 }
1669
1670 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
1671 {
1672 /*
1673 * get_frontend is now handled together with other stats
1674 * retrival, when read_status() is called, as some statistics
1675 * will depend on the layers detection.
1676 */
1677 return 0;
1678 };
1679
1680 static int mb86a20s_tune(struct dvb_frontend *fe,
1681 bool re_tune,
1682 unsigned int mode_flags,
1683 unsigned int *delay,
1684 fe_status_t *status)
1685 {
1686 struct mb86a20s_state *state = fe->demodulator_priv;
1687 int rc = 0;
1688
1689 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1690
1691 if (re_tune)
1692 rc = mb86a20s_set_frontend(fe);
1693
1694 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1695 mb86a20s_read_status_and_stats(fe, status);
1696
1697 return rc;
1698 }
1699
1700 static void mb86a20s_release(struct dvb_frontend *fe)
1701 {
1702 struct mb86a20s_state *state = fe->demodulator_priv;
1703
1704 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1705
1706 kfree(state);
1707 }
1708
1709 static struct dvb_frontend_ops mb86a20s_ops;
1710
1711 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
1712 struct i2c_adapter *i2c)
1713 {
1714 struct mb86a20s_state *state;
1715 u8 rev;
1716
1717 dev_dbg(&i2c->dev, "%s called.\n", __func__);
1718
1719 /* allocate memory for the internal state */
1720 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
1721 if (state == NULL) {
1722 dev_err(&i2c->dev,
1723 "%s: unable to allocate memory for state\n", __func__);
1724 goto error;
1725 }
1726
1727 /* setup the state */
1728 state->config = config;
1729 state->i2c = i2c;
1730
1731 /* create dvb_frontend */
1732 memcpy(&state->frontend.ops, &mb86a20s_ops,
1733 sizeof(struct dvb_frontend_ops));
1734 state->frontend.demodulator_priv = state;
1735
1736 /* Check if it is a mb86a20s frontend */
1737 rev = mb86a20s_readreg(state, 0);
1738
1739 if (rev == 0x13) {
1740 dev_info(&i2c->dev,
1741 "Detected a Fujitsu mb86a20s frontend\n");
1742 } else {
1743 dev_dbg(&i2c->dev,
1744 "Frontend revision %d is unknown - aborting.\n",
1745 rev);
1746 goto error;
1747 }
1748
1749 return &state->frontend;
1750
1751 error:
1752 kfree(state);
1753 return NULL;
1754 }
1755 EXPORT_SYMBOL(mb86a20s_attach);
1756
1757 static struct dvb_frontend_ops mb86a20s_ops = {
1758 .delsys = { SYS_ISDBT },
1759 /* Use dib8000 values per default */
1760 .info = {
1761 .name = "Fujitsu mb86A20s",
1762 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER |
1763 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1764 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1765 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1766 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
1767 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
1768 /* Actually, those values depend on the used tuner */
1769 .frequency_min = 45000000,
1770 .frequency_max = 864000000,
1771 .frequency_stepsize = 62500,
1772 },
1773
1774 .release = mb86a20s_release,
1775
1776 .init = mb86a20s_initfe,
1777 .set_frontend = mb86a20s_set_frontend,
1778 .get_frontend = mb86a20s_get_frontend_dummy,
1779 .read_status = mb86a20s_read_status_and_stats,
1780 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
1781 .tune = mb86a20s_tune,
1782 };
1783
1784 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
1785 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1786 MODULE_LICENSE("GPL");
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