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[media] mb86a20s: adjust IF based on what's set on the tuner
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / mb86a20s.c
1 /*
2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
3 *
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
19
20 #include "dvb_frontend.h"
21 #include "mb86a20s.h"
22
23 static int debug = 1;
24 module_param(debug, int, 0644);
25 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
26
27 struct mb86a20s_state {
28 struct i2c_adapter *i2c;
29 const struct mb86a20s_config *config;
30 u32 last_frequency;
31
32 struct dvb_frontend frontend;
33
34 u32 if_freq;
35
36 u32 estimated_rate[3];
37
38 bool need_init;
39 };
40
41 struct regdata {
42 u8 reg;
43 u8 data;
44 };
45
46 #define BER_SAMPLING_RATE 1 /* Seconds */
47
48 /*
49 * Initialization sequence: Use whatevere default values that PV SBTVD
50 * does on its initialisation, obtained via USB snoop
51 */
52 static struct regdata mb86a20s_init1[] = {
53 { 0x70, 0x0f },
54 { 0x70, 0xff },
55 { 0x08, 0x01 },
56 { 0x09, 0x3e },
57 { 0x50, 0xd1 }, { 0x51, 0x22 },
58 { 0x39, 0x01 },
59 { 0x71, 0x00 },
60 { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 },
61 };
62
63 static struct regdata mb86a20s_init2[] = {
64 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
65 { 0x3b, 0x21 },
66 { 0x3c, 0x3a },
67 { 0x01, 0x0d },
68 { 0x04, 0x08 }, { 0x05, 0x05 },
69 { 0x04, 0x0e }, { 0x05, 0x00 },
70 { 0x04, 0x0f }, { 0x05, 0x14 },
71 { 0x04, 0x0b }, { 0x05, 0x8c },
72 { 0x04, 0x00 }, { 0x05, 0x00 },
73 { 0x04, 0x01 }, { 0x05, 0x07 },
74 { 0x04, 0x02 }, { 0x05, 0x0f },
75 { 0x04, 0x03 }, { 0x05, 0xa0 },
76 { 0x04, 0x09 }, { 0x05, 0x00 },
77 { 0x04, 0x0a }, { 0x05, 0xff },
78 { 0x04, 0x27 }, { 0x05, 0x64 },
79 { 0x04, 0x28 }, { 0x05, 0x00 },
80 { 0x04, 0x1e }, { 0x05, 0xff },
81 { 0x04, 0x29 }, { 0x05, 0x0a },
82 { 0x04, 0x32 }, { 0x05, 0x0a },
83 { 0x04, 0x14 }, { 0x05, 0x02 },
84 { 0x04, 0x04 }, { 0x05, 0x00 },
85 { 0x04, 0x05 }, { 0x05, 0x22 },
86 { 0x04, 0x06 }, { 0x05, 0x0e },
87 { 0x04, 0x07 }, { 0x05, 0xd8 },
88 { 0x04, 0x12 }, { 0x05, 0x00 },
89 { 0x04, 0x13 }, { 0x05, 0xff },
90 { 0x04, 0x15 }, { 0x05, 0x4e },
91 { 0x04, 0x16 }, { 0x05, 0x20 },
92
93 /*
94 * On this demod, when the bit count reaches the count below,
95 * it collects the bit error count. The bit counters are initialized
96 * to 65535 here. This warrants that all of them will be quickly
97 * calculated when device gets locked. As TMCC is parsed, the values
98 * will be adjusted later in the driver's code.
99 */
100 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
101 { 0x50, 0xa7 }, { 0x51, 0x00 },
102 { 0x50, 0xa8 }, { 0x51, 0xff },
103 { 0x50, 0xa9 }, { 0x51, 0xff },
104 { 0x50, 0xaa }, { 0x51, 0x00 },
105 { 0x50, 0xab }, { 0x51, 0xff },
106 { 0x50, 0xac }, { 0x51, 0xff },
107 { 0x50, 0xad }, { 0x51, 0x00 },
108 { 0x50, 0xae }, { 0x51, 0xff },
109 { 0x50, 0xaf }, { 0x51, 0xff },
110
111 /*
112 * On this demod, post BER counts blocks. When the count reaches the
113 * value below, it collects the block error count. The block counters
114 * are initialized to 127 here. This warrants that all of them will be
115 * quickly calculated when device gets locked. As TMCC is parsed, the
116 * values will be adjusted later in the driver's code.
117 */
118 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
119 { 0x50, 0xdc }, { 0x51, 0x00 },
120 { 0x50, 0xdd }, { 0x51, 0x7f },
121 { 0x50, 0xde }, { 0x51, 0x00 },
122 { 0x50, 0xdf }, { 0x51, 0x7f },
123 { 0x50, 0xe0 }, { 0x51, 0x00 },
124 { 0x50, 0xe1 }, { 0x51, 0x7f },
125
126 /*
127 * On this demod, when the block count reaches the count below,
128 * it collects the block error count. The block counters are initialized
129 * to 127 here. This warrants that all of them will be quickly
130 * calculated when device gets locked. As TMCC is parsed, the values
131 * will be adjusted later in the driver's code.
132 */
133 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
134 { 0x50, 0xb2 }, { 0x51, 0x00 },
135 { 0x50, 0xb3 }, { 0x51, 0x7f },
136 { 0x50, 0xb4 }, { 0x51, 0x00 },
137 { 0x50, 0xb5 }, { 0x51, 0x7f },
138 { 0x50, 0xb6 }, { 0x51, 0x00 },
139 { 0x50, 0xb7 }, { 0x51, 0x7f },
140
141 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
142 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
143 { 0x45, 0x04 }, /* CN symbol 4 */
144 { 0x48, 0x04 }, /* CN manual mode */
145
146 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
147 { 0x50, 0xd6 }, { 0x51, 0x1f },
148 { 0x50, 0xd2 }, { 0x51, 0x03 },
149 { 0x50, 0xd7 }, { 0x51, 0x3f },
150 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 },
151 { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c },
152
153 { 0x04, 0x40 }, { 0x05, 0x00 },
154 { 0x28, 0x00 }, { 0x29, 0x10 },
155 { 0x28, 0x05 }, { 0x29, 0x02 },
156 { 0x1c, 0x01 },
157 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
158 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
159 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
160 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
161 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
162 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
163 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
164 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
165 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
166 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
167 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
168 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
169 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
170 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
171 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
172 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
173 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
174 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
175 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
176 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
177 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
178 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
179 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
180 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
181 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
182 { 0x50, 0x1e }, { 0x51, 0x5d },
183 { 0x50, 0x22 }, { 0x51, 0x00 },
184 { 0x50, 0x23 }, { 0x51, 0xc8 },
185 { 0x50, 0x24 }, { 0x51, 0x00 },
186 { 0x50, 0x25 }, { 0x51, 0xf0 },
187 { 0x50, 0x26 }, { 0x51, 0x00 },
188 { 0x50, 0x27 }, { 0x51, 0xc3 },
189 { 0x50, 0x39 }, { 0x51, 0x02 },
190 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
191 { 0xd0, 0x00 },
192 };
193
194 static struct regdata mb86a20s_reset_reception[] = {
195 { 0x70, 0xf0 },
196 { 0x70, 0xff },
197 { 0x08, 0x01 },
198 { 0x08, 0x00 },
199 };
200
201 static struct regdata mb86a20s_per_ber_reset[] = {
202 { 0x53, 0x00 }, /* pre BER Counter reset */
203 { 0x53, 0x07 },
204
205 { 0x5f, 0x00 }, /* post BER Counter reset */
206 { 0x5f, 0x07 },
207
208 { 0x50, 0xb1 }, /* PER Counter reset */
209 { 0x51, 0x07 },
210 { 0x51, 0x00 },
211 };
212
213 /*
214 * I2C read/write functions and macros
215 */
216
217 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
218 u8 i2c_addr, u8 reg, u8 data)
219 {
220 u8 buf[] = { reg, data };
221 struct i2c_msg msg = {
222 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
223 };
224 int rc;
225
226 rc = i2c_transfer(state->i2c, &msg, 1);
227 if (rc != 1) {
228 dev_err(&state->i2c->dev,
229 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
230 __func__, rc, reg, data);
231 return rc;
232 }
233
234 return 0;
235 }
236
237 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
238 u8 i2c_addr, struct regdata *rd, int size)
239 {
240 int i, rc;
241
242 for (i = 0; i < size; i++) {
243 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
244 rd[i].data);
245 if (rc < 0)
246 return rc;
247 }
248 return 0;
249 }
250
251 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
252 u8 i2c_addr, u8 reg)
253 {
254 u8 val;
255 int rc;
256 struct i2c_msg msg[] = {
257 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
258 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
259 };
260
261 rc = i2c_transfer(state->i2c, msg, 2);
262
263 if (rc != 2) {
264 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
265 __func__, reg, rc);
266 return (rc < 0) ? rc : -EIO;
267 }
268
269 return val;
270 }
271
272 #define mb86a20s_readreg(state, reg) \
273 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
274 #define mb86a20s_writereg(state, reg, val) \
275 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
276 #define mb86a20s_writeregdata(state, regdata) \
277 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
278 regdata, ARRAY_SIZE(regdata))
279
280 /*
281 * Ancillary internal routines (likely compiled inlined)
282 *
283 * The functions below assume that gateway lock has already obtained
284 */
285
286 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
287 {
288 struct mb86a20s_state *state = fe->demodulator_priv;
289 int val;
290
291 *status = 0;
292
293 val = mb86a20s_readreg(state, 0x0a) & 0xf;
294 if (val < 0)
295 return val;
296
297 if (val >= 2)
298 *status |= FE_HAS_SIGNAL;
299
300 if (val >= 4)
301 *status |= FE_HAS_CARRIER;
302
303 if (val >= 5)
304 *status |= FE_HAS_VITERBI;
305
306 if (val >= 7)
307 *status |= FE_HAS_SYNC;
308
309 if (val >= 8) /* Maybe 9? */
310 *status |= FE_HAS_LOCK;
311
312 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
313 __func__, *status, val);
314
315 return 0;
316 }
317
318 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
319 {
320 struct mb86a20s_state *state = fe->demodulator_priv;
321 int rc;
322 unsigned rf_max, rf_min, rf;
323
324 /* Does a binary search to get RF strength */
325 rf_max = 0xfff;
326 rf_min = 0;
327 do {
328 rf = (rf_max + rf_min) / 2;
329 rc = mb86a20s_writereg(state, 0x04, 0x1f);
330 if (rc < 0)
331 return rc;
332 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
333 if (rc < 0)
334 return rc;
335 rc = mb86a20s_writereg(state, 0x04, 0x20);
336 if (rc < 0)
337 return rc;
338 rc = mb86a20s_writereg(state, 0x04, rf);
339 if (rc < 0)
340 return rc;
341
342 rc = mb86a20s_readreg(state, 0x02);
343 if (rc < 0)
344 return rc;
345 if (rc & 0x08)
346 rf_min = (rf_max + rf_min) / 2;
347 else
348 rf_max = (rf_max + rf_min) / 2;
349 if (rf_max - rf_min < 4) {
350 rf = (rf_max + rf_min) / 2;
351
352 /* Rescale it from 2^12 (4096) to 2^16 */
353 rf <<= (16 - 12);
354 dev_dbg(&state->i2c->dev,
355 "%s: signal strength = %d (%d < RF=%d < %d)\n",
356 __func__, rf, rf_min, rf >> 4, rf_max);
357 return rf;
358 }
359 } while (1);
360
361 return 0;
362 }
363
364 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
365 unsigned layer)
366 {
367 int rc;
368 static unsigned char reg[] = {
369 [0] = 0x86, /* Layer A */
370 [1] = 0x8a, /* Layer B */
371 [2] = 0x8e, /* Layer C */
372 };
373
374 if (layer >= ARRAY_SIZE(reg))
375 return -EINVAL;
376 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
377 if (rc < 0)
378 return rc;
379 rc = mb86a20s_readreg(state, 0x6e);
380 if (rc < 0)
381 return rc;
382 switch ((rc >> 4) & 0x07) {
383 case 0:
384 return DQPSK;
385 case 1:
386 return QPSK;
387 case 2:
388 return QAM_16;
389 case 3:
390 return QAM_64;
391 default:
392 return QAM_AUTO;
393 }
394 }
395
396 static int mb86a20s_get_fec(struct mb86a20s_state *state,
397 unsigned layer)
398 {
399 int rc;
400
401 static unsigned char reg[] = {
402 [0] = 0x87, /* Layer A */
403 [1] = 0x8b, /* Layer B */
404 [2] = 0x8f, /* Layer C */
405 };
406
407 if (layer >= ARRAY_SIZE(reg))
408 return -EINVAL;
409 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
410 if (rc < 0)
411 return rc;
412 rc = mb86a20s_readreg(state, 0x6e);
413 if (rc < 0)
414 return rc;
415 switch ((rc >> 4) & 0x07) {
416 case 0:
417 return FEC_1_2;
418 case 1:
419 return FEC_2_3;
420 case 2:
421 return FEC_3_4;
422 case 3:
423 return FEC_5_6;
424 case 4:
425 return FEC_7_8;
426 default:
427 return FEC_AUTO;
428 }
429 }
430
431 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
432 unsigned layer)
433 {
434 int rc;
435
436 static unsigned char reg[] = {
437 [0] = 0x88, /* Layer A */
438 [1] = 0x8c, /* Layer B */
439 [2] = 0x90, /* Layer C */
440 };
441
442 if (layer >= ARRAY_SIZE(reg))
443 return -EINVAL;
444 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
445 if (rc < 0)
446 return rc;
447 rc = mb86a20s_readreg(state, 0x6e);
448 if (rc < 0)
449 return rc;
450
451 switch ((rc >> 4) & 0x07) {
452 case 1:
453 return GUARD_INTERVAL_1_4;
454 case 2:
455 return GUARD_INTERVAL_1_8;
456 case 3:
457 return GUARD_INTERVAL_1_16;
458 case 4:
459 return GUARD_INTERVAL_1_32;
460
461 default:
462 case 0:
463 return GUARD_INTERVAL_AUTO;
464 }
465 }
466
467 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
468 unsigned layer)
469 {
470 int rc, count;
471 static unsigned char reg[] = {
472 [0] = 0x89, /* Layer A */
473 [1] = 0x8d, /* Layer B */
474 [2] = 0x91, /* Layer C */
475 };
476
477 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
478
479 if (layer >= ARRAY_SIZE(reg))
480 return -EINVAL;
481
482 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
483 if (rc < 0)
484 return rc;
485 rc = mb86a20s_readreg(state, 0x6e);
486 if (rc < 0)
487 return rc;
488 count = (rc >> 4) & 0x0f;
489
490 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
491
492 return count;
493 }
494
495 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
496 {
497 struct mb86a20s_state *state = fe->demodulator_priv;
498 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
499
500 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
501
502 /* Fixed parameters */
503 c->delivery_system = SYS_ISDBT;
504 c->bandwidth_hz = 6000000;
505
506 /* Initialize values that will be later autodetected */
507 c->isdbt_layer_enabled = 0;
508 c->transmission_mode = TRANSMISSION_MODE_AUTO;
509 c->guard_interval = GUARD_INTERVAL_AUTO;
510 c->isdbt_sb_mode = 0;
511 c->isdbt_sb_segment_count = 0;
512 }
513
514 /*
515 * Estimates the bit rate using the per-segment bit rate given by
516 * ABNT/NBR 15601 spec (table 4).
517 */
518 static u32 isdbt_rate[3][5][4] = {
519 { /* DQPSK/QPSK */
520 { 280850, 312060, 330420, 340430 }, /* 1/2 */
521 { 374470, 416080, 440560, 453910 }, /* 2/3 */
522 { 421280, 468090, 495630, 510650 }, /* 3/4 */
523 { 468090, 520100, 550700, 567390 }, /* 5/6 */
524 { 491500, 546110, 578230, 595760 }, /* 7/8 */
525 }, { /* QAM16 */
526 { 561710, 624130, 660840, 680870 }, /* 1/2 */
527 { 748950, 832170, 881120, 907820 }, /* 2/3 */
528 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
529 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
530 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
531 }, { /* QAM64 */
532 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
533 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
534 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
535 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
536 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
537 }
538 };
539
540 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
541 u32 modulation, u32 fec, u32 interleaving,
542 u32 segment)
543 {
544 struct mb86a20s_state *state = fe->demodulator_priv;
545 u32 rate;
546 int m, f, i;
547
548 /*
549 * If modulation/fec/interleaving is not detected, the default is
550 * to consider the lowest bit rate, to avoid taking too long time
551 * to get BER.
552 */
553 switch (modulation) {
554 case DQPSK:
555 case QPSK:
556 default:
557 m = 0;
558 break;
559 case QAM_16:
560 m = 1;
561 break;
562 case QAM_64:
563 m = 2;
564 break;
565 }
566
567 switch (fec) {
568 default:
569 case FEC_1_2:
570 case FEC_AUTO:
571 f = 0;
572 break;
573 case FEC_2_3:
574 f = 1;
575 break;
576 case FEC_3_4:
577 f = 2;
578 break;
579 case FEC_5_6:
580 f = 3;
581 break;
582 case FEC_7_8:
583 f = 4;
584 break;
585 }
586
587 switch (interleaving) {
588 default:
589 case GUARD_INTERVAL_1_4:
590 i = 0;
591 break;
592 case GUARD_INTERVAL_1_8:
593 i = 1;
594 break;
595 case GUARD_INTERVAL_1_16:
596 i = 2;
597 break;
598 case GUARD_INTERVAL_1_32:
599 i = 3;
600 break;
601 }
602
603 /* Samples BER at BER_SAMPLING_RATE seconds */
604 rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE;
605
606 /* Avoids sampling too quickly or to overflow the register */
607 if (rate < 256)
608 rate = 256;
609 else if (rate > (1 << 24) - 1)
610 rate = (1 << 24) - 1;
611
612 dev_dbg(&state->i2c->dev,
613 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
614 __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000,
615 rate, rate);
616
617 state->estimated_rate[i] = rate;
618 }
619
620
621 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
622 {
623 struct mb86a20s_state *state = fe->demodulator_priv;
624 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
625 int i, rc;
626
627 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
628
629 /* Reset frontend cache to default values */
630 mb86a20s_reset_frontend_cache(fe);
631
632 /* Check for partial reception */
633 rc = mb86a20s_writereg(state, 0x6d, 0x85);
634 if (rc < 0)
635 return rc;
636 rc = mb86a20s_readreg(state, 0x6e);
637 if (rc < 0)
638 return rc;
639 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
640
641 /* Get per-layer data */
642
643 for (i = 0; i < 3; i++) {
644 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
645 __func__, 'A' + i);
646
647 rc = mb86a20s_get_segment_count(state, i);
648 if (rc < 0)
649 goto noperlayer_error;
650 if (rc >= 0 && rc < 14) {
651 c->layer[i].segment_count = rc;
652 } else {
653 c->layer[i].segment_count = 0;
654 state->estimated_rate[i] = 0;
655 continue;
656 }
657 c->isdbt_layer_enabled |= 1 << i;
658 rc = mb86a20s_get_modulation(state, i);
659 if (rc < 0)
660 goto noperlayer_error;
661 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
662 __func__, rc);
663 c->layer[i].modulation = rc;
664 rc = mb86a20s_get_fec(state, i);
665 if (rc < 0)
666 goto noperlayer_error;
667 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
668 __func__, rc);
669 c->layer[i].fec = rc;
670 rc = mb86a20s_get_interleaving(state, i);
671 if (rc < 0)
672 goto noperlayer_error;
673 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
674 __func__, rc);
675 c->layer[i].interleaving = rc;
676 mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation,
677 c->layer[i].fec,
678 c->layer[i].interleaving,
679 c->layer[i].segment_count);
680 }
681
682 rc = mb86a20s_writereg(state, 0x6d, 0x84);
683 if (rc < 0)
684 return rc;
685 if ((rc & 0x60) == 0x20) {
686 c->isdbt_sb_mode = 1;
687 /* At least, one segment should exist */
688 if (!c->isdbt_sb_segment_count)
689 c->isdbt_sb_segment_count = 1;
690 }
691
692 /* Get transmission mode and guard interval */
693 rc = mb86a20s_readreg(state, 0x07);
694 if (rc < 0)
695 return rc;
696 if ((rc & 0x60) == 0x20) {
697 switch (rc & 0x0c >> 2) {
698 case 0:
699 c->transmission_mode = TRANSMISSION_MODE_2K;
700 break;
701 case 1:
702 c->transmission_mode = TRANSMISSION_MODE_4K;
703 break;
704 case 2:
705 c->transmission_mode = TRANSMISSION_MODE_8K;
706 break;
707 }
708 }
709 if (!(rc & 0x10)) {
710 switch (rc & 0x3) {
711 case 0:
712 c->guard_interval = GUARD_INTERVAL_1_4;
713 break;
714 case 1:
715 c->guard_interval = GUARD_INTERVAL_1_8;
716 break;
717 case 2:
718 c->guard_interval = GUARD_INTERVAL_1_16;
719 break;
720 }
721 }
722 return 0;
723
724 noperlayer_error:
725
726 /* per-layer info is incomplete; discard all per-layer */
727 c->isdbt_layer_enabled = 0;
728
729 return rc;
730 }
731
732 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
733 {
734 struct mb86a20s_state *state = fe->demodulator_priv;
735 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
736 int rc, val;
737
738 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
739
740 /* Reset the counters, if the channel changed */
741 if (state->last_frequency != c->frequency) {
742 memset(&c->strength, 0, sizeof(c->strength));
743 memset(&c->cnr, 0, sizeof(c->cnr));
744 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
745 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
746 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
747 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
748 memset(&c->block_error, 0, sizeof(c->block_error));
749 memset(&c->block_count, 0, sizeof(c->block_count));
750
751 state->last_frequency = c->frequency;
752 }
753
754 /* Clear status for most stats */
755
756 /* BER/PER counter reset */
757 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
758 if (rc < 0)
759 goto err;
760
761 /* CNR counter reset */
762 rc = mb86a20s_readreg(state, 0x45);
763 if (rc < 0)
764 goto err;
765 val = rc;
766 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
767 if (rc < 0)
768 goto err;
769 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
770 if (rc < 0)
771 goto err;
772
773 /* MER counter reset */
774 rc = mb86a20s_writereg(state, 0x50, 0x50);
775 if (rc < 0)
776 goto err;
777 rc = mb86a20s_readreg(state, 0x51);
778 if (rc < 0)
779 goto err;
780 val = rc;
781 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
782 if (rc < 0)
783 goto err;
784 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
785 if (rc < 0)
786 goto err;
787
788 goto ok;
789 err:
790 dev_err(&state->i2c->dev,
791 "%s: Can't reset FE statistics (error %d).\n",
792 __func__, rc);
793 ok:
794 return rc;
795 }
796
797 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
798 unsigned layer,
799 u32 *error, u32 *count)
800 {
801 struct mb86a20s_state *state = fe->demodulator_priv;
802 int rc, val;
803
804 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
805
806 if (layer >= 3)
807 return -EINVAL;
808
809 /* Check if the BER measures are already available */
810 rc = mb86a20s_readreg(state, 0x54);
811 if (rc < 0)
812 return rc;
813
814 /* Check if data is available for that layer */
815 if (!(rc & (1 << layer))) {
816 dev_dbg(&state->i2c->dev,
817 "%s: preBER for layer %c is not available yet.\n",
818 __func__, 'A' + layer);
819 return -EBUSY;
820 }
821
822 /* Read Bit Error Count */
823 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
824 if (rc < 0)
825 return rc;
826 *error = rc << 16;
827 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
828 if (rc < 0)
829 return rc;
830 *error |= rc << 8;
831 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
832 if (rc < 0)
833 return rc;
834 *error |= rc;
835
836 dev_dbg(&state->i2c->dev,
837 "%s: bit error before Viterbi for layer %c: %d.\n",
838 __func__, 'A' + layer, *error);
839
840 /* Read Bit Count */
841 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
842 if (rc < 0)
843 return rc;
844 rc = mb86a20s_readreg(state, 0x51);
845 if (rc < 0)
846 return rc;
847 *count = rc << 16;
848 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
849 if (rc < 0)
850 return rc;
851 rc = mb86a20s_readreg(state, 0x51);
852 if (rc < 0)
853 return rc;
854 *count |= rc << 8;
855 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
856 if (rc < 0)
857 return rc;
858 rc = mb86a20s_readreg(state, 0x51);
859 if (rc < 0)
860 return rc;
861 *count |= rc;
862
863 dev_dbg(&state->i2c->dev,
864 "%s: bit count before Viterbi for layer %c: %d.\n",
865 __func__, 'A' + layer, *count);
866
867
868 /*
869 * As we get TMCC data from the frontend, we can better estimate the
870 * BER bit counters, in order to do the BER measure during a longer
871 * time. Use those data, if available, to update the bit count
872 * measure.
873 */
874
875 if (state->estimated_rate[layer]
876 && state->estimated_rate[layer] != *count) {
877 dev_dbg(&state->i2c->dev,
878 "%s: updating layer %c preBER counter to %d.\n",
879 __func__, 'A' + layer, state->estimated_rate[layer]);
880
881 /* Turn off BER before Viterbi */
882 rc = mb86a20s_writereg(state, 0x52, 0x00);
883
884 /* Update counter for this layer */
885 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
886 if (rc < 0)
887 return rc;
888 rc = mb86a20s_writereg(state, 0x51,
889 state->estimated_rate[layer] >> 16);
890 if (rc < 0)
891 return rc;
892 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
893 if (rc < 0)
894 return rc;
895 rc = mb86a20s_writereg(state, 0x51,
896 state->estimated_rate[layer] >> 8);
897 if (rc < 0)
898 return rc;
899 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
900 if (rc < 0)
901 return rc;
902 rc = mb86a20s_writereg(state, 0x51,
903 state->estimated_rate[layer]);
904 if (rc < 0)
905 return rc;
906
907 /* Turn on BER before Viterbi */
908 rc = mb86a20s_writereg(state, 0x52, 0x01);
909
910 /* Reset all preBER counters */
911 rc = mb86a20s_writereg(state, 0x53, 0x00);
912 if (rc < 0)
913 return rc;
914 rc = mb86a20s_writereg(state, 0x53, 0x07);
915 } else {
916 /* Reset counter to collect new data */
917 rc = mb86a20s_readreg(state, 0x53);
918 if (rc < 0)
919 return rc;
920 val = rc;
921 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
922 if (rc < 0)
923 return rc;
924 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
925 }
926
927 return rc;
928 }
929
930 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
931 unsigned layer,
932 u32 *error, u32 *count)
933 {
934 struct mb86a20s_state *state = fe->demodulator_priv;
935 u32 counter, collect_rate;
936 int rc, val;
937
938 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
939
940 if (layer >= 3)
941 return -EINVAL;
942
943 /* Check if the BER measures are already available */
944 rc = mb86a20s_readreg(state, 0x60);
945 if (rc < 0)
946 return rc;
947
948 /* Check if data is available for that layer */
949 if (!(rc & (1 << layer))) {
950 dev_dbg(&state->i2c->dev,
951 "%s: post BER for layer %c is not available yet.\n",
952 __func__, 'A' + layer);
953 return -EBUSY;
954 }
955
956 /* Read Bit Error Count */
957 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
958 if (rc < 0)
959 return rc;
960 *error = rc << 16;
961 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
962 if (rc < 0)
963 return rc;
964 *error |= rc << 8;
965 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
966 if (rc < 0)
967 return rc;
968 *error |= rc;
969
970 dev_dbg(&state->i2c->dev,
971 "%s: post bit error for layer %c: %d.\n",
972 __func__, 'A' + layer, *error);
973
974 /* Read Bit Count */
975 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
976 if (rc < 0)
977 return rc;
978 rc = mb86a20s_readreg(state, 0x51);
979 if (rc < 0)
980 return rc;
981 counter = rc << 8;
982 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
983 if (rc < 0)
984 return rc;
985 rc = mb86a20s_readreg(state, 0x51);
986 if (rc < 0)
987 return rc;
988 counter |= rc;
989 *count = counter * 204 * 8;
990
991 dev_dbg(&state->i2c->dev,
992 "%s: post bit count for layer %c: %d.\n",
993 __func__, 'A' + layer, *count);
994
995 /*
996 * As we get TMCC data from the frontend, we can better estimate the
997 * BER bit counters, in order to do the BER measure during a longer
998 * time. Use those data, if available, to update the bit count
999 * measure.
1000 */
1001
1002 if (!state->estimated_rate[layer])
1003 goto reset_measurement;
1004
1005 collect_rate = state->estimated_rate[layer] / 204 / 8;
1006 if (collect_rate < 32)
1007 collect_rate = 32;
1008 if (collect_rate > 65535)
1009 collect_rate = 65535;
1010 if (collect_rate != counter) {
1011 dev_dbg(&state->i2c->dev,
1012 "%s: updating postBER counter on layer %c to %d.\n",
1013 __func__, 'A' + layer, collect_rate);
1014
1015 /* Turn off BER after Viterbi */
1016 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1017
1018 /* Update counter for this layer */
1019 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1020 if (rc < 0)
1021 return rc;
1022 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1023 if (rc < 0)
1024 return rc;
1025 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1026 if (rc < 0)
1027 return rc;
1028 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1029 if (rc < 0)
1030 return rc;
1031
1032 /* Turn on BER after Viterbi */
1033 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1034
1035 /* Reset all preBER counters */
1036 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1037 if (rc < 0)
1038 return rc;
1039 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1040
1041 return rc;
1042 }
1043
1044 reset_measurement:
1045 /* Reset counter to collect new data */
1046 rc = mb86a20s_readreg(state, 0x5f);
1047 if (rc < 0)
1048 return rc;
1049 val = rc;
1050 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1051 if (rc < 0)
1052 return rc;
1053 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1054
1055 return rc;
1056 }
1057
1058 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1059 unsigned layer,
1060 u32 *error, u32 *count)
1061 {
1062 struct mb86a20s_state *state = fe->demodulator_priv;
1063 int rc, val;
1064 u32 collect_rate;
1065 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1066
1067 if (layer >= 3)
1068 return -EINVAL;
1069
1070 /* Check if the PER measures are already available */
1071 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1072 if (rc < 0)
1073 return rc;
1074 rc = mb86a20s_readreg(state, 0x51);
1075 if (rc < 0)
1076 return rc;
1077
1078 /* Check if data is available for that layer */
1079
1080 if (!(rc & (1 << layer))) {
1081 dev_dbg(&state->i2c->dev,
1082 "%s: block counts for layer %c aren't available yet.\n",
1083 __func__, 'A' + layer);
1084 return -EBUSY;
1085 }
1086
1087 /* Read Packet error Count */
1088 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1089 if (rc < 0)
1090 return rc;
1091 rc = mb86a20s_readreg(state, 0x51);
1092 if (rc < 0)
1093 return rc;
1094 *error = rc << 8;
1095 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1096 if (rc < 0)
1097 return rc;
1098 rc = mb86a20s_readreg(state, 0x51);
1099 if (rc < 0)
1100 return rc;
1101 *error |= rc;
1102 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1103 __func__, 'A' + layer, *error);
1104
1105 /* Read Bit Count */
1106 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1107 if (rc < 0)
1108 return rc;
1109 rc = mb86a20s_readreg(state, 0x51);
1110 if (rc < 0)
1111 return rc;
1112 *count = rc << 8;
1113 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1114 if (rc < 0)
1115 return rc;
1116 rc = mb86a20s_readreg(state, 0x51);
1117 if (rc < 0)
1118 return rc;
1119 *count |= rc;
1120
1121 dev_dbg(&state->i2c->dev,
1122 "%s: block count for layer %c: %d.\n",
1123 __func__, 'A' + layer, *count);
1124
1125 /*
1126 * As we get TMCC data from the frontend, we can better estimate the
1127 * BER bit counters, in order to do the BER measure during a longer
1128 * time. Use those data, if available, to update the bit count
1129 * measure.
1130 */
1131
1132 if (!state->estimated_rate[layer])
1133 goto reset_measurement;
1134
1135 collect_rate = state->estimated_rate[layer] / 204 / 8;
1136 if (collect_rate < 32)
1137 collect_rate = 32;
1138 if (collect_rate > 65535)
1139 collect_rate = 65535;
1140
1141 if (collect_rate != *count) {
1142 dev_dbg(&state->i2c->dev,
1143 "%s: updating PER counter on layer %c to %d.\n",
1144 __func__, 'A' + layer, collect_rate);
1145
1146 /* Stop PER measurement */
1147 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1148 if (rc < 0)
1149 return rc;
1150 rc = mb86a20s_writereg(state, 0x51, 0x00);
1151 if (rc < 0)
1152 return rc;
1153
1154 /* Update this layer's counter */
1155 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1156 if (rc < 0)
1157 return rc;
1158 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1159 if (rc < 0)
1160 return rc;
1161 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1162 if (rc < 0)
1163 return rc;
1164 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1165 if (rc < 0)
1166 return rc;
1167
1168 /* start PER measurement */
1169 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1170 if (rc < 0)
1171 return rc;
1172 rc = mb86a20s_writereg(state, 0x51, 0x07);
1173 if (rc < 0)
1174 return rc;
1175
1176 /* Reset all counters to collect new data */
1177 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1178 if (rc < 0)
1179 return rc;
1180 rc = mb86a20s_writereg(state, 0x51, 0x07);
1181 if (rc < 0)
1182 return rc;
1183 rc = mb86a20s_writereg(state, 0x51, 0x00);
1184
1185 return rc;
1186 }
1187
1188 reset_measurement:
1189 /* Reset counter to collect new data */
1190 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1191 if (rc < 0)
1192 return rc;
1193 rc = mb86a20s_readreg(state, 0x51);
1194 if (rc < 0)
1195 return rc;
1196 val = rc;
1197 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1198 if (rc < 0)
1199 return rc;
1200 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1201
1202 return rc;
1203 }
1204
1205 struct linear_segments {
1206 unsigned x, y;
1207 };
1208
1209 /*
1210 * All tables below return a dB/1000 measurement
1211 */
1212
1213 static struct linear_segments cnr_to_db_table[] = {
1214 { 19648, 0},
1215 { 18187, 1000},
1216 { 16534, 2000},
1217 { 14823, 3000},
1218 { 13161, 4000},
1219 { 11622, 5000},
1220 { 10279, 6000},
1221 { 9089, 7000},
1222 { 8042, 8000},
1223 { 7137, 9000},
1224 { 6342, 10000},
1225 { 5641, 11000},
1226 { 5030, 12000},
1227 { 4474, 13000},
1228 { 3988, 14000},
1229 { 3556, 15000},
1230 { 3180, 16000},
1231 { 2841, 17000},
1232 { 2541, 18000},
1233 { 2276, 19000},
1234 { 2038, 20000},
1235 { 1800, 21000},
1236 { 1625, 22000},
1237 { 1462, 23000},
1238 { 1324, 24000},
1239 { 1175, 25000},
1240 { 1063, 26000},
1241 { 980, 27000},
1242 { 907, 28000},
1243 { 840, 29000},
1244 { 788, 30000},
1245 };
1246
1247 static struct linear_segments cnr_64qam_table[] = {
1248 { 3922688, 0},
1249 { 3920384, 1000},
1250 { 3902720, 2000},
1251 { 3894784, 3000},
1252 { 3882496, 4000},
1253 { 3872768, 5000},
1254 { 3858944, 6000},
1255 { 3851520, 7000},
1256 { 3838976, 8000},
1257 { 3829248, 9000},
1258 { 3818240, 10000},
1259 { 3806976, 11000},
1260 { 3791872, 12000},
1261 { 3767040, 13000},
1262 { 3720960, 14000},
1263 { 3637504, 15000},
1264 { 3498496, 16000},
1265 { 3296000, 17000},
1266 { 3031040, 18000},
1267 { 2715392, 19000},
1268 { 2362624, 20000},
1269 { 1963264, 21000},
1270 { 1649664, 22000},
1271 { 1366784, 23000},
1272 { 1120768, 24000},
1273 { 890880, 25000},
1274 { 723456, 26000},
1275 { 612096, 27000},
1276 { 518912, 28000},
1277 { 448256, 29000},
1278 { 388864, 30000},
1279 };
1280
1281 static struct linear_segments cnr_16qam_table[] = {
1282 { 5314816, 0},
1283 { 5219072, 1000},
1284 { 5118720, 2000},
1285 { 4998912, 3000},
1286 { 4875520, 4000},
1287 { 4736000, 5000},
1288 { 4604160, 6000},
1289 { 4458752, 7000},
1290 { 4300288, 8000},
1291 { 4092928, 9000},
1292 { 3836160, 10000},
1293 { 3521024, 11000},
1294 { 3155968, 12000},
1295 { 2756864, 13000},
1296 { 2347008, 14000},
1297 { 1955072, 15000},
1298 { 1593600, 16000},
1299 { 1297920, 17000},
1300 { 1043968, 18000},
1301 { 839680, 19000},
1302 { 672256, 20000},
1303 { 523008, 21000},
1304 { 424704, 22000},
1305 { 345088, 23000},
1306 { 280064, 24000},
1307 { 221440, 25000},
1308 { 179712, 26000},
1309 { 151040, 27000},
1310 { 128512, 28000},
1311 { 110080, 29000},
1312 { 95744, 30000},
1313 };
1314
1315 struct linear_segments cnr_qpsk_table[] = {
1316 { 2834176, 0},
1317 { 2683648, 1000},
1318 { 2536960, 2000},
1319 { 2391808, 3000},
1320 { 2133248, 4000},
1321 { 1906176, 5000},
1322 { 1666560, 6000},
1323 { 1422080, 7000},
1324 { 1189632, 8000},
1325 { 976384, 9000},
1326 { 790272, 10000},
1327 { 633344, 11000},
1328 { 505600, 12000},
1329 { 402944, 13000},
1330 { 320768, 14000},
1331 { 255488, 15000},
1332 { 204032, 16000},
1333 { 163072, 17000},
1334 { 130304, 18000},
1335 { 105216, 19000},
1336 { 83456, 20000},
1337 { 65024, 21000},
1338 { 52480, 22000},
1339 { 42752, 23000},
1340 { 34560, 24000},
1341 { 27136, 25000},
1342 { 22016, 26000},
1343 { 18432, 27000},
1344 { 15616, 28000},
1345 { 13312, 29000},
1346 { 11520, 30000},
1347 };
1348
1349 static u32 interpolate_value(u32 value, struct linear_segments *segments,
1350 unsigned len)
1351 {
1352 u64 tmp64;
1353 u32 dx, dy;
1354 int i, ret;
1355
1356 if (value >= segments[0].x)
1357 return segments[0].y;
1358 if (value < segments[len-1].x)
1359 return segments[len-1].y;
1360
1361 for (i = 1; i < len - 1; i++) {
1362 /* If value is identical, no need to interpolate */
1363 if (value == segments[i].x)
1364 return segments[i].y;
1365 if (value > segments[i].x)
1366 break;
1367 }
1368
1369 /* Linear interpolation between the two (x,y) points */
1370 dy = segments[i].y - segments[i - 1].y;
1371 dx = segments[i - 1].x - segments[i].x;
1372 tmp64 = value - segments[i].x;
1373 tmp64 *= dy;
1374 do_div(tmp64, dx);
1375 ret = segments[i].y - tmp64;
1376
1377 return ret;
1378 }
1379
1380 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1381 {
1382 struct mb86a20s_state *state = fe->demodulator_priv;
1383 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1384 u32 cnr_linear, cnr;
1385 int rc, val;
1386
1387 /* Check if CNR is available */
1388 rc = mb86a20s_readreg(state, 0x45);
1389 if (rc < 0)
1390 return rc;
1391
1392 if (!(rc & 0x40)) {
1393 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1394 __func__);
1395 return -EBUSY;
1396 }
1397 val = rc;
1398
1399 rc = mb86a20s_readreg(state, 0x46);
1400 if (rc < 0)
1401 return rc;
1402 cnr_linear = rc << 8;
1403
1404 rc = mb86a20s_readreg(state, 0x46);
1405 if (rc < 0)
1406 return rc;
1407 cnr_linear |= rc;
1408
1409 cnr = interpolate_value(cnr_linear,
1410 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1411
1412 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1413 c->cnr.stat[0].svalue = cnr;
1414
1415 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1416 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1417
1418 /* CNR counter reset */
1419 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1420 if (rc < 0)
1421 return rc;
1422 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1423
1424 return rc;
1425 }
1426
1427 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1428 {
1429 struct mb86a20s_state *state = fe->demodulator_priv;
1430 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1431 u32 mer, cnr;
1432 int rc, val, i;
1433 struct linear_segments *segs;
1434 unsigned segs_len;
1435
1436 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1437
1438 /* Check if the measures are already available */
1439 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1440 if (rc < 0)
1441 return rc;
1442 rc = mb86a20s_readreg(state, 0x51);
1443 if (rc < 0)
1444 return rc;
1445
1446 /* Check if data is available */
1447 if (!(rc & 0x01)) {
1448 dev_dbg(&state->i2c->dev,
1449 "%s: MER measures aren't available yet.\n", __func__);
1450 return -EBUSY;
1451 }
1452
1453 /* Read all layers */
1454 for (i = 0; i < 3; i++) {
1455 if (!(c->isdbt_layer_enabled & (1 << i))) {
1456 c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1457 continue;
1458 }
1459
1460 rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3);
1461 if (rc < 0)
1462 return rc;
1463 rc = mb86a20s_readreg(state, 0x51);
1464 if (rc < 0)
1465 return rc;
1466 mer = rc << 16;
1467 rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3);
1468 if (rc < 0)
1469 return rc;
1470 rc = mb86a20s_readreg(state, 0x51);
1471 if (rc < 0)
1472 return rc;
1473 mer |= rc << 8;
1474 rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3);
1475 if (rc < 0)
1476 return rc;
1477 rc = mb86a20s_readreg(state, 0x51);
1478 if (rc < 0)
1479 return rc;
1480 mer |= rc;
1481
1482 switch (c->layer[i].modulation) {
1483 case DQPSK:
1484 case QPSK:
1485 segs = cnr_qpsk_table;
1486 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1487 break;
1488 case QAM_16:
1489 segs = cnr_16qam_table;
1490 segs_len = ARRAY_SIZE(cnr_16qam_table);
1491 break;
1492 default:
1493 case QAM_64:
1494 segs = cnr_64qam_table;
1495 segs_len = ARRAY_SIZE(cnr_64qam_table);
1496 break;
1497 }
1498 cnr = interpolate_value(mer, segs, segs_len);
1499
1500 c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL;
1501 c->cnr.stat[1 + i].svalue = cnr;
1502
1503 dev_dbg(&state->i2c->dev,
1504 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1505 __func__, 'A' + i, cnr / 1000, cnr % 1000, mer);
1506
1507 }
1508
1509 /* Start a new MER measurement */
1510 /* MER counter reset */
1511 rc = mb86a20s_writereg(state, 0x50, 0x50);
1512 if (rc < 0)
1513 return rc;
1514 rc = mb86a20s_readreg(state, 0x51);
1515 if (rc < 0)
1516 return rc;
1517 val = rc;
1518
1519 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1520 if (rc < 0)
1521 return rc;
1522 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1523 if (rc < 0)
1524 return rc;
1525
1526 return 0;
1527 }
1528
1529 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1530 {
1531 struct mb86a20s_state *state = fe->demodulator_priv;
1532 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1533 int i;
1534
1535 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1536
1537 /* Fill the length of each status counter */
1538
1539 /* Only global stats */
1540 c->strength.len = 1;
1541
1542 /* Per-layer stats - 3 layers + global */
1543 c->cnr.len = 4;
1544 c->pre_bit_error.len = 4;
1545 c->pre_bit_count.len = 4;
1546 c->post_bit_error.len = 4;
1547 c->post_bit_count.len = 4;
1548 c->block_error.len = 4;
1549 c->block_count.len = 4;
1550
1551 /* Signal is always available */
1552 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1553 c->strength.stat[0].uvalue = 0;
1554
1555 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1556 for (i = 0; i < 4; i++) {
1557 c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1558 c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1559 c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1560 c->post_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1561 c->post_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1562 c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1563 c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1564 }
1565 }
1566
1567 static int mb86a20s_get_stats(struct dvb_frontend *fe)
1568 {
1569 struct mb86a20s_state *state = fe->demodulator_priv;
1570 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1571 int rc = 0, i;
1572 u32 bit_error = 0, bit_count = 0;
1573 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1574 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1575 u32 block_error = 0, block_count = 0;
1576 u32 t_block_error = 0, t_block_count = 0;
1577 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1578 int per_layers = 0;
1579
1580 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1581
1582 mb86a20s_get_main_CNR(fe);
1583
1584 /* Get per-layer stats */
1585 mb86a20s_get_blk_error_layer_CNR(fe);
1586
1587 for (i = 0; i < 3; i++) {
1588 if (c->isdbt_layer_enabled & (1 << i)) {
1589 /* Layer is active and has rc segments */
1590 active_layers++;
1591
1592 /* Handle BER before vterbi */
1593 rc = mb86a20s_get_pre_ber(fe, i,
1594 &bit_error, &bit_count);
1595 if (rc >= 0) {
1596 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1597 c->pre_bit_error.stat[1 + i].uvalue += bit_error;
1598 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1599 c->pre_bit_count.stat[1 + i].uvalue += bit_count;
1600 } else if (rc != -EBUSY) {
1601 /*
1602 * If an I/O error happened,
1603 * measures are now unavailable
1604 */
1605 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1606 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1607 dev_err(&state->i2c->dev,
1608 "%s: Can't get BER for layer %c (error %d).\n",
1609 __func__, 'A' + i, rc);
1610 }
1611 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1612 pre_ber_layers++;
1613
1614 /* Handle BER post vterbi */
1615 rc = mb86a20s_get_post_ber(fe, i,
1616 &bit_error, &bit_count);
1617 if (rc >= 0) {
1618 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1619 c->post_bit_error.stat[1 + i].uvalue += bit_error;
1620 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1621 c->post_bit_count.stat[1 + i].uvalue += bit_count;
1622 } else if (rc != -EBUSY) {
1623 /*
1624 * If an I/O error happened,
1625 * measures are now unavailable
1626 */
1627 c->post_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1628 c->post_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1629 dev_err(&state->i2c->dev,
1630 "%s: Can't get BER for layer %c (error %d).\n",
1631 __func__, 'A' + i, rc);
1632 }
1633 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1634 post_ber_layers++;
1635
1636 /* Handle Block errors for PER/UCB reports */
1637 rc = mb86a20s_get_blk_error(fe, i,
1638 &block_error,
1639 &block_count);
1640 if (rc >= 0) {
1641 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1642 c->block_error.stat[1 + i].uvalue += block_error;
1643 c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1644 c->block_count.stat[1 + i].uvalue += block_count;
1645 } else if (rc != -EBUSY) {
1646 /*
1647 * If an I/O error happened,
1648 * measures are now unavailable
1649 */
1650 c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1651 c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1652 dev_err(&state->i2c->dev,
1653 "%s: Can't get PER for layer %c (error %d).\n",
1654 __func__, 'A' + i, rc);
1655
1656 }
1657 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1658 per_layers++;
1659
1660 /* Update total preBER */
1661 t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue;
1662 t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue;
1663
1664 /* Update total postBER */
1665 t_post_bit_error += c->post_bit_error.stat[1 + i].uvalue;
1666 t_post_bit_count += c->post_bit_count.stat[1 + i].uvalue;
1667
1668 /* Update total PER */
1669 t_block_error += c->block_error.stat[1 + i].uvalue;
1670 t_block_count += c->block_count.stat[1 + i].uvalue;
1671 }
1672 }
1673
1674 /*
1675 * Start showing global count if at least one error count is
1676 * available.
1677 */
1678 if (pre_ber_layers) {
1679 /*
1680 * At least one per-layer BER measure was read. We can now
1681 * calculate the total BER
1682 *
1683 * Total Bit Error/Count is calculated as the sum of the
1684 * bit errors on all active layers.
1685 */
1686 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1687 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1688 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1689 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1690 } else {
1691 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1692 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1693 }
1694
1695 /*
1696 * Start showing global count if at least one error count is
1697 * available.
1698 */
1699 if (post_ber_layers) {
1700 /*
1701 * At least one per-layer BER measure was read. We can now
1702 * calculate the total BER
1703 *
1704 * Total Bit Error/Count is calculated as the sum of the
1705 * bit errors on all active layers.
1706 */
1707 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1708 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1709 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1710 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1711 } else {
1712 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1713 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1714 }
1715
1716 if (per_layers) {
1717 /*
1718 * At least one per-layer UCB measure was read. We can now
1719 * calculate the total UCB
1720 *
1721 * Total block Error/Count is calculated as the sum of the
1722 * block errors on all active layers.
1723 */
1724 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1725 c->block_error.stat[0].uvalue = t_block_error;
1726 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1727 c->block_count.stat[0].uvalue = t_block_count;
1728 } else {
1729 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1730 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1731 }
1732
1733 return rc;
1734 }
1735
1736 /*
1737 * The functions below are called via DVB callbacks, so they need to
1738 * properly use the I2C gate control
1739 */
1740
1741 static int mb86a20s_initfe(struct dvb_frontend *fe)
1742 {
1743 struct mb86a20s_state *state = fe->demodulator_priv;
1744 u64 pll;
1745 int rc;
1746 u8 regD5 = 1;
1747
1748 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1749
1750 if (fe->ops.i2c_gate_ctrl)
1751 fe->ops.i2c_gate_ctrl(fe, 0);
1752
1753 /* Initialize the frontend */
1754 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1755 if (rc < 0)
1756 goto err;
1757
1758 /* Adjust IF frequency to match tuner */
1759 if (fe->ops.tuner_ops.get_if_frequency)
1760 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1761
1762 if (!state->if_freq)
1763 state->if_freq = 3300000;
1764
1765 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1766 pll = state->if_freq * 1677721600L;
1767 do_div(pll, 1628571429L);
1768 rc = mb86a20s_writereg(state, 0x28, 0x20);
1769 if (rc < 0)
1770 goto err;
1771 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1772 if (rc < 0)
1773 goto err;
1774 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1775 if (rc < 0)
1776 goto err;
1777 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1778 if (rc < 0)
1779 goto err;
1780 dev_dbg(&state->i2c->dev, "%s: IF=%d, PLL=0x%06llx\n",
1781 __func__, state->if_freq, (long long)pll);
1782
1783 if (!state->config->is_serial) {
1784 regD5 &= ~1;
1785
1786 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1787 if (rc < 0)
1788 goto err;
1789 rc = mb86a20s_writereg(state, 0x51, regD5);
1790 if (rc < 0)
1791 goto err;
1792 }
1793
1794 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1795 if (rc < 0)
1796 goto err;
1797
1798
1799 err:
1800 if (fe->ops.i2c_gate_ctrl)
1801 fe->ops.i2c_gate_ctrl(fe, 1);
1802
1803 if (rc < 0) {
1804 state->need_init = true;
1805 dev_info(&state->i2c->dev,
1806 "mb86a20s: Init failed. Will try again later\n");
1807 } else {
1808 state->need_init = false;
1809 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1810 }
1811 return rc;
1812 }
1813
1814 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1815 {
1816 struct mb86a20s_state *state = fe->demodulator_priv;
1817 int rc, if_freq;
1818 #if 0
1819 /*
1820 * FIXME: Properly implement the set frontend properties
1821 */
1822 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1823 #endif
1824 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1825
1826 /*
1827 * Gate should already be opened, but it doesn't hurt to
1828 * double-check
1829 */
1830 if (fe->ops.i2c_gate_ctrl)
1831 fe->ops.i2c_gate_ctrl(fe, 1);
1832 fe->ops.tuner_ops.set_params(fe);
1833
1834 if (fe->ops.tuner_ops.get_if_frequency) {
1835 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1836
1837 /*
1838 * If the IF frequency changed, re-initialize the
1839 * frontend. This is needed by some drivers like tda18271,
1840 * that only sets the IF after receiving a set_params() call
1841 */
1842 if (if_freq != state->if_freq)
1843 state->need_init = true;
1844 }
1845
1846 /*
1847 * Make it more reliable: if, for some reason, the initial
1848 * device initialization doesn't happen, initialize it when
1849 * a SBTVD parameters are adjusted.
1850 *
1851 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1852 * the agc callback logic is not called during DVB attach time,
1853 * causing mb86a20s to not be initialized with Kworld SBTVD.
1854 * So, this hack is needed, in order to make Kworld SBTVD to work.
1855 *
1856 * It is also needed to change the IF after the initial init.
1857 */
1858 if (state->need_init)
1859 mb86a20s_initfe(fe);
1860
1861 if (fe->ops.i2c_gate_ctrl)
1862 fe->ops.i2c_gate_ctrl(fe, 0);
1863
1864 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1865 mb86a20s_reset_counters(fe);
1866
1867 if (fe->ops.i2c_gate_ctrl)
1868 fe->ops.i2c_gate_ctrl(fe, 1);
1869
1870 return rc;
1871 }
1872
1873 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1874 fe_status_t *status)
1875 {
1876 struct mb86a20s_state *state = fe->demodulator_priv;
1877 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1878 int rc;
1879
1880 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1881
1882 if (fe->ops.i2c_gate_ctrl)
1883 fe->ops.i2c_gate_ctrl(fe, 0);
1884
1885 /* Get lock */
1886 rc = mb86a20s_read_status(fe, status);
1887 if (!(*status & FE_HAS_LOCK)) {
1888 mb86a20s_stats_not_ready(fe);
1889 mb86a20s_reset_frontend_cache(fe);
1890 }
1891 if (rc < 0) {
1892 dev_err(&state->i2c->dev,
1893 "%s: Can't read frontend lock status\n", __func__);
1894 goto error;
1895 }
1896
1897 /* Get signal strength */
1898 rc = mb86a20s_read_signal_strength(fe);
1899 if (rc < 0) {
1900 dev_err(&state->i2c->dev,
1901 "%s: Can't reset VBER registers.\n", __func__);
1902 mb86a20s_stats_not_ready(fe);
1903 mb86a20s_reset_frontend_cache(fe);
1904
1905 rc = 0; /* Status is OK */
1906 goto error;
1907 }
1908 /* Fill signal strength */
1909 c->strength.stat[0].uvalue = rc;
1910
1911 if (*status & FE_HAS_LOCK) {
1912 /* Get TMCC info*/
1913 rc = mb86a20s_get_frontend(fe);
1914 if (rc < 0) {
1915 dev_err(&state->i2c->dev,
1916 "%s: Can't get FE TMCC data.\n", __func__);
1917 rc = 0; /* Status is OK */
1918 goto error;
1919 }
1920
1921 /* Get statistics */
1922 rc = mb86a20s_get_stats(fe);
1923 if (rc < 0 && rc != -EBUSY) {
1924 dev_err(&state->i2c->dev,
1925 "%s: Can't get FE statistics.\n", __func__);
1926 rc = 0;
1927 goto error;
1928 }
1929 rc = 0; /* Don't return EBUSY to userspace */
1930 }
1931 goto ok;
1932
1933 error:
1934 mb86a20s_stats_not_ready(fe);
1935
1936 ok:
1937 if (fe->ops.i2c_gate_ctrl)
1938 fe->ops.i2c_gate_ctrl(fe, 1);
1939
1940 return rc;
1941 }
1942
1943 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
1944 u16 *strength)
1945 {
1946 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1947
1948
1949 *strength = c->strength.stat[0].uvalue;
1950
1951 return 0;
1952 }
1953
1954 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
1955 {
1956 /*
1957 * get_frontend is now handled together with other stats
1958 * retrival, when read_status() is called, as some statistics
1959 * will depend on the layers detection.
1960 */
1961 return 0;
1962 };
1963
1964 static int mb86a20s_tune(struct dvb_frontend *fe,
1965 bool re_tune,
1966 unsigned int mode_flags,
1967 unsigned int *delay,
1968 fe_status_t *status)
1969 {
1970 struct mb86a20s_state *state = fe->demodulator_priv;
1971 int rc = 0;
1972
1973 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1974
1975 if (re_tune)
1976 rc = mb86a20s_set_frontend(fe);
1977
1978 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1979 mb86a20s_read_status_and_stats(fe, status);
1980
1981 return rc;
1982 }
1983
1984 static void mb86a20s_release(struct dvb_frontend *fe)
1985 {
1986 struct mb86a20s_state *state = fe->demodulator_priv;
1987
1988 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1989
1990 kfree(state);
1991 }
1992
1993 static struct dvb_frontend_ops mb86a20s_ops;
1994
1995 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
1996 struct i2c_adapter *i2c)
1997 {
1998 struct mb86a20s_state *state;
1999 u8 rev;
2000
2001 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2002
2003 /* allocate memory for the internal state */
2004 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
2005 if (state == NULL) {
2006 dev_err(&i2c->dev,
2007 "%s: unable to allocate memory for state\n", __func__);
2008 goto error;
2009 }
2010
2011 /* setup the state */
2012 state->config = config;
2013 state->i2c = i2c;
2014
2015 /* create dvb_frontend */
2016 memcpy(&state->frontend.ops, &mb86a20s_ops,
2017 sizeof(struct dvb_frontend_ops));
2018 state->frontend.demodulator_priv = state;
2019
2020 /* Check if it is a mb86a20s frontend */
2021 rev = mb86a20s_readreg(state, 0);
2022
2023 if (rev == 0x13) {
2024 dev_info(&i2c->dev,
2025 "Detected a Fujitsu mb86a20s frontend\n");
2026 } else {
2027 dev_dbg(&i2c->dev,
2028 "Frontend revision %d is unknown - aborting.\n",
2029 rev);
2030 goto error;
2031 }
2032
2033 return &state->frontend;
2034
2035 error:
2036 kfree(state);
2037 return NULL;
2038 }
2039 EXPORT_SYMBOL(mb86a20s_attach);
2040
2041 static struct dvb_frontend_ops mb86a20s_ops = {
2042 .delsys = { SYS_ISDBT },
2043 /* Use dib8000 values per default */
2044 .info = {
2045 .name = "Fujitsu mb86A20s",
2046 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER |
2047 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2048 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2049 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2050 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2051 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2052 /* Actually, those values depend on the used tuner */
2053 .frequency_min = 45000000,
2054 .frequency_max = 864000000,
2055 .frequency_stepsize = 62500,
2056 },
2057
2058 .release = mb86a20s_release,
2059
2060 .init = mb86a20s_initfe,
2061 .set_frontend = mb86a20s_set_frontend,
2062 .get_frontend = mb86a20s_get_frontend_dummy,
2063 .read_status = mb86a20s_read_status_and_stats,
2064 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2065 .tune = mb86a20s_tune,
2066 };
2067
2068 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2069 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2070 MODULE_LICENSE("GPL");
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