2 Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
5 Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 http://products.zarlink.com/product_profiles/MT312.htm
24 http://products.zarlink.com/product_profiles/SL1935.htm
27 #include <linux/delay.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/string.h>
33 #include <linux/slab.h>
35 #include "dvb_frontend.h"
36 #include "mt312_priv.h"
41 struct i2c_adapter
*i2c
;
42 /* configuration settings */
43 const struct mt312_config
*config
;
44 struct dvb_frontend frontend
;
52 #define dprintk(args...) \
55 printk(KERN_DEBUG "mt312: " args); \
58 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
59 #define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */
61 static int mt312_read(struct mt312_state
*state
, const enum mt312_reg_addr reg
,
62 u8
*buf
, const size_t count
)
65 struct i2c_msg msg
[2];
66 u8 regbuf
[1] = { reg
};
68 msg
[0].addr
= state
->config
->demod_address
;
72 msg
[1].addr
= state
->config
->demod_address
;
73 msg
[1].flags
= I2C_M_RD
;
77 ret
= i2c_transfer(state
->i2c
, msg
, 2);
80 printk(KERN_DEBUG
"%s: ret == %d\n", __func__
, ret
);
86 dprintk("R(%d):", reg
& 0x7f);
87 for (i
= 0; i
< count
; i
++)
88 printk(KERN_CONT
" %02x", buf
[i
]);
95 static int mt312_write(struct mt312_state
*state
, const enum mt312_reg_addr reg
,
96 const u8
*src
, const size_t count
)
104 dprintk("W(%d):", reg
& 0x7f);
105 for (i
= 0; i
< count
; i
++)
106 printk(KERN_CONT
" %02x", src
[i
]);
111 memcpy(&buf
[1], src
, count
);
113 msg
.addr
= state
->config
->demod_address
;
118 ret
= i2c_transfer(state
->i2c
, &msg
, 1);
121 dprintk("%s: ret == %d\n", __func__
, ret
);
128 static inline int mt312_readreg(struct mt312_state
*state
,
129 const enum mt312_reg_addr reg
, u8
*val
)
131 return mt312_read(state
, reg
, val
, 1);
134 static inline int mt312_writereg(struct mt312_state
*state
,
135 const enum mt312_reg_addr reg
, const u8 val
)
137 return mt312_write(state
, reg
, &val
, 1);
140 static inline u32
mt312_div(u32 a
, u32 b
)
142 return (a
+ (b
/ 2)) / b
;
145 static int mt312_reset(struct mt312_state
*state
, const u8 full
)
147 return mt312_writereg(state
, RESET
, full
? 0x80 : 0x40);
150 static int mt312_get_inversion(struct mt312_state
*state
,
151 fe_spectral_inversion_t
*i
)
156 ret
= mt312_readreg(state
, VIT_MODE
, &vit_mode
);
160 if (vit_mode
& 0x80) /* auto inversion was used */
161 *i
= (vit_mode
& 0x40) ? INVERSION_ON
: INVERSION_OFF
;
166 static int mt312_get_symbol_rate(struct mt312_state
*state
, u32
*sr
)
175 ret
= mt312_readreg(state
, SYM_RATE_H
, &sym_rate_h
);
179 if (sym_rate_h
& 0x80) {
180 /* symbol rate search was used */
181 ret
= mt312_writereg(state
, MON_CTRL
, 0x03);
185 ret
= mt312_read(state
, MONITOR_H
, buf
, sizeof(buf
));
189 monitor
= (buf
[0] << 8) | buf
[1];
191 dprintk("sr(auto) = %u\n",
192 mt312_div(monitor
* 15625, 4));
194 ret
= mt312_writereg(state
, MON_CTRL
, 0x05);
198 ret
= mt312_read(state
, MONITOR_H
, buf
, sizeof(buf
));
202 dec_ratio
= ((buf
[0] >> 5) & 0x07) * 32;
204 ret
= mt312_read(state
, SYM_RAT_OP_H
, buf
, sizeof(buf
));
208 sym_rat_op
= (buf
[0] << 8) | buf
[1];
210 dprintk("sym_rat_op=%d dec_ratio=%d\n",
211 sym_rat_op
, dec_ratio
);
212 dprintk("*sr(manual) = %lu\n",
213 (((state
->xtal
* 8192) / (sym_rat_op
+ 8192)) *
220 static int mt312_get_code_rate(struct mt312_state
*state
, fe_code_rate_t
*cr
)
222 const fe_code_rate_t fec_tab
[8] =
223 { FEC_1_2
, FEC_2_3
, FEC_3_4
, FEC_5_6
, FEC_6_7
, FEC_7_8
,
224 FEC_AUTO
, FEC_AUTO
};
229 ret
= mt312_readreg(state
, FEC_STATUS
, &fec_status
);
233 *cr
= fec_tab
[(fec_status
>> 4) & 0x07];
238 static int mt312_initfe(struct dvb_frontend
*fe
)
240 struct mt312_state
*state
= fe
->demodulator_priv
;
245 ret
= mt312_writereg(state
, CONFIG
,
246 (state
->freq_mult
== 6 ? 0x88 : 0x8c));
250 /* wait at least 150 usec */
254 ret
= mt312_reset(state
, 1);
258 /* Per datasheet, write correct values. 09/28/03 ACCJr.
259 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
261 u8 buf_def
[8] = { 0x14, 0x12, 0x03, 0x02,
262 0x01, 0x00, 0x00, 0x00 };
264 ret
= mt312_write(state
, VIT_SETUP
, buf_def
, sizeof(buf_def
));
272 ret
= mt312_writereg(state
, GPP_CTRL
, 0x80);
276 /* configure ZL10313 for optimal ADC performance */
279 ret
= mt312_write(state
, HW_CTRL
, buf
, 2);
283 /* enable MPEG output and ADCs */
284 ret
= mt312_writereg(state
, HW_CTRL
, 0x00);
288 ret
= mt312_writereg(state
, MPEG_CTRL
, 0x00);
296 buf
[0] = mt312_div(state
->xtal
* state
->freq_mult
* 2, 1000000);
299 buf
[1] = mt312_div(state
->xtal
, 22000 * 4);
301 ret
= mt312_write(state
, SYS_CLK
, buf
, sizeof(buf
));
305 ret
= mt312_writereg(state
, SNR_THS_HIGH
, 0x32);
309 /* different MOCLK polarity */
319 ret
= mt312_writereg(state
, OP_CTRL
, buf
[0]);
327 ret
= mt312_write(state
, TS_SW_LIM_L
, buf
, sizeof(buf
));
331 ret
= mt312_writereg(state
, CS_SW_LIM
, 0x69);
338 static int mt312_send_master_cmd(struct dvb_frontend
*fe
,
339 struct dvb_diseqc_master_cmd
*c
)
341 struct mt312_state
*state
= fe
->demodulator_priv
;
345 if ((c
->msg_len
== 0) || (c
->msg_len
> sizeof(c
->msg
)))
348 ret
= mt312_readreg(state
, DISEQC_MODE
, &diseqc_mode
);
352 ret
= mt312_write(state
, (0x80 | DISEQC_INSTR
), c
->msg
, c
->msg_len
);
356 ret
= mt312_writereg(state
, DISEQC_MODE
,
357 (diseqc_mode
& 0x40) | ((c
->msg_len
- 1) << 3)
362 /* is there a better way to wait for message to be transmitted */
365 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
366 if (c
->msg
[0] & 0x02) {
367 ret
= mt312_writereg(state
, DISEQC_MODE
, (diseqc_mode
& 0x40));
375 static int mt312_send_burst(struct dvb_frontend
*fe
, const fe_sec_mini_cmd_t c
)
377 struct mt312_state
*state
= fe
->demodulator_priv
;
378 const u8 mini_tab
[2] = { 0x02, 0x03 };
386 ret
= mt312_readreg(state
, DISEQC_MODE
, &diseqc_mode
);
390 ret
= mt312_writereg(state
, DISEQC_MODE
,
391 (diseqc_mode
& 0x40) | mini_tab
[c
]);
398 static int mt312_set_tone(struct dvb_frontend
*fe
, const fe_sec_tone_mode_t t
)
400 struct mt312_state
*state
= fe
->demodulator_priv
;
401 const u8 tone_tab
[2] = { 0x01, 0x00 };
406 if (t
> SEC_TONE_OFF
)
409 ret
= mt312_readreg(state
, DISEQC_MODE
, &diseqc_mode
);
413 ret
= mt312_writereg(state
, DISEQC_MODE
,
414 (diseqc_mode
& 0x40) | tone_tab
[t
]);
421 static int mt312_set_voltage(struct dvb_frontend
*fe
, const fe_sec_voltage_t v
)
423 struct mt312_state
*state
= fe
->demodulator_priv
;
424 const u8 volt_tab
[3] = { 0x00, 0x40, 0x00 };
427 if (v
> SEC_VOLTAGE_OFF
)
431 if (state
->config
->voltage_inverted
)
434 return mt312_writereg(state
, DISEQC_MODE
, val
);
437 static int mt312_read_status(struct dvb_frontend
*fe
, fe_status_t
*s
)
439 struct mt312_state
*state
= fe
->demodulator_priv
;
445 ret
= mt312_read(state
, QPSK_STAT_H
, status
, sizeof(status
));
449 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
450 " FEC_STATUS: 0x%02x\n", status
[0], status
[1], status
[2]);
452 if (status
[0] & 0xc0)
453 *s
|= FE_HAS_SIGNAL
; /* signal noise ratio */
454 if (status
[0] & 0x04)
455 *s
|= FE_HAS_CARRIER
; /* qpsk carrier lock */
456 if (status
[2] & 0x02)
457 *s
|= FE_HAS_VITERBI
; /* viterbi lock */
458 if (status
[2] & 0x04)
459 *s
|= FE_HAS_SYNC
; /* byte align lock */
460 if (status
[0] & 0x01)
461 *s
|= FE_HAS_LOCK
; /* qpsk lock */
466 static int mt312_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
468 struct mt312_state
*state
= fe
->demodulator_priv
;
472 ret
= mt312_read(state
, RS_BERCNT_H
, buf
, 3);
476 *ber
= ((buf
[0] << 16) | (buf
[1] << 8) | buf
[2]) * 64;
481 static int mt312_read_signal_strength(struct dvb_frontend
*fe
,
482 u16
*signal_strength
)
484 struct mt312_state
*state
= fe
->demodulator_priv
;
490 ret
= mt312_read(state
, AGC_H
, buf
, sizeof(buf
));
494 agc
= (buf
[0] << 6) | (buf
[1] >> 2);
495 err_db
= (s16
) (((buf
[1] & 0x03) << 14) | buf
[2] << 6) >> 6;
497 *signal_strength
= agc
;
499 dprintk("agc=%08x err_db=%hd\n", agc
, err_db
);
504 static int mt312_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
506 struct mt312_state
*state
= fe
->demodulator_priv
;
510 ret
= mt312_read(state
, M_SNR_H
, buf
, sizeof(buf
));
514 *snr
= 0xFFFF - ((((buf
[0] & 0x7f) << 8) | buf
[1]) << 1);
519 static int mt312_read_ucblocks(struct dvb_frontend
*fe
, u32
*ubc
)
521 struct mt312_state
*state
= fe
->demodulator_priv
;
525 ret
= mt312_read(state
, RS_UBC_H
, buf
, sizeof(buf
));
529 *ubc
= (buf
[0] << 8) | buf
[1];
534 static int mt312_set_frontend(struct dvb_frontend
*fe
)
536 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
537 struct mt312_state
*state
= fe
->demodulator_priv
;
539 u8 buf
[5], config_val
;
542 const u8 fec_tab
[10] =
543 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
544 const u8 inv_tab
[3] = { 0x00, 0x40, 0x80 };
546 dprintk("%s: Freq %d\n", __func__
, p
->frequency
);
548 if ((p
->frequency
< fe
->ops
.info
.frequency_min
)
549 || (p
->frequency
> fe
->ops
.info
.frequency_max
))
552 if (((int)p
->inversion
< INVERSION_OFF
)
553 || (p
->inversion
> INVERSION_ON
))
556 if ((p
->symbol_rate
< fe
->ops
.info
.symbol_rate_min
)
557 || (p
->symbol_rate
> fe
->ops
.info
.symbol_rate_max
))
560 if (((int)p
->fec_inner
< FEC_NONE
)
561 || (p
->fec_inner
> FEC_AUTO
))
564 if ((p
->fec_inner
== FEC_4_5
)
565 || (p
->fec_inner
== FEC_8_9
))
570 /* For now we will do this only for the VP310.
571 * It should be better for the mt312 as well,
572 * but tuning will be slower. ACCJr 09/29/03
574 ret
= mt312_readreg(state
, CONFIG
, &config_val
);
577 if (p
->symbol_rate
>= 30000000) {
578 /* Note that 30MS/s should use 90MHz */
579 if (state
->freq_mult
== 6) {
580 /* We are running 60MHz */
581 state
->freq_mult
= 9;
582 ret
= mt312_initfe(fe
);
587 if (state
->freq_mult
== 9) {
588 /* We are running 90MHz */
589 state
->freq_mult
= 6;
590 ret
= mt312_initfe(fe
);
605 if (fe
->ops
.tuner_ops
.set_params
) {
606 fe
->ops
.tuner_ops
.set_params(fe
);
607 if (fe
->ops
.i2c_gate_ctrl
)
608 fe
->ops
.i2c_gate_ctrl(fe
, 0);
611 /* sr = (u16)(sr * 256.0 / 1000000.0) */
612 sr
= mt312_div(p
->symbol_rate
* 4, 15625);
615 buf
[0] = (sr
>> 8) & 0x3f;
616 buf
[1] = (sr
>> 0) & 0xff;
619 buf
[2] = inv_tab
[p
->inversion
] | fec_tab
[p
->fec_inner
];
622 buf
[3] = 0x40; /* swap I and Q before QPSK demodulation */
624 if (p
->symbol_rate
< 10000000)
625 buf
[3] |= 0x04; /* use afc mode */
630 ret
= mt312_write(state
, SYM_RATE_H
, buf
, sizeof(buf
));
634 mt312_reset(state
, 0);
639 static int mt312_get_frontend(struct dvb_frontend
*fe
)
641 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
642 struct mt312_state
*state
= fe
->demodulator_priv
;
645 ret
= mt312_get_inversion(state
, &p
->inversion
);
649 ret
= mt312_get_symbol_rate(state
, &p
->symbol_rate
);
653 ret
= mt312_get_code_rate(state
, &p
->fec_inner
);
660 static int mt312_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
662 struct mt312_state
*state
= fe
->demodulator_priv
;
669 ret
= mt312_readreg(state
, GPP_CTRL
, &val
);
673 /* preserve this bit to not accidentally shutdown ADC */
683 ret
= mt312_writereg(state
, GPP_CTRL
, val
);
689 static int mt312_sleep(struct dvb_frontend
*fe
)
691 struct mt312_state
*state
= fe
->demodulator_priv
;
695 /* reset all registers to defaults */
696 ret
= mt312_reset(state
, 1);
700 if (state
->id
== ID_ZL10313
) {
702 ret
= mt312_writereg(state
, GPP_CTRL
, 0x00);
706 /* full shutdown of ADCs, mpeg bus tristated */
707 ret
= mt312_writereg(state
, HW_CTRL
, 0x0d);
712 ret
= mt312_readreg(state
, CONFIG
, &config
);
717 ret
= mt312_writereg(state
, CONFIG
, config
& 0x7f);
724 static int mt312_get_tune_settings(struct dvb_frontend
*fe
,
725 struct dvb_frontend_tune_settings
*fesettings
)
727 fesettings
->min_delay_ms
= 50;
728 fesettings
->step_size
= 0;
729 fesettings
->max_drift
= 0;
733 static void mt312_release(struct dvb_frontend
*fe
)
735 struct mt312_state
*state
= fe
->demodulator_priv
;
739 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
740 static struct dvb_frontend_ops mt312_ops
= {
741 .delsys
= { SYS_DVBS
},
743 .name
= "Zarlink ???? DVB-S",
744 .frequency_min
= 950000,
745 .frequency_max
= 2150000,
746 /* FIXME: adjust freq to real used xtal */
747 .frequency_stepsize
= (MT312_PLL_CLK
/ 1000) / 128,
748 .symbol_rate_min
= MT312_SYS_CLK
/ 128, /* FIXME as above */
749 .symbol_rate_max
= MT312_SYS_CLK
/ 2,
751 FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
|
752 FE_CAN_FEC_3_4
| FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
|
753 FE_CAN_FEC_AUTO
| FE_CAN_QPSK
| FE_CAN_MUTE_TS
|
757 .release
= mt312_release
,
759 .init
= mt312_initfe
,
760 .sleep
= mt312_sleep
,
761 .i2c_gate_ctrl
= mt312_i2c_gate_ctrl
,
763 .set_frontend
= mt312_set_frontend
,
764 .get_frontend
= mt312_get_frontend
,
765 .get_tune_settings
= mt312_get_tune_settings
,
767 .read_status
= mt312_read_status
,
768 .read_ber
= mt312_read_ber
,
769 .read_signal_strength
= mt312_read_signal_strength
,
770 .read_snr
= mt312_read_snr
,
771 .read_ucblocks
= mt312_read_ucblocks
,
773 .diseqc_send_master_cmd
= mt312_send_master_cmd
,
774 .diseqc_send_burst
= mt312_send_burst
,
775 .set_tone
= mt312_set_tone
,
776 .set_voltage
= mt312_set_voltage
,
779 struct dvb_frontend
*mt312_attach(const struct mt312_config
*config
,
780 struct i2c_adapter
*i2c
)
782 struct mt312_state
*state
= NULL
;
784 /* allocate memory for the internal state */
785 state
= kzalloc(sizeof(struct mt312_state
), GFP_KERNEL
);
789 /* setup the state */
790 state
->config
= config
;
793 /* check if the demod is there */
794 if (mt312_readreg(state
, ID
, &state
->id
) < 0)
797 /* create dvb_frontend */
798 memcpy(&state
->frontend
.ops
, &mt312_ops
,
799 sizeof(struct dvb_frontend_ops
));
800 state
->frontend
.demodulator_priv
= state
;
804 strcpy(state
->frontend
.ops
.info
.name
, "Zarlink VP310 DVB-S");
805 state
->xtal
= MT312_PLL_CLK
;
806 state
->freq_mult
= 9;
809 strcpy(state
->frontend
.ops
.info
.name
, "Zarlink MT312 DVB-S");
810 state
->xtal
= MT312_PLL_CLK
;
811 state
->freq_mult
= 6;
814 strcpy(state
->frontend
.ops
.info
.name
, "Zarlink ZL10313 DVB-S");
815 state
->xtal
= MT312_PLL_CLK_10_111
;
816 state
->freq_mult
= 9;
819 printk(KERN_WARNING
"Only Zarlink VP310/MT312/ZL10313"
820 " are supported chips.\n");
824 return &state
->frontend
;
830 EXPORT_SYMBOL(mt312_attach
);
832 module_param(debug
, int, 0644);
833 MODULE_PARM_DESC(debug
, "Turn on/off frontend debugging (default:off).");
835 MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
836 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
837 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
838 MODULE_LICENSE("GPL");