drivers/media/dvb-frontends/mt352.c

   1 /*
   2  *  Driver for Zarlink DVB-T MT352 demodulator
   3  *
   4  *  Written by Holger Waechtler <holger@qanu.de>
   5  *       and Daniel Mack <daniel@qanu.de>
   6  *
   7  *  AVerMedia AVerTV DVB-T 771 support by
   8  *       Wolfram Joost <dbox2@frokaschwei.de>
   9  *
  10  *  Support for Samsung TDTC9251DH01C(M) tuner
  11  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
  12  *                     Amauri  Celani  <acelani@essegi.net>
  13  *
  14  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
  15  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *
  26  *  GNU General Public License for more details.
  27  */
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/string.h>
  34 #include <linux/slab.h>
  35
  36 #include "dvb_frontend.h"
  37 #include "mt352_priv.h"
  38 #include "mt352.h"
  39
  40 struct mt352_state {
  41         struct i2c_adapter* i2c;
  42         struct dvb_frontend frontend;
  43
  44         /* configuration settings */
  45         struct mt352_config config;
  46 };
  47
  48 static int debug;
  49 #define dprintk(args...) \
  50         do { \
  51                 if (debug) printk(KERN_DEBUG "mt352: " args); \
  52         } while (0)
  53
  54 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
  55 {
  56         struct mt352_state* state = fe->demodulator_priv;
  57         u8 buf[2] = { reg, val };
  58         struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
  59                                .buf = buf, .len = 2 };
  60         int err = i2c_transfer(state->i2c, &msg, 1);
  61         if (err != 1) {
  62                 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
  63                 return err;
  64         }
  65         return 0;
  66 }
  67
  68 static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
  69 {
  70         int err,i;
  71         for (i=0; i < ilen-1; i++)
  72                 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
  73                         return err;
  74
  75         return 0;
  76 }
  77
  78 static int mt352_read_register(struct mt352_state* state, u8 reg)
  79 {
  80         int ret;
  81         u8 b0 [] = { reg };
  82         u8 b1 [] = { 0 };
  83         struct i2c_msg msg [] = { { .addr = state->config.demod_address,
  84                                     .flags = 0,
  85                                     .buf = b0, .len = 1 },
  86                                   { .addr = state->config.demod_address,
  87                                     .flags = I2C_M_RD,
  88                                     .buf = b1, .len = 1 } };
  89
  90         ret = i2c_transfer(state->i2c, msg, 2);
  91
  92         if (ret != 2) {
  93                 printk("%s: readreg error (reg=%d, ret==%i)\n",
  94                        __func__, reg, ret);
  95                 return ret;
  96         }
  97
  98         return b1[0];
  99 }
 100
 101 static int mt352_sleep(struct dvb_frontend* fe)
 102 {
 103         static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
 104
 105         _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
 106         return 0;
 107 }
 108
 109 static void mt352_calc_nominal_rate(struct mt352_state* state,
 110                                     u32 bandwidth,
 111                                     unsigned char *buf)
 112 {
 113         u32 adc_clock = 20480; /* 20.340 MHz */
 114         u32 bw,value;
 115
 116         switch (bandwidth) {
 117         case 6000000:
 118                 bw = 6;
 119                 break;
 120         case 7000000:
 121                 bw = 7;
 122                 break;
 123         case 8000000:
 124         default:
 125                 bw = 8;
 126                 break;
 127         }
 128         if (state->config.adc_clock)
 129                 adc_clock = state->config.adc_clock;
 130
 131         value = 64 * bw * (1<<16) / (7 * 8);
 132         value = value * 1000 / adc_clock;
 133         dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
 134                 __func__, bw, adc_clock, value);
 135         buf[0] = msb(value);
 136         buf[1] = lsb(value);
 137 }
 138
 139 static void mt352_calc_input_freq(struct mt352_state* state,
 140                                   unsigned char *buf)
 141 {
 142         int adc_clock = 20480; /* 20.480000 MHz */
 143         int if2       = 36167; /* 36.166667 MHz */
 144         int ife,value;
 145
 146         if (state->config.adc_clock)
 147                 adc_clock = state->config.adc_clock;
 148         if (state->config.if2)
 149                 if2 = state->config.if2;
 150
 151         if (adc_clock >= if2 * 2)
 152                 ife = if2;
 153         else {
 154                 ife = adc_clock - (if2 % adc_clock);
 155                 if (ife > adc_clock / 2)
 156                         ife = adc_clock - ife;
 157         }
 158         value = -16374 * ife / adc_clock;
 159         dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
 160                 __func__, if2, ife, adc_clock, value, value & 0x3fff);
 161         buf[0] = msb(value);
 162         buf[1] = lsb(value);
 163 }
 164
 165 static int mt352_set_parameters(struct dvb_frontend *fe)
 166 {
 167         struct dtv_frontend_properties *op = &fe->dtv_property_cache;
 168         struct mt352_state* state = fe->demodulator_priv;
 169         unsigned char buf[13];
 170         static unsigned char tuner_go[] = { 0x5d, 0x01 };
 171         static unsigned char fsm_go[]   = { 0x5e, 0x01 };
 172         unsigned int tps = 0;
 173
 174         switch (op->code_rate_HP) {
 175                 case FEC_2_3:
 176                         tps |= (1 << 7);
 177                         break;
 178                 case FEC_3_4:
 179                         tps |= (2 << 7);
 180                         break;
 181                 case FEC_5_6:
 182                         tps |= (3 << 7);
 183                         break;
 184                 case FEC_7_8:
 185                         tps |= (4 << 7);
 186                         break;
 187                 case FEC_1_2:
 188                 case FEC_AUTO:
 189                         break;
 190                 default:
 191                         return -EINVAL;
 192         }
 193
 194         switch (op->code_rate_LP) {
 195                 case FEC_2_3:
 196                         tps |= (1 << 4);
 197                         break;
 198                 case FEC_3_4:
 199                         tps |= (2 << 4);
 200                         break;
 201                 case FEC_5_6:
 202                         tps |= (3 << 4);
 203                         break;
 204                 case FEC_7_8:
 205                         tps |= (4 << 4);
 206                         break;
 207                 case FEC_1_2:
 208                 case FEC_AUTO:
 209                         break;
 210                 case FEC_NONE:
 211                         if (op->hierarchy == HIERARCHY_AUTO ||
 212                             op->hierarchy == HIERARCHY_NONE)
 213                                 break;
 214                 default:
 215                         return -EINVAL;
 216         }
 217
 218         switch (op->modulation) {
 219                 case QPSK:
 220                         break;
 221                 case QAM_AUTO:
 222                 case QAM_16:
 223                         tps |= (1 << 13);
 224                         break;
 225                 case QAM_64:
 226                         tps |= (2 << 13);
 227                         break;
 228                 default:
 229                         return -EINVAL;
 230         }
 231
 232         switch (op->transmission_mode) {
 233                 case TRANSMISSION_MODE_2K:
 234                 case TRANSMISSION_MODE_AUTO:
 235                         break;
 236                 case TRANSMISSION_MODE_8K:
 237                         tps |= (1 << 0);
 238                         break;
 239                 default:
 240                         return -EINVAL;
 241         }
 242
 243         switch (op->guard_interval) {
 244                 case GUARD_INTERVAL_1_32:
 245                 case GUARD_INTERVAL_AUTO:
 246                         break;
 247                 case GUARD_INTERVAL_1_16:
 248                         tps |= (1 << 2);
 249                         break;
 250                 case GUARD_INTERVAL_1_8:
 251                         tps |= (2 << 2);
 252                         break;
 253                 case GUARD_INTERVAL_1_4:
 254                         tps |= (3 << 2);
 255                         break;
 256                 default:
 257                         return -EINVAL;
 258         }
 259
 260         switch (op->hierarchy) {
 261                 case HIERARCHY_AUTO:
 262                 case HIERARCHY_NONE:
 263                         break;
 264                 case HIERARCHY_1:
 265                         tps |= (1 << 10);
 266                         break;
 267                 case HIERARCHY_2:
 268                         tps |= (2 << 10);
 269                         break;
 270                 case HIERARCHY_4:
 271                         tps |= (3 << 10);
 272                         break;
 273                 default:
 274                         return -EINVAL;
 275         }
 276
 277
 278         buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
 279
 280         buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
 281         buf[2] = lsb(tps);
 282
 283         buf[3] = 0x50;  // old
 284 //      buf[3] = 0xf4;  // pinnacle
 285
 286         mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
 287         mt352_calc_input_freq(state, buf+6);
 288
 289         if (state->config.no_tuner) {
 290                 if (fe->ops.tuner_ops.set_params) {
 291                         fe->ops.tuner_ops.set_params(fe);
 292                         if (fe->ops.i2c_gate_ctrl)
 293                                 fe->ops.i2c_gate_ctrl(fe, 0);
 294                 }
 295
 296                 _mt352_write(fe, buf, 8);
 297                 _mt352_write(fe, fsm_go, 2);
 298         } else {
 299                 if (fe->ops.tuner_ops.calc_regs) {
 300                         fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
 301                         buf[8] <<= 1;
 302                         _mt352_write(fe, buf, sizeof(buf));
 303                         _mt352_write(fe, tuner_go, 2);
 304                 }
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int mt352_get_parameters(struct dvb_frontend* fe,
 311                                 struct dtv_frontend_properties *op)
 312 {
 313         struct mt352_state* state = fe->demodulator_priv;
 314         u16 tps;
 315         u16 div;
 316         u8 trl;
 317         static const u8 tps_fec_to_api[8] =
 318         {
 319                 FEC_1_2,
 320                 FEC_2_3,
 321                 FEC_3_4,
 322                 FEC_5_6,
 323                 FEC_7_8,
 324                 FEC_AUTO,
 325                 FEC_AUTO,
 326                 FEC_AUTO
 327         };
 328
 329         if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
 330                 return -EINVAL;
 331
 332         /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
 333          * the mt352 sometimes works with the wrong parameters
 334          */
 335         tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
 336         div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
 337         trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
 338
 339         op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
 340         op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
 341
 342         switch ( (tps >> 13) & 3)
 343         {
 344                 case 0:
 345                         op->modulation = QPSK;
 346                         break;
 347                 case 1:
 348                         op->modulation = QAM_16;
 349                         break;
 350                 case 2:
 351                         op->modulation = QAM_64;
 352                         break;
 353                 default:
 354                         op->modulation = QAM_AUTO;
 355                         break;
 356         }
 357
 358         op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
 359
 360         switch ( (tps >> 2) & 3)
 361         {
 362                 case 0:
 363                         op->guard_interval = GUARD_INTERVAL_1_32;
 364                         break;
 365                 case 1:
 366                         op->guard_interval = GUARD_INTERVAL_1_16;
 367                         break;
 368                 case 2:
 369                         op->guard_interval = GUARD_INTERVAL_1_8;
 370                         break;
 371                 case 3:
 372                         op->guard_interval = GUARD_INTERVAL_1_4;
 373                         break;
 374                 default:
 375                         op->guard_interval = GUARD_INTERVAL_AUTO;
 376                         break;
 377         }
 378
 379         switch ( (tps >> 10) & 7)
 380         {
 381                 case 0:
 382                         op->hierarchy = HIERARCHY_NONE;
 383                         break;
 384                 case 1:
 385                         op->hierarchy = HIERARCHY_1;
 386                         break;
 387                 case 2:
 388                         op->hierarchy = HIERARCHY_2;
 389                         break;
 390                 case 3:
 391                         op->hierarchy = HIERARCHY_4;
 392                         break;
 393                 default:
 394                         op->hierarchy = HIERARCHY_AUTO;
 395                         break;
 396         }
 397
 398         op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
 399
 400         if (trl == 0x72)
 401                 op->bandwidth_hz = 8000000;
 402         else if (trl == 0x64)
 403                 op->bandwidth_hz = 7000000;
 404         else
 405                 op->bandwidth_hz = 6000000;
 406
 407
 408         if (mt352_read_register(state, STATUS_2) & 0x02)
 409                 op->inversion = INVERSION_OFF;
 410         else
 411                 op->inversion = INVERSION_ON;
 412
 413         return 0;
 414 }
 415
 416 static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
 417 {
 418         struct mt352_state* state = fe->demodulator_priv;
 419         int s0, s1, s3;
 420
 421         /* FIXME:
 422          *
 423          * The MT352 design manual from Zarlink states (page 46-47):
 424          *
 425          * Notes about the TUNER_GO register:
 426          *
 427          * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
 428          * byte is copied from the tuner to the STATUS_3 register and
 429          * completion of the read operation is indicated by bit-5 of the
 430          * INTERRUPT_3 register.
 431          */
 432
 433         if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
 434                 return -EREMOTEIO;
 435         if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
 436                 return -EREMOTEIO;
 437         if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
 438                 return -EREMOTEIO;
 439
 440         *status = 0;
 441         if (s0 & (1 << 4))
 442                 *status |= FE_HAS_CARRIER;
 443         if (s0 & (1 << 1))
 444                 *status |= FE_HAS_VITERBI;
 445         if (s0 & (1 << 5))
 446                 *status |= FE_HAS_LOCK;
 447         if (s1 & (1 << 1))
 448                 *status |= FE_HAS_SYNC;
 449         if (s3 & (1 << 6))
 450                 *status |= FE_HAS_SIGNAL;
 451
 452         if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
 453                       (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
 454                 *status &= ~FE_HAS_LOCK;
 455
 456         return 0;
 457 }
 458
 459 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
 460 {
 461         struct mt352_state* state = fe->demodulator_priv;
 462
 463         *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
 464                (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
 465                (mt352_read_register (state, RS_ERR_CNT_0));
 466
 467         return 0;
 468 }
 469
 470 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 471 {
 472         struct mt352_state* state = fe->demodulator_priv;
 473
 474         /* align the 12 bit AGC gain with the most significant bits */
 475         u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
 476                 (mt352_read_register(state, AGC_GAIN_0) << 4);
 477
 478         /* inverse of gain is signal strength */
 479         *strength = ~signal;
 480         return 0;
 481 }
 482
 483 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
 484 {
 485         struct mt352_state* state = fe->demodulator_priv;
 486
 487         u8 _snr = mt352_read_register (state, SNR);
 488         *snr = (_snr << 8) | _snr;
 489
 490         return 0;
 491 }
 492
 493 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 494 {
 495         struct mt352_state* state = fe->demodulator_priv;
 496
 497         *ucblocks = (mt352_read_register (state,  RS_UBC_1) << 8) |
 498                     (mt352_read_register (state,  RS_UBC_0));
 499
 500         return 0;
 501 }
 502
 503 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
 504 {
 505         fe_tune_settings->min_delay_ms = 800;
 506         fe_tune_settings->step_size = 0;
 507         fe_tune_settings->max_drift = 0;
 508
 509         return 0;
 510 }
 511
 512 static int mt352_init(struct dvb_frontend* fe)
 513 {
 514         struct mt352_state* state = fe->demodulator_priv;
 515
 516         static u8 mt352_reset_attach [] = { RESET, 0xC0 };
 517
 518         dprintk("%s: hello\n",__func__);
 519
 520         if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
 521             (mt352_read_register(state, CONFIG) & 0x20) == 0) {
 522
 523                 /* Do a "hard" reset */
 524                 _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
 525                 return state->config.demod_init(fe);
 526         }
 527
 528         return 0;
 529 }
 530
 531 static void mt352_release(struct dvb_frontend* fe)
 532 {
 533         struct mt352_state* state = fe->demodulator_priv;
 534         kfree(state);
 535 }
 536
 537 static const struct dvb_frontend_ops mt352_ops;
 538
 539 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
 540                                   struct i2c_adapter* i2c)
 541 {
 542         struct mt352_state* state = NULL;
 543
 544         /* allocate memory for the internal state */
 545         state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
 546         if (state == NULL) goto error;
 547
 548         /* setup the state */
 549         state->i2c = i2c;
 550         memcpy(&state->config,config,sizeof(struct mt352_config));
 551
 552         /* check if the demod is there */
 553         if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
 554
 555         /* create dvb_frontend */
 556         memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
 557         state->frontend.demodulator_priv = state;
 558         return &state->frontend;
 559
 560 error:
 561         kfree(state);
 562         return NULL;
 563 }
 564
 565 static const struct dvb_frontend_ops mt352_ops = {
 566         .delsys = { SYS_DVBT },
 567         .info = {
 568                 .name                   = "Zarlink MT352 DVB-T",
 569                 .frequency_min          = 174000000,
 570                 .frequency_max          = 862000000,
 571                 .frequency_stepsize     = 166667,
 572                 .frequency_tolerance    = 0,
 573                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 574                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 575                         FE_CAN_FEC_AUTO |
 576                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 577                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
 578                         FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
 579                         FE_CAN_MUTE_TS
 580         },
 581
 582         .release = mt352_release,
 583
 584         .init = mt352_init,
 585         .sleep = mt352_sleep,
 586         .write = _mt352_write,
 587
 588         .set_frontend = mt352_set_parameters,
 589         .get_frontend = mt352_get_parameters,
 590         .get_tune_settings = mt352_get_tune_settings,
 591
 592         .read_status = mt352_read_status,
 593         .read_ber = mt352_read_ber,
 594         .read_signal_strength = mt352_read_signal_strength,
 595         .read_snr = mt352_read_snr,
 596         .read_ucblocks = mt352_read_ucblocks,
 597 };
 598
 599 module_param(debug, int, 0644);
 600 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 601
 602 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
 603 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
 604 MODULE_LICENSE("GPL");
 605
 606 EXPORT_SYMBOL(mt352_attach);