]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/media/i2c/adv7842.c
projects / mirror_ubuntu-zesty-kernel.git / blob
? search:


dceabc29239a66eb14b09b75875890aaf6d39e2a
[mirror_ubuntu-zesty-kernel.git] / drivers / media / i2c / adv7842.c
1 /*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
30 */
31
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/i2c.h>
37 #include <linux/delay.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/v4l2-dv-timings.h>
41 #include <linux/hdmi.h>
42 #include <media/v4l2-device.h>
43 #include <media/v4l2-ctrls.h>
44 #include <media/v4l2-dv-timings.h>
45 #include <media/adv7842.h>
46
47 static int debug;
48 module_param(debug, int, 0644);
49 MODULE_PARM_DESC(debug, "debug level (0-2)");
50
51 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
52 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
53 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
54 MODULE_LICENSE("GPL");
55
56 /* ADV7842 system clock frequency */
57 #define ADV7842_fsc (28636360)
58
59 #define ADV7842_RGB_OUT (1 << 1)
60
61 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
62 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
63 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
64
65 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
66 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
67 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
68 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
69 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
70 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
71
72 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
73 #define ADV7842_OP_CH_SEL_GRB (1 << 5)
74 #define ADV7842_OP_CH_SEL_BGR (2 << 5)
75 #define ADV7842_OP_CH_SEL_RGB (3 << 5)
76 #define ADV7842_OP_CH_SEL_BRG (4 << 5)
77 #define ADV7842_OP_CH_SEL_RBG (5 << 5)
78
79 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
80
81 /*
82 **********************************************************************
83 *
84 * Arrays with configuration parameters for the ADV7842
85 *
86 **********************************************************************
87 */
88
89 struct adv7842_format_info {
90 u32 code;
91 u8 op_ch_sel;
92 bool rgb_out;
93 bool swap_cb_cr;
94 u8 op_format_sel;
95 };
96
97 struct adv7842_state {
98 struct adv7842_platform_data pdata;
99 struct v4l2_subdev sd;
100 struct media_pad pad;
101 struct v4l2_ctrl_handler hdl;
102 enum adv7842_mode mode;
103 struct v4l2_dv_timings timings;
104 enum adv7842_vid_std_select vid_std_select;
105
106 const struct adv7842_format_info *format;
107
108 v4l2_std_id norm;
109 struct {
110 u8 edid[256];
111 u32 present;
112 } hdmi_edid;
113 struct {
114 u8 edid[256];
115 u32 present;
116 } vga_edid;
117 struct v4l2_fract aspect_ratio;
118 u32 rgb_quantization_range;
119 bool is_cea_format;
120 struct workqueue_struct *work_queues;
121 struct delayed_work delayed_work_enable_hotplug;
122 bool restart_stdi_once;
123 bool hdmi_port_a;
124
125 /* i2c clients */
126 struct i2c_client *i2c_sdp_io;
127 struct i2c_client *i2c_sdp;
128 struct i2c_client *i2c_cp;
129 struct i2c_client *i2c_vdp;
130 struct i2c_client *i2c_afe;
131 struct i2c_client *i2c_hdmi;
132 struct i2c_client *i2c_repeater;
133 struct i2c_client *i2c_edid;
134 struct i2c_client *i2c_infoframe;
135 struct i2c_client *i2c_cec;
136 struct i2c_client *i2c_avlink;
137
138 /* controls */
139 struct v4l2_ctrl *detect_tx_5v_ctrl;
140 struct v4l2_ctrl *analog_sampling_phase_ctrl;
141 struct v4l2_ctrl *free_run_color_ctrl_manual;
142 struct v4l2_ctrl *free_run_color_ctrl;
143 struct v4l2_ctrl *rgb_quantization_range_ctrl;
144 };
145
146 /* Unsupported timings. This device cannot support 720p30. */
147 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
148 V4L2_DV_BT_CEA_1280X720P30,
149 { }
150 };
151
152 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
153 {
154 int i;
155
156 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
157 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
158 return false;
159 return true;
160 }
161
162 struct adv7842_video_standards {
163 struct v4l2_dv_timings timings;
164 u8 vid_std;
165 u8 v_freq;
166 };
167
168 /* sorted by number of lines */
169 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
170 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
171 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
172 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
173 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
174 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
175 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
176 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
177 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
178 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
179 /* TODO add 1920x1080P60_RB (CVT timing) */
180 { },
181 };
182
183 /* sorted by number of lines */
184 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
185 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
186 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
187 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
188 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
189 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
190 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
191 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
192 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
194 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
195 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
196 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
197 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
198 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
199 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
200 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
201 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
202 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
203 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
204 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
205 /* TODO add 1600X1200P60_RB (not a DMT timing) */
206 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
207 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
208 { },
209 };
210
211 /* sorted by number of lines */
212 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
213 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
214 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
215 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
216 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
217 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
218 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
219 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
220 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
221 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
222 { },
223 };
224
225 /* sorted by number of lines */
226 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
227 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
228 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
229 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
230 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
231 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
232 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
233 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
234 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
235 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
236 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
237 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
238 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
239 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
240 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
241 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
242 { },
243 };
244
245 /* ----------------------------------------------------------------------- */
246
247 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
248 {
249 return container_of(sd, struct adv7842_state, sd);
250 }
251
252 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
253 {
254 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
255 }
256
257 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
258 {
259 return V4L2_DV_BT_BLANKING_WIDTH(t);
260 }
261
262 static inline unsigned htotal(const struct v4l2_bt_timings *t)
263 {
264 return V4L2_DV_BT_FRAME_WIDTH(t);
265 }
266
267 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
268 {
269 return V4L2_DV_BT_BLANKING_HEIGHT(t);
270 }
271
272 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
273 {
274 return V4L2_DV_BT_FRAME_HEIGHT(t);
275 }
276
277
278 /* ----------------------------------------------------------------------- */
279
280 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
281 u8 command, bool check)
282 {
283 union i2c_smbus_data data;
284
285 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
286 I2C_SMBUS_READ, command,
287 I2C_SMBUS_BYTE_DATA, &data))
288 return data.byte;
289 if (check)
290 v4l_err(client, "error reading %02x, %02x\n",
291 client->addr, command);
292 return -EIO;
293 }
294
295 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
296 {
297 int i;
298
299 for (i = 0; i < 3; i++) {
300 int ret = adv_smbus_read_byte_data_check(client, command, true);
301
302 if (ret >= 0) {
303 if (i)
304 v4l_err(client, "read ok after %d retries\n", i);
305 return ret;
306 }
307 }
308 v4l_err(client, "read failed\n");
309 return -EIO;
310 }
311
312 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
313 u8 command, u8 value)
314 {
315 union i2c_smbus_data data;
316 int err;
317 int i;
318
319 data.byte = value;
320 for (i = 0; i < 3; i++) {
321 err = i2c_smbus_xfer(client->adapter, client->addr,
322 client->flags,
323 I2C_SMBUS_WRITE, command,
324 I2C_SMBUS_BYTE_DATA, &data);
325 if (!err)
326 break;
327 }
328 if (err < 0)
329 v4l_err(client, "error writing %02x, %02x, %02x\n",
330 client->addr, command, value);
331 return err;
332 }
333
334 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
335 u8 command, u8 value)
336 {
337 union i2c_smbus_data data;
338 data.byte = value;
339
340 i2c_smbus_xfer(client->adapter, client->addr,
341 client->flags,
342 I2C_SMBUS_WRITE, command,
343 I2C_SMBUS_BYTE_DATA, &data);
344 }
345
346 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
347 u8 command, unsigned length, const u8 *values)
348 {
349 union i2c_smbus_data data;
350
351 if (length > I2C_SMBUS_BLOCK_MAX)
352 length = I2C_SMBUS_BLOCK_MAX;
353 data.block[0] = length;
354 memcpy(data.block + 1, values, length);
355 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
356 I2C_SMBUS_WRITE, command,
357 I2C_SMBUS_I2C_BLOCK_DATA, &data);
358 }
359
360 /* ----------------------------------------------------------------------- */
361
362 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
363 {
364 struct i2c_client *client = v4l2_get_subdevdata(sd);
365
366 return adv_smbus_read_byte_data(client, reg);
367 }
368
369 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
370 {
371 struct i2c_client *client = v4l2_get_subdevdata(sd);
372
373 return adv_smbus_write_byte_data(client, reg, val);
374 }
375
376 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
377 {
378 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
379 }
380
381 static inline int io_write_clr_set(struct v4l2_subdev *sd,
382 u8 reg, u8 mask, u8 val)
383 {
384 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
385 }
386
387 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
388 {
389 struct adv7842_state *state = to_state(sd);
390
391 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
392 }
393
394 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
395 {
396 struct adv7842_state *state = to_state(sd);
397
398 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
399 }
400
401 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
402 {
403 struct adv7842_state *state = to_state(sd);
404
405 return adv_smbus_read_byte_data(state->i2c_cec, reg);
406 }
407
408 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
409 {
410 struct adv7842_state *state = to_state(sd);
411
412 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
413 }
414
415 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
416 {
417 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
418 }
419
420 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
421 {
422 struct adv7842_state *state = to_state(sd);
423
424 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
425 }
426
427 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
428 {
429 struct adv7842_state *state = to_state(sd);
430
431 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
432 }
433
434 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
435 {
436 struct adv7842_state *state = to_state(sd);
437
438 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
439 }
440
441 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
442 {
443 struct adv7842_state *state = to_state(sd);
444
445 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
446 }
447
448 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
449 {
450 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
451 }
452
453 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
454 {
455 struct adv7842_state *state = to_state(sd);
456
457 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
458 }
459
460 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
461 {
462 struct adv7842_state *state = to_state(sd);
463
464 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
465 }
466
467 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
468 {
469 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
470 }
471
472 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
473 {
474 struct adv7842_state *state = to_state(sd);
475
476 return adv_smbus_read_byte_data(state->i2c_afe, reg);
477 }
478
479 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
480 {
481 struct adv7842_state *state = to_state(sd);
482
483 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
484 }
485
486 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
487 {
488 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
489 }
490
491 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
492 {
493 struct adv7842_state *state = to_state(sd);
494
495 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
496 }
497
498 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
499 {
500 struct adv7842_state *state = to_state(sd);
501
502 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
503 }
504
505 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
506 {
507 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
508 }
509
510 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
511 {
512 struct adv7842_state *state = to_state(sd);
513
514 return adv_smbus_read_byte_data(state->i2c_edid, reg);
515 }
516
517 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
518 {
519 struct adv7842_state *state = to_state(sd);
520
521 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
522 }
523
524 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
525 {
526 struct adv7842_state *state = to_state(sd);
527
528 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
529 }
530
531 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
532 {
533 struct adv7842_state *state = to_state(sd);
534
535 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
536 }
537
538 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
539 {
540 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
541 }
542
543 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
544 {
545 struct adv7842_state *state = to_state(sd);
546
547 return adv_smbus_read_byte_data(state->i2c_cp, reg);
548 }
549
550 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
551 {
552 struct adv7842_state *state = to_state(sd);
553
554 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
555 }
556
557 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
558 {
559 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
560 }
561
562 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
563 {
564 struct adv7842_state *state = to_state(sd);
565
566 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
567 }
568
569 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
570 {
571 struct adv7842_state *state = to_state(sd);
572
573 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
574 }
575
576 static void main_reset(struct v4l2_subdev *sd)
577 {
578 struct i2c_client *client = v4l2_get_subdevdata(sd);
579
580 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
581
582 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
583
584 mdelay(5);
585 }
586
587 /* -----------------------------------------------------------------------------
588 * Format helpers
589 */
590
591 static const struct adv7842_format_info adv7842_formats[] = {
592 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
593 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
594 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
595 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
596 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
597 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
598 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
599 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
600 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
601 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
602 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
603 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
604 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
605 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
606 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
607 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
608 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
609 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
610 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
611 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
612 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
613 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
614 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
615 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
616 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
617 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
618 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
619 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
620 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
621 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
622 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
623 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
624 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
625 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
626 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
627 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
628 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
629 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
630 };
631
632 static const struct adv7842_format_info *
633 adv7842_format_info(struct adv7842_state *state, u32 code)
634 {
635 unsigned int i;
636
637 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
638 if (adv7842_formats[i].code == code)
639 return &adv7842_formats[i];
640 }
641
642 return NULL;
643 }
644
645 /* ----------------------------------------------------------------------- */
646
647 static inline bool is_analog_input(struct v4l2_subdev *sd)
648 {
649 struct adv7842_state *state = to_state(sd);
650
651 return ((state->mode == ADV7842_MODE_RGB) ||
652 (state->mode == ADV7842_MODE_COMP));
653 }
654
655 static inline bool is_digital_input(struct v4l2_subdev *sd)
656 {
657 struct adv7842_state *state = to_state(sd);
658
659 return state->mode == ADV7842_MODE_HDMI;
660 }
661
662 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
663 .type = V4L2_DV_BT_656_1120,
664 /* keep this initialization for compatibility with GCC < 4.4.6 */
665 .reserved = { 0 },
666 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
667 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
668 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
669 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
670 V4L2_DV_BT_CAP_CUSTOM)
671 };
672
673 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
674 .type = V4L2_DV_BT_656_1120,
675 /* keep this initialization for compatibility with GCC < 4.4.6 */
676 .reserved = { 0 },
677 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
678 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
679 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
680 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
681 V4L2_DV_BT_CAP_CUSTOM)
682 };
683
684 static inline const struct v4l2_dv_timings_cap *
685 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
686 {
687 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
688 &adv7842_timings_cap_analog;
689 }
690
691 /* ----------------------------------------------------------------------- */
692
693 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
694 {
695 struct delayed_work *dwork = to_delayed_work(work);
696 struct adv7842_state *state = container_of(dwork,
697 struct adv7842_state, delayed_work_enable_hotplug);
698 struct v4l2_subdev *sd = &state->sd;
699 int present = state->hdmi_edid.present;
700 u8 mask = 0;
701
702 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
703 __func__, present);
704
705 if (present & (0x04 << ADV7842_EDID_PORT_A))
706 mask |= 0x20;
707 if (present & (0x04 << ADV7842_EDID_PORT_B))
708 mask |= 0x10;
709 io_write_and_or(sd, 0x20, 0xcf, mask);
710 }
711
712 static int edid_write_vga_segment(struct v4l2_subdev *sd)
713 {
714 struct i2c_client *client = v4l2_get_subdevdata(sd);
715 struct adv7842_state *state = to_state(sd);
716 const u8 *val = state->vga_edid.edid;
717 int err = 0;
718 int i;
719
720 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
721
722 /* HPA disable on port A and B */
723 io_write_and_or(sd, 0x20, 0xcf, 0x00);
724
725 /* Disable I2C access to internal EDID ram from VGA DDC port */
726 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
727
728 /* edid segment pointer '1' for VGA port */
729 rep_write_and_or(sd, 0x77, 0xef, 0x10);
730
731 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
732 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
733 I2C_SMBUS_BLOCK_MAX, val + i);
734 if (err)
735 return err;
736
737 /* Calculates the checksums and enables I2C access
738 * to internal EDID ram from VGA DDC port.
739 */
740 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
741
742 for (i = 0; i < 1000; i++) {
743 if (rep_read(sd, 0x79) & 0x20)
744 break;
745 mdelay(1);
746 }
747 if (i == 1000) {
748 v4l_err(client, "error enabling edid on VGA port\n");
749 return -EIO;
750 }
751
752 /* enable hotplug after 200 ms */
753 queue_delayed_work(state->work_queues,
754 &state->delayed_work_enable_hotplug, HZ / 5);
755
756 return 0;
757 }
758
759 static int edid_spa_location(const u8 *edid)
760 {
761 u8 d;
762
763 /*
764 * TODO, improve and update for other CEA extensions
765 * currently only for 1 segment (256 bytes),
766 * i.e. 1 extension block and CEA revision 3.
767 */
768 if ((edid[0x7e] != 1) ||
769 (edid[0x80] != 0x02) ||
770 (edid[0x81] != 0x03)) {
771 return -EINVAL;
772 }
773 /*
774 * search Vendor Specific Data Block (tag 3)
775 */
776 d = edid[0x82] & 0x7f;
777 if (d > 4) {
778 int i = 0x84;
779 int end = 0x80 + d;
780 do {
781 u8 tag = edid[i]>>5;
782 u8 len = edid[i] & 0x1f;
783
784 if ((tag == 3) && (len >= 5))
785 return i + 4;
786 i += len + 1;
787 } while (i < end);
788 }
789 return -EINVAL;
790 }
791
792 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
793 {
794 struct i2c_client *client = v4l2_get_subdevdata(sd);
795 struct adv7842_state *state = to_state(sd);
796 const u8 *val = state->hdmi_edid.edid;
797 int spa_loc = edid_spa_location(val);
798 int err = 0;
799 int i;
800
801 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
802 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
803
804 /* HPA disable on port A and B */
805 io_write_and_or(sd, 0x20, 0xcf, 0x00);
806
807 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
808 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
809
810 if (!state->hdmi_edid.present)
811 return 0;
812
813 /* edid segment pointer '0' for HDMI ports */
814 rep_write_and_or(sd, 0x77, 0xef, 0x00);
815
816 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
817 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
818 I2C_SMBUS_BLOCK_MAX, val + i);
819 if (err)
820 return err;
821
822 if (spa_loc < 0)
823 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
824
825 if (port == ADV7842_EDID_PORT_A) {
826 rep_write(sd, 0x72, val[spa_loc]);
827 rep_write(sd, 0x73, val[spa_loc + 1]);
828 } else {
829 rep_write(sd, 0x74, val[spa_loc]);
830 rep_write(sd, 0x75, val[spa_loc + 1]);
831 }
832 rep_write(sd, 0x76, spa_loc & 0xff);
833 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
834
835 /* Calculates the checksums and enables I2C access to internal
836 * EDID ram from HDMI DDC ports
837 */
838 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
839
840 for (i = 0; i < 1000; i++) {
841 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
842 break;
843 mdelay(1);
844 }
845 if (i == 1000) {
846 v4l_err(client, "error enabling edid on port %c\n",
847 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
848 return -EIO;
849 }
850
851 /* enable hotplug after 200 ms */
852 queue_delayed_work(state->work_queues,
853 &state->delayed_work_enable_hotplug, HZ / 5);
854
855 return 0;
856 }
857
858 /* ----------------------------------------------------------------------- */
859
860 #ifdef CONFIG_VIDEO_ADV_DEBUG
861 static void adv7842_inv_register(struct v4l2_subdev *sd)
862 {
863 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
864 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
865 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
866 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
867 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
868 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
869 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
870 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
871 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
872 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
873 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
874 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
875 }
876
877 static int adv7842_g_register(struct v4l2_subdev *sd,
878 struct v4l2_dbg_register *reg)
879 {
880 reg->size = 1;
881 switch (reg->reg >> 8) {
882 case 0:
883 reg->val = io_read(sd, reg->reg & 0xff);
884 break;
885 case 1:
886 reg->val = avlink_read(sd, reg->reg & 0xff);
887 break;
888 case 2:
889 reg->val = cec_read(sd, reg->reg & 0xff);
890 break;
891 case 3:
892 reg->val = infoframe_read(sd, reg->reg & 0xff);
893 break;
894 case 4:
895 reg->val = sdp_io_read(sd, reg->reg & 0xff);
896 break;
897 case 5:
898 reg->val = sdp_read(sd, reg->reg & 0xff);
899 break;
900 case 6:
901 reg->val = afe_read(sd, reg->reg & 0xff);
902 break;
903 case 7:
904 reg->val = rep_read(sd, reg->reg & 0xff);
905 break;
906 case 8:
907 reg->val = edid_read(sd, reg->reg & 0xff);
908 break;
909 case 9:
910 reg->val = hdmi_read(sd, reg->reg & 0xff);
911 break;
912 case 0xa:
913 reg->val = cp_read(sd, reg->reg & 0xff);
914 break;
915 case 0xb:
916 reg->val = vdp_read(sd, reg->reg & 0xff);
917 break;
918 default:
919 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
920 adv7842_inv_register(sd);
921 break;
922 }
923 return 0;
924 }
925
926 static int adv7842_s_register(struct v4l2_subdev *sd,
927 const struct v4l2_dbg_register *reg)
928 {
929 u8 val = reg->val & 0xff;
930
931 switch (reg->reg >> 8) {
932 case 0:
933 io_write(sd, reg->reg & 0xff, val);
934 break;
935 case 1:
936 avlink_write(sd, reg->reg & 0xff, val);
937 break;
938 case 2:
939 cec_write(sd, reg->reg & 0xff, val);
940 break;
941 case 3:
942 infoframe_write(sd, reg->reg & 0xff, val);
943 break;
944 case 4:
945 sdp_io_write(sd, reg->reg & 0xff, val);
946 break;
947 case 5:
948 sdp_write(sd, reg->reg & 0xff, val);
949 break;
950 case 6:
951 afe_write(sd, reg->reg & 0xff, val);
952 break;
953 case 7:
954 rep_write(sd, reg->reg & 0xff, val);
955 break;
956 case 8:
957 edid_write(sd, reg->reg & 0xff, val);
958 break;
959 case 9:
960 hdmi_write(sd, reg->reg & 0xff, val);
961 break;
962 case 0xa:
963 cp_write(sd, reg->reg & 0xff, val);
964 break;
965 case 0xb:
966 vdp_write(sd, reg->reg & 0xff, val);
967 break;
968 default:
969 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
970 adv7842_inv_register(sd);
971 break;
972 }
973 return 0;
974 }
975 #endif
976
977 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
978 {
979 struct adv7842_state *state = to_state(sd);
980 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
981 u8 reg_io_6f = io_read(sd, 0x6f);
982 int val = 0;
983
984 if (reg_io_6f & 0x02)
985 val |= 1; /* port A */
986 if (reg_io_6f & 0x01)
987 val |= 2; /* port B */
988
989 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
990
991 if (val != prev)
992 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
993 return 0;
994 }
995
996 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
997 u8 prim_mode,
998 const struct adv7842_video_standards *predef_vid_timings,
999 const struct v4l2_dv_timings *timings)
1000 {
1001 int i;
1002
1003 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
1004 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
1005 is_digital_input(sd) ? 250000 : 1000000))
1006 continue;
1007 /* video std */
1008 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
1009 /* v_freq and prim mode */
1010 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
1011 return 0;
1012 }
1013
1014 return -1;
1015 }
1016
1017 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
1018 struct v4l2_dv_timings *timings)
1019 {
1020 struct adv7842_state *state = to_state(sd);
1021 int err;
1022
1023 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1024
1025 /* reset to default values */
1026 io_write(sd, 0x16, 0x43);
1027 io_write(sd, 0x17, 0x5a);
1028 /* disable embedded syncs for auto graphics mode */
1029 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1030 cp_write(sd, 0x26, 0x00);
1031 cp_write(sd, 0x27, 0x00);
1032 cp_write(sd, 0x28, 0x00);
1033 cp_write(sd, 0x29, 0x00);
1034 cp_write(sd, 0x8f, 0x40);
1035 cp_write(sd, 0x90, 0x00);
1036 cp_write(sd, 0xa5, 0x00);
1037 cp_write(sd, 0xa6, 0x00);
1038 cp_write(sd, 0xa7, 0x00);
1039 cp_write(sd, 0xab, 0x00);
1040 cp_write(sd, 0xac, 0x00);
1041
1042 switch (state->mode) {
1043 case ADV7842_MODE_COMP:
1044 case ADV7842_MODE_RGB:
1045 err = find_and_set_predefined_video_timings(sd,
1046 0x01, adv7842_prim_mode_comp, timings);
1047 if (err)
1048 err = find_and_set_predefined_video_timings(sd,
1049 0x02, adv7842_prim_mode_gr, timings);
1050 break;
1051 case ADV7842_MODE_HDMI:
1052 err = find_and_set_predefined_video_timings(sd,
1053 0x05, adv7842_prim_mode_hdmi_comp, timings);
1054 if (err)
1055 err = find_and_set_predefined_video_timings(sd,
1056 0x06, adv7842_prim_mode_hdmi_gr, timings);
1057 break;
1058 default:
1059 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1060 __func__, state->mode);
1061 err = -1;
1062 break;
1063 }
1064
1065
1066 return err;
1067 }
1068
1069 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1070 const struct v4l2_bt_timings *bt)
1071 {
1072 struct adv7842_state *state = to_state(sd);
1073 struct i2c_client *client = v4l2_get_subdevdata(sd);
1074 u32 width = htotal(bt);
1075 u32 height = vtotal(bt);
1076 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1077 u16 cp_start_eav = width - bt->hfrontporch;
1078 u16 cp_start_vbi = height - bt->vfrontporch + 1;
1079 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1080 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1081 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1082 const u8 pll[2] = {
1083 0xc0 | ((width >> 8) & 0x1f),
1084 width & 0xff
1085 };
1086
1087 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1088
1089 switch (state->mode) {
1090 case ADV7842_MODE_COMP:
1091 case ADV7842_MODE_RGB:
1092 /* auto graphics */
1093 io_write(sd, 0x00, 0x07); /* video std */
1094 io_write(sd, 0x01, 0x02); /* prim mode */
1095 /* enable embedded syncs for auto graphics mode */
1096 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1097
1098 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1099 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1100 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1101 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1102 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1103 break;
1104 }
1105
1106 /* active video - horizontal timing */
1107 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1108 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1109 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1110 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1111
1112 /* active video - vertical timing */
1113 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1114 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1115 ((cp_end_vbi >> 8) & 0xf));
1116 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1117 break;
1118 case ADV7842_MODE_HDMI:
1119 /* set default prim_mode/vid_std for HDMI
1120 according to [REF_03, c. 4.2] */
1121 io_write(sd, 0x00, 0x02); /* video std */
1122 io_write(sd, 0x01, 0x06); /* prim mode */
1123 break;
1124 default:
1125 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1126 __func__, state->mode);
1127 break;
1128 }
1129
1130 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1131 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1132 cp_write(sd, 0xab, (height >> 4) & 0xff);
1133 cp_write(sd, 0xac, (height & 0x0f) << 4);
1134 }
1135
1136 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1137 {
1138 struct adv7842_state *state = to_state(sd);
1139 u8 offset_buf[4];
1140
1141 if (auto_offset) {
1142 offset_a = 0x3ff;
1143 offset_b = 0x3ff;
1144 offset_c = 0x3ff;
1145 }
1146
1147 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1148 __func__, auto_offset ? "Auto" : "Manual",
1149 offset_a, offset_b, offset_c);
1150
1151 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1152 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1153 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1154 offset_buf[3] = offset_c & 0x0ff;
1155
1156 /* Registers must be written in this order with no i2c access in between */
1157 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1158 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1159 }
1160
1161 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1162 {
1163 struct adv7842_state *state = to_state(sd);
1164 u8 gain_buf[4];
1165 u8 gain_man = 1;
1166 u8 agc_mode_man = 1;
1167
1168 if (auto_gain) {
1169 gain_man = 0;
1170 agc_mode_man = 0;
1171 gain_a = 0x100;
1172 gain_b = 0x100;
1173 gain_c = 0x100;
1174 }
1175
1176 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1177 __func__, auto_gain ? "Auto" : "Manual",
1178 gain_a, gain_b, gain_c);
1179
1180 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1181 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1182 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1183 gain_buf[3] = ((gain_c & 0x0ff));
1184
1185 /* Registers must be written in this order with no i2c access in between */
1186 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1187 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1188 }
1189
1190 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1191 {
1192 struct adv7842_state *state = to_state(sd);
1193 bool rgb_output = io_read(sd, 0x02) & 0x02;
1194 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1195
1196 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1197 __func__, state->rgb_quantization_range,
1198 rgb_output, hdmi_signal);
1199
1200 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1201 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1202
1203 switch (state->rgb_quantization_range) {
1204 case V4L2_DV_RGB_RANGE_AUTO:
1205 if (state->mode == ADV7842_MODE_RGB) {
1206 /* Receiving analog RGB signal
1207 * Set RGB full range (0-255) */
1208 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1209 break;
1210 }
1211
1212 if (state->mode == ADV7842_MODE_COMP) {
1213 /* Receiving analog YPbPr signal
1214 * Set automode */
1215 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1216 break;
1217 }
1218
1219 if (hdmi_signal) {
1220 /* Receiving HDMI signal
1221 * Set automode */
1222 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1223 break;
1224 }
1225
1226 /* Receiving DVI-D signal
1227 * ADV7842 selects RGB limited range regardless of
1228 * input format (CE/IT) in automatic mode */
1229 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1230 /* RGB limited range (16-235) */
1231 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1232 } else {
1233 /* RGB full range (0-255) */
1234 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1235
1236 if (is_digital_input(sd) && rgb_output) {
1237 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1238 } else {
1239 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1240 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1241 }
1242 }
1243 break;
1244 case V4L2_DV_RGB_RANGE_LIMITED:
1245 if (state->mode == ADV7842_MODE_COMP) {
1246 /* YCrCb limited range (16-235) */
1247 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1248 break;
1249 }
1250
1251 /* RGB limited range (16-235) */
1252 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1253
1254 break;
1255 case V4L2_DV_RGB_RANGE_FULL:
1256 if (state->mode == ADV7842_MODE_COMP) {
1257 /* YCrCb full range (0-255) */
1258 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1259 break;
1260 }
1261
1262 /* RGB full range (0-255) */
1263 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1264
1265 if (is_analog_input(sd) || hdmi_signal)
1266 break;
1267
1268 /* Adjust gain/offset for DVI-D signals only */
1269 if (rgb_output) {
1270 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1271 } else {
1272 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1273 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1274 }
1275 break;
1276 }
1277 }
1278
1279 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1280 {
1281 struct v4l2_subdev *sd = to_sd(ctrl);
1282 struct adv7842_state *state = to_state(sd);
1283
1284 /* TODO SDP ctrls
1285 contrast/brightness/hue/free run is acting a bit strange,
1286 not sure if sdp csc is correct.
1287 */
1288 switch (ctrl->id) {
1289 /* standard ctrls */
1290 case V4L2_CID_BRIGHTNESS:
1291 cp_write(sd, 0x3c, ctrl->val);
1292 sdp_write(sd, 0x14, ctrl->val);
1293 /* ignore lsb sdp 0x17[3:2] */
1294 return 0;
1295 case V4L2_CID_CONTRAST:
1296 cp_write(sd, 0x3a, ctrl->val);
1297 sdp_write(sd, 0x13, ctrl->val);
1298 /* ignore lsb sdp 0x17[1:0] */
1299 return 0;
1300 case V4L2_CID_SATURATION:
1301 cp_write(sd, 0x3b, ctrl->val);
1302 sdp_write(sd, 0x15, ctrl->val);
1303 /* ignore lsb sdp 0x17[5:4] */
1304 return 0;
1305 case V4L2_CID_HUE:
1306 cp_write(sd, 0x3d, ctrl->val);
1307 sdp_write(sd, 0x16, ctrl->val);
1308 /* ignore lsb sdp 0x17[7:6] */
1309 return 0;
1310 /* custom ctrls */
1311 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1312 afe_write(sd, 0xc8, ctrl->val);
1313 return 0;
1314 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1315 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1316 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1317 return 0;
1318 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1319 u8 R = (ctrl->val & 0xff0000) >> 16;
1320 u8 G = (ctrl->val & 0x00ff00) >> 8;
1321 u8 B = (ctrl->val & 0x0000ff);
1322 /* RGB -> YUV, numerical approximation */
1323 int Y = 66 * R + 129 * G + 25 * B;
1324 int U = -38 * R - 74 * G + 112 * B;
1325 int V = 112 * R - 94 * G - 18 * B;
1326
1327 /* Scale down to 8 bits with rounding */
1328 Y = (Y + 128) >> 8;
1329 U = (U + 128) >> 8;
1330 V = (V + 128) >> 8;
1331 /* make U,V positive */
1332 Y += 16;
1333 U += 128;
1334 V += 128;
1335
1336 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1337 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1338
1339 /* CP */
1340 cp_write(sd, 0xc1, R);
1341 cp_write(sd, 0xc0, G);
1342 cp_write(sd, 0xc2, B);
1343 /* SDP */
1344 sdp_write(sd, 0xde, Y);
1345 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1346 return 0;
1347 }
1348 case V4L2_CID_DV_RX_RGB_RANGE:
1349 state->rgb_quantization_range = ctrl->val;
1350 set_rgb_quantization_range(sd);
1351 return 0;
1352 }
1353 return -EINVAL;
1354 }
1355
1356 static inline bool no_power(struct v4l2_subdev *sd)
1357 {
1358 return io_read(sd, 0x0c) & 0x24;
1359 }
1360
1361 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1362 {
1363 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1364 }
1365
1366 static inline bool is_hdmi(struct v4l2_subdev *sd)
1367 {
1368 return hdmi_read(sd, 0x05) & 0x80;
1369 }
1370
1371 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1372 {
1373 struct adv7842_state *state = to_state(sd);
1374
1375 *status = 0;
1376
1377 if (io_read(sd, 0x0c) & 0x24)
1378 *status |= V4L2_IN_ST_NO_POWER;
1379
1380 if (state->mode == ADV7842_MODE_SDP) {
1381 /* status from SDP block */
1382 if (!(sdp_read(sd, 0x5A) & 0x01))
1383 *status |= V4L2_IN_ST_NO_SIGNAL;
1384
1385 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1386 __func__, *status);
1387 return 0;
1388 }
1389 /* status from CP block */
1390 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1391 !(cp_read(sd, 0xb1) & 0x80))
1392 /* TODO channel 2 */
1393 *status |= V4L2_IN_ST_NO_SIGNAL;
1394
1395 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1396 *status |= V4L2_IN_ST_NO_SIGNAL;
1397
1398 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1399 __func__, *status);
1400
1401 return 0;
1402 }
1403
1404 struct stdi_readback {
1405 u16 bl, lcf, lcvs;
1406 u8 hs_pol, vs_pol;
1407 bool interlaced;
1408 };
1409
1410 static int stdi2dv_timings(struct v4l2_subdev *sd,
1411 struct stdi_readback *stdi,
1412 struct v4l2_dv_timings *timings)
1413 {
1414 struct adv7842_state *state = to_state(sd);
1415 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1416 u32 pix_clk;
1417 int i;
1418
1419 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1420 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1421
1422 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1423 adv7842_get_dv_timings_cap(sd),
1424 adv7842_check_dv_timings, NULL))
1425 continue;
1426 if (vtotal(bt) != stdi->lcf + 1)
1427 continue;
1428 if (bt->vsync != stdi->lcvs)
1429 continue;
1430
1431 pix_clk = hfreq * htotal(bt);
1432
1433 if ((pix_clk < bt->pixelclock + 1000000) &&
1434 (pix_clk > bt->pixelclock - 1000000)) {
1435 *timings = v4l2_dv_timings_presets[i];
1436 return 0;
1437 }
1438 }
1439
1440 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1441 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1442 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1443 timings))
1444 return 0;
1445 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1446 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1447 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1448 state->aspect_ratio, timings))
1449 return 0;
1450
1451 v4l2_dbg(2, debug, sd,
1452 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1453 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1454 stdi->hs_pol, stdi->vs_pol);
1455 return -1;
1456 }
1457
1458 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1459 {
1460 u32 status;
1461
1462 adv7842_g_input_status(sd, &status);
1463 if (status & V4L2_IN_ST_NO_SIGNAL) {
1464 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1465 return -ENOLINK;
1466 }
1467
1468 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1469 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1470 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1471
1472 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1473 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1474 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1475 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1476 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1477 } else {
1478 stdi->hs_pol = 'x';
1479 stdi->vs_pol = 'x';
1480 }
1481 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1482
1483 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1484 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1485 return -ENOLINK;
1486 }
1487
1488 v4l2_dbg(2, debug, sd,
1489 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1490 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1491 stdi->hs_pol, stdi->vs_pol,
1492 stdi->interlaced ? "interlaced" : "progressive");
1493
1494 return 0;
1495 }
1496
1497 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1498 struct v4l2_enum_dv_timings *timings)
1499 {
1500 if (timings->pad != 0)
1501 return -EINVAL;
1502
1503 return v4l2_enum_dv_timings_cap(timings,
1504 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1505 }
1506
1507 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1508 struct v4l2_dv_timings_cap *cap)
1509 {
1510 if (cap->pad != 0)
1511 return -EINVAL;
1512
1513 *cap = *adv7842_get_dv_timings_cap(sd);
1514 return 0;
1515 }
1516
1517 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1518 if the format is listed in adv7842_timings[] */
1519 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1520 struct v4l2_dv_timings *timings)
1521 {
1522 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1523 is_digital_input(sd) ? 250000 : 1000000,
1524 adv7842_check_dv_timings, NULL);
1525 }
1526
1527 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1528 struct v4l2_dv_timings *timings)
1529 {
1530 struct adv7842_state *state = to_state(sd);
1531 struct v4l2_bt_timings *bt = &timings->bt;
1532 struct stdi_readback stdi = { 0 };
1533
1534 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1535
1536 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1537
1538 /* SDP block */
1539 if (state->mode == ADV7842_MODE_SDP)
1540 return -ENODATA;
1541
1542 /* read STDI */
1543 if (read_stdi(sd, &stdi)) {
1544 state->restart_stdi_once = true;
1545 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1546 return -ENOLINK;
1547 }
1548 bt->interlaced = stdi.interlaced ?
1549 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1550 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1551 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1552
1553 if (is_digital_input(sd)) {
1554 uint32_t freq;
1555
1556 timings->type = V4L2_DV_BT_656_1120;
1557
1558 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1559 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1560 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1561 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1562 if (is_hdmi(sd)) {
1563 /* adjust for deep color mode */
1564 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1565 }
1566 bt->pixelclock = freq;
1567 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1568 hdmi_read(sd, 0x21);
1569 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1570 hdmi_read(sd, 0x23);
1571 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1572 hdmi_read(sd, 0x25);
1573 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1574 hdmi_read(sd, 0x2b)) / 2;
1575 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1576 hdmi_read(sd, 0x2f)) / 2;
1577 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1578 hdmi_read(sd, 0x33)) / 2;
1579 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1580 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1581 if (bt->interlaced == V4L2_DV_INTERLACED) {
1582 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1583 hdmi_read(sd, 0x0c);
1584 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1585 hdmi_read(sd, 0x2d)) / 2;
1586 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1587 hdmi_read(sd, 0x31)) / 2;
1588 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1589 hdmi_read(sd, 0x35)) / 2;
1590 } else {
1591 bt->il_vfrontporch = 0;
1592 bt->il_vsync = 0;
1593 bt->il_vbackporch = 0;
1594 }
1595 adv7842_fill_optional_dv_timings_fields(sd, timings);
1596 } else {
1597 /* find format
1598 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1599 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1600 */
1601 if (!stdi2dv_timings(sd, &stdi, timings))
1602 goto found;
1603 stdi.lcvs += 1;
1604 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1605 if (!stdi2dv_timings(sd, &stdi, timings))
1606 goto found;
1607 stdi.lcvs -= 2;
1608 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1609 if (stdi2dv_timings(sd, &stdi, timings)) {
1610 /*
1611 * The STDI block may measure wrong values, especially
1612 * for lcvs and lcf. If the driver can not find any
1613 * valid timing, the STDI block is restarted to measure
1614 * the video timings again. The function will return an
1615 * error, but the restart of STDI will generate a new
1616 * STDI interrupt and the format detection process will
1617 * restart.
1618 */
1619 if (state->restart_stdi_once) {
1620 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1621 /* TODO restart STDI for Sync Channel 2 */
1622 /* enter one-shot mode */
1623 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1624 /* trigger STDI restart */
1625 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1626 /* reset to continuous mode */
1627 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1628 state->restart_stdi_once = false;
1629 return -ENOLINK;
1630 }
1631 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1632 return -ERANGE;
1633 }
1634 state->restart_stdi_once = true;
1635 }
1636 found:
1637
1638 if (debug > 1)
1639 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1640 timings, true);
1641 return 0;
1642 }
1643
1644 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1645 struct v4l2_dv_timings *timings)
1646 {
1647 struct adv7842_state *state = to_state(sd);
1648 struct v4l2_bt_timings *bt;
1649 int err;
1650
1651 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1652
1653 if (state->mode == ADV7842_MODE_SDP)
1654 return -ENODATA;
1655
1656 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1657 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1658 return 0;
1659 }
1660
1661 bt = &timings->bt;
1662
1663 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1664 adv7842_check_dv_timings, NULL))
1665 return -ERANGE;
1666
1667 adv7842_fill_optional_dv_timings_fields(sd, timings);
1668
1669 state->timings = *timings;
1670
1671 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1672
1673 /* Use prim_mode and vid_std when available */
1674 err = configure_predefined_video_timings(sd, timings);
1675 if (err) {
1676 /* custom settings when the video format
1677 does not have prim_mode/vid_std */
1678 configure_custom_video_timings(sd, bt);
1679 }
1680
1681 set_rgb_quantization_range(sd);
1682
1683
1684 if (debug > 1)
1685 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1686 timings, true);
1687 return 0;
1688 }
1689
1690 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1691 struct v4l2_dv_timings *timings)
1692 {
1693 struct adv7842_state *state = to_state(sd);
1694
1695 if (state->mode == ADV7842_MODE_SDP)
1696 return -ENODATA;
1697 *timings = state->timings;
1698 return 0;
1699 }
1700
1701 static void enable_input(struct v4l2_subdev *sd)
1702 {
1703 struct adv7842_state *state = to_state(sd);
1704
1705 set_rgb_quantization_range(sd);
1706 switch (state->mode) {
1707 case ADV7842_MODE_SDP:
1708 case ADV7842_MODE_COMP:
1709 case ADV7842_MODE_RGB:
1710 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1711 break;
1712 case ADV7842_MODE_HDMI:
1713 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1714 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1715 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1716 break;
1717 default:
1718 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1719 __func__, state->mode);
1720 break;
1721 }
1722 }
1723
1724 static void disable_input(struct v4l2_subdev *sd)
1725 {
1726 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1727 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1728 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1729 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1730 }
1731
1732 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1733 const struct adv7842_sdp_csc_coeff *c)
1734 {
1735 /* csc auto/manual */
1736 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1737
1738 if (!c->manual)
1739 return;
1740
1741 /* csc scaling */
1742 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1743
1744 /* A coeff */
1745 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1746 sdp_io_write(sd, 0xe1, c->A1);
1747 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1748 sdp_io_write(sd, 0xe3, c->A2);
1749 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1750 sdp_io_write(sd, 0xe5, c->A3);
1751
1752 /* A scale */
1753 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1754 sdp_io_write(sd, 0xe7, c->A4);
1755
1756 /* B coeff */
1757 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1758 sdp_io_write(sd, 0xe9, c->B1);
1759 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1760 sdp_io_write(sd, 0xeb, c->B2);
1761 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1762 sdp_io_write(sd, 0xed, c->B3);
1763
1764 /* B scale */
1765 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1766 sdp_io_write(sd, 0xef, c->B4);
1767
1768 /* C coeff */
1769 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1770 sdp_io_write(sd, 0xf1, c->C1);
1771 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1772 sdp_io_write(sd, 0xf3, c->C2);
1773 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1774 sdp_io_write(sd, 0xf5, c->C3);
1775
1776 /* C scale */
1777 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1778 sdp_io_write(sd, 0xf7, c->C4);
1779 }
1780
1781 static void select_input(struct v4l2_subdev *sd,
1782 enum adv7842_vid_std_select vid_std_select)
1783 {
1784 struct adv7842_state *state = to_state(sd);
1785
1786 switch (state->mode) {
1787 case ADV7842_MODE_SDP:
1788 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1789 io_write(sd, 0x01, 0); /* prim mode */
1790 /* enable embedded syncs for auto graphics mode */
1791 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1792
1793 afe_write(sd, 0x00, 0x00); /* power up ADC */
1794 afe_write(sd, 0xc8, 0x00); /* phase control */
1795
1796 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1797 /* script says register 0xde, which don't exist in manual */
1798
1799 /* Manual analog input muxing mode, CVBS (6.4)*/
1800 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1801 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1802 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1803 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1804 } else {
1805 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1806 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1807 }
1808 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1809 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1810
1811 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1812 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1813
1814 /* SDP recommended settings */
1815 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1816 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1817
1818 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1819 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1820 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1821 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1822 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1823 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1824 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1825
1826 /* deinterlacer enabled and 3D comb */
1827 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1828
1829 break;
1830
1831 case ADV7842_MODE_COMP:
1832 case ADV7842_MODE_RGB:
1833 /* Automatic analog input muxing mode */
1834 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1835 /* set mode and select free run resolution */
1836 io_write(sd, 0x00, vid_std_select); /* video std */
1837 io_write(sd, 0x01, 0x02); /* prim mode */
1838 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1839 for auto graphics mode */
1840
1841 afe_write(sd, 0x00, 0x00); /* power up ADC */
1842 afe_write(sd, 0xc8, 0x00); /* phase control */
1843 if (state->mode == ADV7842_MODE_COMP) {
1844 /* force to YCrCb */
1845 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1846 } else {
1847 /* force to RGB */
1848 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1849 }
1850
1851 /* set ADI recommended settings for digitizer */
1852 /* "ADV7842 Register Settings Recommendations
1853 * (rev. 1.8, November 2010)" p. 9. */
1854 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1855 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1856
1857 /* set to default gain for RGB */
1858 cp_write(sd, 0x73, 0x10);
1859 cp_write(sd, 0x74, 0x04);
1860 cp_write(sd, 0x75, 0x01);
1861 cp_write(sd, 0x76, 0x00);
1862
1863 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1864 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1865 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1866 break;
1867
1868 case ADV7842_MODE_HDMI:
1869 /* Automatic analog input muxing mode */
1870 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1871 /* set mode and select free run resolution */
1872 if (state->hdmi_port_a)
1873 hdmi_write(sd, 0x00, 0x02); /* select port A */
1874 else
1875 hdmi_write(sd, 0x00, 0x03); /* select port B */
1876 io_write(sd, 0x00, vid_std_select); /* video std */
1877 io_write(sd, 0x01, 5); /* prim mode */
1878 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1879 for auto graphics mode */
1880
1881 /* set ADI recommended settings for HDMI: */
1882 /* "ADV7842 Register Settings Recommendations
1883 * (rev. 1.8, November 2010)" p. 3. */
1884 hdmi_write(sd, 0xc0, 0x00);
1885 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1886 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1887 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1888 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1889 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1890 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1891 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1892 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1893 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1894 Improve robustness */
1895 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1896 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1897 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1898 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1899 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1900 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1901 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1902 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1903 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1904 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1905
1906 afe_write(sd, 0x00, 0xff); /* power down ADC */
1907 afe_write(sd, 0xc8, 0x40); /* phase control */
1908
1909 /* set to default gain for HDMI */
1910 cp_write(sd, 0x73, 0x10);
1911 cp_write(sd, 0x74, 0x04);
1912 cp_write(sd, 0x75, 0x01);
1913 cp_write(sd, 0x76, 0x00);
1914
1915 /* reset ADI recommended settings for digitizer */
1916 /* "ADV7842 Register Settings Recommendations
1917 * (rev. 2.5, June 2010)" p. 17. */
1918 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1919 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1920 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1921
1922 /* CP coast control */
1923 cp_write(sd, 0xc3, 0x33); /* Component mode */
1924
1925 /* color space conversion, autodetect color space */
1926 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1927 break;
1928
1929 default:
1930 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1931 __func__, state->mode);
1932 break;
1933 }
1934 }
1935
1936 static int adv7842_s_routing(struct v4l2_subdev *sd,
1937 u32 input, u32 output, u32 config)
1938 {
1939 struct adv7842_state *state = to_state(sd);
1940
1941 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1942
1943 switch (input) {
1944 case ADV7842_SELECT_HDMI_PORT_A:
1945 state->mode = ADV7842_MODE_HDMI;
1946 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1947 state->hdmi_port_a = true;
1948 break;
1949 case ADV7842_SELECT_HDMI_PORT_B:
1950 state->mode = ADV7842_MODE_HDMI;
1951 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1952 state->hdmi_port_a = false;
1953 break;
1954 case ADV7842_SELECT_VGA_COMP:
1955 state->mode = ADV7842_MODE_COMP;
1956 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1957 break;
1958 case ADV7842_SELECT_VGA_RGB:
1959 state->mode = ADV7842_MODE_RGB;
1960 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1961 break;
1962 case ADV7842_SELECT_SDP_CVBS:
1963 state->mode = ADV7842_MODE_SDP;
1964 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1965 break;
1966 case ADV7842_SELECT_SDP_YC:
1967 state->mode = ADV7842_MODE_SDP;
1968 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1969 break;
1970 default:
1971 return -EINVAL;
1972 }
1973
1974 disable_input(sd);
1975 select_input(sd, state->vid_std_select);
1976 enable_input(sd);
1977
1978 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1979
1980 return 0;
1981 }
1982
1983 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
1984 struct v4l2_subdev_pad_config *cfg,
1985 struct v4l2_subdev_mbus_code_enum *code)
1986 {
1987 if (code->index >= ARRAY_SIZE(adv7842_formats))
1988 return -EINVAL;
1989 code->code = adv7842_formats[code->index].code;
1990 return 0;
1991 }
1992
1993 static void adv7842_fill_format(struct adv7842_state *state,
1994 struct v4l2_mbus_framefmt *format)
1995 {
1996 memset(format, 0, sizeof(*format));
1997
1998 format->width = state->timings.bt.width;
1999 format->height = state->timings.bt.height;
2000 format->field = V4L2_FIELD_NONE;
2001 format->colorspace = V4L2_COLORSPACE_SRGB;
2002
2003 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2004 format->colorspace = (state->timings.bt.height <= 576) ?
2005 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2006 }
2007
2008 /*
2009 * Compute the op_ch_sel value required to obtain on the bus the component order
2010 * corresponding to the selected format taking into account bus reordering
2011 * applied by the board at the output of the device.
2012 *
2013 * The following table gives the op_ch_value from the format component order
2014 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2015 * adv7842_bus_order value in row).
2016 *
2017 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2018 * ----------+-------------------------------------------------
2019 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
2020 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2021 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2022 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2023 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
2024 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
2025 */
2026 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2027 {
2028 #define _SEL(a, b, c, d, e, f) { \
2029 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2030 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2031 #define _BUS(x) [ADV7842_BUS_ORDER_##x]
2032
2033 static const unsigned int op_ch_sel[6][6] = {
2034 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2035 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2036 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2037 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2038 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2039 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2040 };
2041
2042 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2043 }
2044
2045 static void adv7842_setup_format(struct adv7842_state *state)
2046 {
2047 struct v4l2_subdev *sd = &state->sd;
2048
2049 io_write_clr_set(sd, 0x02, 0x02,
2050 state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2051 io_write(sd, 0x03, state->format->op_format_sel |
2052 state->pdata.op_format_mode_sel);
2053 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2054 io_write_clr_set(sd, 0x05, 0x01,
2055 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2056 }
2057
2058 static int adv7842_get_format(struct v4l2_subdev *sd,
2059 struct v4l2_subdev_pad_config *cfg,
2060 struct v4l2_subdev_format *format)
2061 {
2062 struct adv7842_state *state = to_state(sd);
2063
2064 if (format->pad != ADV7842_PAD_SOURCE)
2065 return -EINVAL;
2066
2067 if (state->mode == ADV7842_MODE_SDP) {
2068 /* SPD block */
2069 if (!(sdp_read(sd, 0x5a) & 0x01))
2070 return -EINVAL;
2071 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2072 format->format.width = 720;
2073 /* valid signal */
2074 if (state->norm & V4L2_STD_525_60)
2075 format->format.height = 480;
2076 else
2077 format->format.height = 576;
2078 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
2079 return 0;
2080 }
2081
2082 adv7842_fill_format(state, &format->format);
2083
2084 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2085 struct v4l2_mbus_framefmt *fmt;
2086
2087 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2088 format->format.code = fmt->code;
2089 } else {
2090 format->format.code = state->format->code;
2091 }
2092
2093 return 0;
2094 }
2095
2096 static int adv7842_set_format(struct v4l2_subdev *sd,
2097 struct v4l2_subdev_pad_config *cfg,
2098 struct v4l2_subdev_format *format)
2099 {
2100 struct adv7842_state *state = to_state(sd);
2101 const struct adv7842_format_info *info;
2102
2103 if (format->pad != ADV7842_PAD_SOURCE)
2104 return -EINVAL;
2105
2106 if (state->mode == ADV7842_MODE_SDP)
2107 return adv7842_get_format(sd, cfg, format);
2108
2109 info = adv7842_format_info(state, format->format.code);
2110 if (info == NULL)
2111 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2112
2113 adv7842_fill_format(state, &format->format);
2114 format->format.code = info->code;
2115
2116 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2117 struct v4l2_mbus_framefmt *fmt;
2118
2119 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2120 fmt->code = format->format.code;
2121 } else {
2122 state->format = info;
2123 adv7842_setup_format(state);
2124 }
2125
2126 return 0;
2127 }
2128
2129 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2130 {
2131 if (enable) {
2132 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
2133 io_write(sd, 0x46, 0x9c);
2134 /* ESDP_50HZ_DET interrupt */
2135 io_write(sd, 0x5a, 0x10);
2136 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2137 io_write(sd, 0x73, 0x03);
2138 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2139 io_write(sd, 0x78, 0x03);
2140 /* Enable SDP Standard Detection Change and SDP Video Detected */
2141 io_write(sd, 0xa0, 0x09);
2142 /* Enable HDMI_MODE interrupt */
2143 io_write(sd, 0x69, 0x08);
2144 } else {
2145 io_write(sd, 0x46, 0x0);
2146 io_write(sd, 0x5a, 0x0);
2147 io_write(sd, 0x73, 0x0);
2148 io_write(sd, 0x78, 0x0);
2149 io_write(sd, 0xa0, 0x0);
2150 io_write(sd, 0x69, 0x0);
2151 }
2152 }
2153
2154 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2155 {
2156 struct adv7842_state *state = to_state(sd);
2157 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
2158 u8 irq_status[6];
2159
2160 adv7842_irq_enable(sd, false);
2161
2162 /* read status */
2163 irq_status[0] = io_read(sd, 0x43);
2164 irq_status[1] = io_read(sd, 0x57);
2165 irq_status[2] = io_read(sd, 0x70);
2166 irq_status[3] = io_read(sd, 0x75);
2167 irq_status[4] = io_read(sd, 0x9d);
2168 irq_status[5] = io_read(sd, 0x66);
2169
2170 /* and clear */
2171 if (irq_status[0])
2172 io_write(sd, 0x44, irq_status[0]);
2173 if (irq_status[1])
2174 io_write(sd, 0x58, irq_status[1]);
2175 if (irq_status[2])
2176 io_write(sd, 0x71, irq_status[2]);
2177 if (irq_status[3])
2178 io_write(sd, 0x76, irq_status[3]);
2179 if (irq_status[4])
2180 io_write(sd, 0x9e, irq_status[4]);
2181 if (irq_status[5])
2182 io_write(sd, 0x67, irq_status[5]);
2183
2184 adv7842_irq_enable(sd, true);
2185
2186 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2187 irq_status[0], irq_status[1], irq_status[2],
2188 irq_status[3], irq_status[4], irq_status[5]);
2189
2190 /* format change CP */
2191 fmt_change_cp = irq_status[0] & 0x9c;
2192
2193 /* format change SDP */
2194 if (state->mode == ADV7842_MODE_SDP)
2195 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2196 else
2197 fmt_change_sdp = 0;
2198
2199 /* digital format CP */
2200 if (is_digital_input(sd))
2201 fmt_change_digital = irq_status[3] & 0x03;
2202 else
2203 fmt_change_digital = 0;
2204
2205 /* format change */
2206 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2207 v4l2_dbg(1, debug, sd,
2208 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2209 __func__, fmt_change_cp, fmt_change_digital,
2210 fmt_change_sdp);
2211 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
2212 if (handled)
2213 *handled = true;
2214 }
2215
2216 /* HDMI/DVI mode */
2217 if (irq_status[5] & 0x08) {
2218 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2219 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2220 set_rgb_quantization_range(sd);
2221 if (handled)
2222 *handled = true;
2223 }
2224
2225 /* tx 5v detect */
2226 if (irq_status[2] & 0x3) {
2227 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2228 adv7842_s_detect_tx_5v_ctrl(sd);
2229 if (handled)
2230 *handled = true;
2231 }
2232 return 0;
2233 }
2234
2235 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2236 {
2237 struct adv7842_state *state = to_state(sd);
2238 u8 *data = NULL;
2239
2240 memset(edid->reserved, 0, sizeof(edid->reserved));
2241
2242 switch (edid->pad) {
2243 case ADV7842_EDID_PORT_A:
2244 case ADV7842_EDID_PORT_B:
2245 if (state->hdmi_edid.present & (0x04 << edid->pad))
2246 data = state->hdmi_edid.edid;
2247 break;
2248 case ADV7842_EDID_PORT_VGA:
2249 if (state->vga_edid.present)
2250 data = state->vga_edid.edid;
2251 break;
2252 default:
2253 return -EINVAL;
2254 }
2255
2256 if (edid->start_block == 0 && edid->blocks == 0) {
2257 edid->blocks = data ? 2 : 0;
2258 return 0;
2259 }
2260
2261 if (!data)
2262 return -ENODATA;
2263
2264 if (edid->start_block >= 2)
2265 return -EINVAL;
2266
2267 if (edid->start_block + edid->blocks > 2)
2268 edid->blocks = 2 - edid->start_block;
2269
2270 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2271
2272 return 0;
2273 }
2274
2275 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2276 {
2277 struct adv7842_state *state = to_state(sd);
2278 int err = 0;
2279
2280 memset(e->reserved, 0, sizeof(e->reserved));
2281
2282 if (e->pad > ADV7842_EDID_PORT_VGA)
2283 return -EINVAL;
2284 if (e->start_block != 0)
2285 return -EINVAL;
2286 if (e->blocks > 2) {
2287 e->blocks = 2;
2288 return -E2BIG;
2289 }
2290
2291 /* todo, per edid */
2292 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2293 e->edid[0x16]);
2294
2295 switch (e->pad) {
2296 case ADV7842_EDID_PORT_VGA:
2297 memset(&state->vga_edid.edid, 0, 256);
2298 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2299 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2300 err = edid_write_vga_segment(sd);
2301 break;
2302 case ADV7842_EDID_PORT_A:
2303 case ADV7842_EDID_PORT_B:
2304 memset(&state->hdmi_edid.edid, 0, 256);
2305 if (e->blocks)
2306 state->hdmi_edid.present |= 0x04 << e->pad;
2307 else
2308 state->hdmi_edid.present &= ~(0x04 << e->pad);
2309 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2310 err = edid_write_hdmi_segment(sd, e->pad);
2311 break;
2312 default:
2313 return -EINVAL;
2314 }
2315 if (err < 0)
2316 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2317 return err;
2318 }
2319
2320 struct adv7842_cfg_read_infoframe {
2321 const char *desc;
2322 u8 present_mask;
2323 u8 head_addr;
2324 u8 payload_addr;
2325 };
2326
2327 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
2328 {
2329 int i;
2330 uint8_t buffer[32];
2331 union hdmi_infoframe frame;
2332 u8 len;
2333 struct i2c_client *client = v4l2_get_subdevdata(sd);
2334 struct device *dev = &client->dev;
2335
2336 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2337 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2338 return;
2339 }
2340
2341 for (i = 0; i < 3; i++)
2342 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2343
2344 len = buffer[2] + 1;
2345
2346 if (len + 3 > sizeof(buffer)) {
2347 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2348 return;
2349 }
2350
2351 for (i = 0; i < len; i++)
2352 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2353
2354 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
2355 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2356 return;
2357 }
2358
2359 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2360 }
2361
2362 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2363 {
2364 int i;
2365 struct adv7842_cfg_read_infoframe cri[] = {
2366 { "AVI", 0x01, 0xe0, 0x00 },
2367 { "Audio", 0x02, 0xe3, 0x1c },
2368 { "SDP", 0x04, 0xe6, 0x2a },
2369 { "Vendor", 0x10, 0xec, 0x54 }
2370 };
2371
2372 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2373 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2374 return;
2375 }
2376
2377 for (i = 0; i < ARRAY_SIZE(cri); i++)
2378 log_infoframe(sd, &cri[i]);
2379 }
2380
2381 static const char * const prim_mode_txt[] = {
2382 "SDP",
2383 "Component",
2384 "Graphics",
2385 "Reserved",
2386 "CVBS & HDMI AUDIO",
2387 "HDMI-Comp",
2388 "HDMI-GR",
2389 "Reserved",
2390 "Reserved",
2391 "Reserved",
2392 "Reserved",
2393 "Reserved",
2394 "Reserved",
2395 "Reserved",
2396 "Reserved",
2397 "Reserved",
2398 };
2399
2400 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2401 {
2402 /* SDP (Standard definition processor) block */
2403 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2404
2405 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2406 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2407 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2408
2409 v4l2_info(sd, "SDP: free run: %s\n",
2410 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2411 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2412 "valid SD/PR signal detected" : "invalid/no signal");
2413 if (sdp_signal_detected) {
2414 static const char * const sdp_std_txt[] = {
2415 "NTSC-M/J",
2416 "1?",
2417 "NTSC-443",
2418 "60HzSECAM",
2419 "PAL-M",
2420 "5?",
2421 "PAL-60",
2422 "7?", "8?", "9?", "a?", "b?",
2423 "PAL-CombN",
2424 "d?",
2425 "PAL-BGHID",
2426 "SECAM"
2427 };
2428 v4l2_info(sd, "SDP: standard %s\n",
2429 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2430 v4l2_info(sd, "SDP: %s\n",
2431 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2432 v4l2_info(sd, "SDP: %s\n",
2433 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2434 v4l2_info(sd, "SDP: deinterlacer %s\n",
2435 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2436 v4l2_info(sd, "SDP: csc %s mode\n",
2437 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2438 }
2439 return 0;
2440 }
2441
2442 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2443 {
2444 /* CP block */
2445 struct adv7842_state *state = to_state(sd);
2446 struct v4l2_dv_timings timings;
2447 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2448 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2449 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2450 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2451 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2452 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2453 bool audio_mute = io_read(sd, 0x65) & 0x40;
2454
2455 static const char * const csc_coeff_sel_rb[16] = {
2456 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2457 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2458 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2459 "reserved", "reserved", "reserved", "reserved", "manual"
2460 };
2461 static const char * const input_color_space_txt[16] = {
2462 "RGB limited range (16-235)", "RGB full range (0-255)",
2463 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2464 "xvYCC Bt.601", "xvYCC Bt.709",
2465 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2466 "invalid", "invalid", "invalid", "invalid", "invalid",
2467 "invalid", "invalid", "automatic"
2468 };
2469 static const char * const rgb_quantization_range_txt[] = {
2470 "Automatic",
2471 "RGB limited range (16-235)",
2472 "RGB full range (0-255)",
2473 };
2474 static const char * const deep_color_mode_txt[4] = {
2475 "8-bits per channel",
2476 "10-bits per channel",
2477 "12-bits per channel",
2478 "16-bits per channel (not supported)"
2479 };
2480
2481 v4l2_info(sd, "-----Chip status-----\n");
2482 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2483 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2484 state->hdmi_port_a ? "A" : "B");
2485 v4l2_info(sd, "EDID A %s, B %s\n",
2486 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2487 "enabled" : "disabled",
2488 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2489 "enabled" : "disabled");
2490 v4l2_info(sd, "HPD A %s, B %s\n",
2491 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2492 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2493 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2494 "enabled" : "disabled");
2495
2496 v4l2_info(sd, "-----Signal status-----\n");
2497 if (state->hdmi_port_a) {
2498 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2499 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2500 v4l2_info(sd, "TMDS signal detected: %s\n",
2501 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2502 v4l2_info(sd, "TMDS signal locked: %s\n",
2503 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2504 } else {
2505 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2506 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2507 v4l2_info(sd, "TMDS signal detected: %s\n",
2508 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2509 v4l2_info(sd, "TMDS signal locked: %s\n",
2510 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2511 }
2512 v4l2_info(sd, "CP free run: %s\n",
2513 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2514 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2515 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2516 (io_read(sd, 0x01) & 0x70) >> 4);
2517
2518 v4l2_info(sd, "-----Video Timings-----\n");
2519 if (no_cp_signal(sd)) {
2520 v4l2_info(sd, "STDI: not locked\n");
2521 } else {
2522 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2523 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2524 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2525 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2526 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2527 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2528 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2529 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2530 v4l2_info(sd,
2531 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2532 lcf, bl, lcvs, fcl,
2533 (cp_read(sd, 0xb1) & 0x40) ?
2534 "interlaced" : "progressive",
2535 hs_pol, vs_pol);
2536 }
2537 if (adv7842_query_dv_timings(sd, &timings))
2538 v4l2_info(sd, "No video detected\n");
2539 else
2540 v4l2_print_dv_timings(sd->name, "Detected format: ",
2541 &timings, true);
2542 v4l2_print_dv_timings(sd->name, "Configured format: ",
2543 &state->timings, true);
2544
2545 if (no_cp_signal(sd))
2546 return 0;
2547
2548 v4l2_info(sd, "-----Color space-----\n");
2549 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2550 rgb_quantization_range_txt[state->rgb_quantization_range]);
2551 v4l2_info(sd, "Input color space: %s\n",
2552 input_color_space_txt[reg_io_0x02 >> 4]);
2553 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2554 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2555 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2556 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2557 "enabled" : "disabled");
2558 v4l2_info(sd, "Color space conversion: %s\n",
2559 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2560
2561 if (!is_digital_input(sd))
2562 return 0;
2563
2564 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2565 v4l2_info(sd, "HDCP encrypted content: %s\n",
2566 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2567 v4l2_info(sd, "HDCP keys read: %s%s\n",
2568 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2569 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2570 if (!is_hdmi(sd))
2571 return 0;
2572
2573 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2574 audio_pll_locked ? "locked" : "not locked",
2575 audio_sample_packet_detect ? "detected" : "not detected",
2576 audio_mute ? "muted" : "enabled");
2577 if (audio_pll_locked && audio_sample_packet_detect) {
2578 v4l2_info(sd, "Audio format: %s\n",
2579 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2580 }
2581 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2582 (hdmi_read(sd, 0x5c) << 8) +
2583 (hdmi_read(sd, 0x5d) & 0xf0));
2584 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2585 (hdmi_read(sd, 0x5e) << 8) +
2586 hdmi_read(sd, 0x5f));
2587 v4l2_info(sd, "AV Mute: %s\n",
2588 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2589 v4l2_info(sd, "Deep color mode: %s\n",
2590 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2591
2592 adv7842_log_infoframes(sd);
2593
2594 return 0;
2595 }
2596
2597 static int adv7842_log_status(struct v4l2_subdev *sd)
2598 {
2599 struct adv7842_state *state = to_state(sd);
2600
2601 if (state->mode == ADV7842_MODE_SDP)
2602 return adv7842_sdp_log_status(sd);
2603 return adv7842_cp_log_status(sd);
2604 }
2605
2606 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2607 {
2608 struct adv7842_state *state = to_state(sd);
2609
2610 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2611
2612 if (state->mode != ADV7842_MODE_SDP)
2613 return -ENODATA;
2614
2615 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2616 *std = 0;
2617 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2618 return 0;
2619 }
2620
2621 switch (sdp_read(sd, 0x52) & 0x0f) {
2622 case 0:
2623 /* NTSC-M/J */
2624 *std &= V4L2_STD_NTSC;
2625 break;
2626 case 2:
2627 /* NTSC-443 */
2628 *std &= V4L2_STD_NTSC_443;
2629 break;
2630 case 3:
2631 /* 60HzSECAM */
2632 *std &= V4L2_STD_SECAM;
2633 break;
2634 case 4:
2635 /* PAL-M */
2636 *std &= V4L2_STD_PAL_M;
2637 break;
2638 case 6:
2639 /* PAL-60 */
2640 *std &= V4L2_STD_PAL_60;
2641 break;
2642 case 0xc:
2643 /* PAL-CombN */
2644 *std &= V4L2_STD_PAL_Nc;
2645 break;
2646 case 0xe:
2647 /* PAL-BGHID */
2648 *std &= V4L2_STD_PAL;
2649 break;
2650 case 0xf:
2651 /* SECAM */
2652 *std &= V4L2_STD_SECAM;
2653 break;
2654 default:
2655 *std &= V4L2_STD_ALL;
2656 break;
2657 }
2658 return 0;
2659 }
2660
2661 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2662 {
2663 if (s && s->adjust) {
2664 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2665 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2666 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2667 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2668 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2669 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2670 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2671 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2672 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2673 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2674 sdp_io_write(sd, 0xaa, s->vs_end_o);
2675 sdp_io_write(sd, 0xab, s->vs_end_e);
2676 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2677 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2678 sdp_io_write(sd, 0xae, s->de_v_end_o);
2679 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2680 } else {
2681 /* set to default */
2682 sdp_io_write(sd, 0x94, 0x00);
2683 sdp_io_write(sd, 0x95, 0x00);
2684 sdp_io_write(sd, 0x96, 0x00);
2685 sdp_io_write(sd, 0x97, 0x20);
2686 sdp_io_write(sd, 0x98, 0x00);
2687 sdp_io_write(sd, 0x99, 0x00);
2688 sdp_io_write(sd, 0x9a, 0x00);
2689 sdp_io_write(sd, 0x9b, 0x00);
2690 sdp_io_write(sd, 0xa8, 0x04);
2691 sdp_io_write(sd, 0xa9, 0x04);
2692 sdp_io_write(sd, 0xaa, 0x04);
2693 sdp_io_write(sd, 0xab, 0x04);
2694 sdp_io_write(sd, 0xac, 0x04);
2695 sdp_io_write(sd, 0xad, 0x04);
2696 sdp_io_write(sd, 0xae, 0x04);
2697 sdp_io_write(sd, 0xaf, 0x04);
2698 }
2699 }
2700
2701 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2702 {
2703 struct adv7842_state *state = to_state(sd);
2704 struct adv7842_platform_data *pdata = &state->pdata;
2705
2706 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2707
2708 if (state->mode != ADV7842_MODE_SDP)
2709 return -ENODATA;
2710
2711 if (norm & V4L2_STD_625_50)
2712 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2713 else if (norm & V4L2_STD_525_60)
2714 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2715 else
2716 adv7842_s_sdp_io(sd, NULL);
2717
2718 if (norm & V4L2_STD_ALL) {
2719 state->norm = norm;
2720 return 0;
2721 }
2722 return -EINVAL;
2723 }
2724
2725 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2726 {
2727 struct adv7842_state *state = to_state(sd);
2728
2729 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2730
2731 if (state->mode != ADV7842_MODE_SDP)
2732 return -ENODATA;
2733
2734 *norm = state->norm;
2735 return 0;
2736 }
2737
2738 /* ----------------------------------------------------------------------- */
2739
2740 static int adv7842_core_init(struct v4l2_subdev *sd)
2741 {
2742 struct adv7842_state *state = to_state(sd);
2743 struct adv7842_platform_data *pdata = &state->pdata;
2744 hdmi_write(sd, 0x48,
2745 (pdata->disable_pwrdnb ? 0x80 : 0) |
2746 (pdata->disable_cable_det_rst ? 0x40 : 0));
2747
2748 disable_input(sd);
2749
2750 /*
2751 * Disable I2C access to internal EDID ram from HDMI DDC ports
2752 * Disable auto edid enable when leaving powerdown mode
2753 */
2754 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2755
2756 /* power */
2757 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2758 io_write(sd, 0x15, 0x80); /* Power up pads */
2759
2760 /* video format */
2761 io_write(sd, 0x02,
2762 0xf0 |
2763 pdata->alt_gamma << 3 |
2764 pdata->op_656_range << 2 |
2765 pdata->alt_data_sat << 0);
2766 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2767 pdata->insert_av_codes << 2 |
2768 pdata->replicate_av_codes << 1);
2769 adv7842_setup_format(state);
2770
2771 /* HDMI audio */
2772 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2773
2774 /* Drive strength */
2775 io_write_and_or(sd, 0x14, 0xc0,
2776 pdata->dr_str_data << 4 |
2777 pdata->dr_str_clk << 2 |
2778 pdata->dr_str_sync);
2779
2780 /* HDMI free run */
2781 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
2782 (pdata->hdmi_free_run_mode << 1));
2783
2784 /* SPD free run */
2785 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
2786 (pdata->sdp_free_run_cbar_en << 1) |
2787 (pdata->sdp_free_run_man_col_en << 2) |
2788 (pdata->sdp_free_run_auto << 3));
2789
2790 /* TODO from platform data */
2791 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2792 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2793 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2794 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2795
2796 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2797 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2798
2799 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2800
2801 /* todo, improve settings for sdram */
2802 if (pdata->sd_ram_size >= 128) {
2803 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2804 if (pdata->sd_ram_ddr) {
2805 /* SDP setup for the AD eval board */
2806 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2807 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2808 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2809 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2810 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2811 } else {
2812 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2813 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2814 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2815 depends on memory */
2816 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2817 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2818 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2819 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2820 }
2821 } else {
2822 /*
2823 * Manual UG-214, rev 0 is bit confusing on this bit
2824 * but a '1' disables any signal if the Ram is active.
2825 */
2826 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2827 }
2828
2829 select_input(sd, pdata->vid_std_select);
2830
2831 enable_input(sd);
2832
2833 if (pdata->hpa_auto) {
2834 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
2835 hdmi_write(sd, 0x69, 0x5c);
2836 } else {
2837 /* HPA manual */
2838 hdmi_write(sd, 0x69, 0xa3);
2839 /* HPA disable on port A and B */
2840 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2841 }
2842
2843 /* LLC */
2844 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
2845 io_write(sd, 0x33, 0x40);
2846
2847 /* interrupts */
2848 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2849
2850 adv7842_irq_enable(sd, true);
2851
2852 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2853 }
2854
2855 /* ----------------------------------------------------------------------- */
2856
2857 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2858 {
2859 /*
2860 * From ADV784x external Memory test.pdf
2861 *
2862 * Reset must just been performed before running test.
2863 * Recommended to reset after test.
2864 */
2865 int i;
2866 int pass = 0;
2867 int fail = 0;
2868 int complete = 0;
2869
2870 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2871 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2872 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2873 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2874 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2875 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2876 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2877 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2878 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2879 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2880 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2881 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2882
2883 mdelay(5);
2884
2885 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2886 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2887 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2888 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2889 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2890 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2891 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2892 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2893 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2894 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2895 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2896
2897 mdelay(5);
2898
2899 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2900 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2901
2902 mdelay(20);
2903
2904 for (i = 0; i < 10; i++) {
2905 u8 result = sdp_io_read(sd, 0xdb);
2906 if (result & 0x10) {
2907 complete++;
2908 if (result & 0x20)
2909 fail++;
2910 else
2911 pass++;
2912 }
2913 mdelay(20);
2914 }
2915
2916 v4l2_dbg(1, debug, sd,
2917 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2918 complete, i, pass, fail);
2919
2920 if (!complete || fail)
2921 return -EIO;
2922 return 0;
2923 }
2924
2925 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2926 struct adv7842_platform_data *pdata)
2927 {
2928 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2929 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2930 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2931 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2932 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2933
2934 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2935 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2936 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2937 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2938
2939 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2940 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2941 }
2942
2943 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2944 {
2945 struct i2c_client *client = v4l2_get_subdevdata(sd);
2946 struct adv7842_state *state = to_state(sd);
2947 struct adv7842_platform_data *pdata = client->dev.platform_data;
2948 struct v4l2_dv_timings timings;
2949 int ret = 0;
2950
2951 if (!pdata)
2952 return -ENODEV;
2953
2954 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2955 v4l2_info(sd, "no sdram or no ddr sdram\n");
2956 return -EINVAL;
2957 }
2958
2959 main_reset(sd);
2960
2961 adv7842_rewrite_i2c_addresses(sd, pdata);
2962
2963 /* run ram test */
2964 ret = adv7842_ddr_ram_test(sd);
2965
2966 main_reset(sd);
2967
2968 adv7842_rewrite_i2c_addresses(sd, pdata);
2969
2970 /* and re-init chip and state */
2971 adv7842_core_init(sd);
2972
2973 disable_input(sd);
2974
2975 select_input(sd, state->vid_std_select);
2976
2977 enable_input(sd);
2978
2979 edid_write_vga_segment(sd);
2980 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
2981 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
2982
2983 timings = state->timings;
2984
2985 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
2986
2987 adv7842_s_dv_timings(sd, &timings);
2988
2989 return ret;
2990 }
2991
2992 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2993 {
2994 switch (cmd) {
2995 case ADV7842_CMD_RAM_TEST:
2996 return adv7842_command_ram_test(sd);
2997 }
2998 return -ENOTTY;
2999 }
3000
3001 /* ----------------------------------------------------------------------- */
3002
3003 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3004 .s_ctrl = adv7842_s_ctrl,
3005 };
3006
3007 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3008 .log_status = adv7842_log_status,
3009 .ioctl = adv7842_ioctl,
3010 .interrupt_service_routine = adv7842_isr,
3011 #ifdef CONFIG_VIDEO_ADV_DEBUG
3012 .g_register = adv7842_g_register,
3013 .s_register = adv7842_s_register,
3014 #endif
3015 };
3016
3017 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
3018 .g_std = adv7842_g_std,
3019 .s_std = adv7842_s_std,
3020 .s_routing = adv7842_s_routing,
3021 .querystd = adv7842_querystd,
3022 .g_input_status = adv7842_g_input_status,
3023 .s_dv_timings = adv7842_s_dv_timings,
3024 .g_dv_timings = adv7842_g_dv_timings,
3025 .query_dv_timings = adv7842_query_dv_timings,
3026 };
3027
3028 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
3029 .enum_mbus_code = adv7842_enum_mbus_code,
3030 .get_fmt = adv7842_get_format,
3031 .set_fmt = adv7842_set_format,
3032 .get_edid = adv7842_get_edid,
3033 .set_edid = adv7842_set_edid,
3034 .enum_dv_timings = adv7842_enum_dv_timings,
3035 .dv_timings_cap = adv7842_dv_timings_cap,
3036 };
3037
3038 static const struct v4l2_subdev_ops adv7842_ops = {
3039 .core = &adv7842_core_ops,
3040 .video = &adv7842_video_ops,
3041 .pad = &adv7842_pad_ops,
3042 };
3043
3044 /* -------------------------- custom ctrls ---------------------------------- */
3045
3046 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3047 .ops = &adv7842_ctrl_ops,
3048 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3049 .name = "Analog Sampling Phase",
3050 .type = V4L2_CTRL_TYPE_INTEGER,
3051 .min = 0,
3052 .max = 0x1f,
3053 .step = 1,
3054 .def = 0,
3055 };
3056
3057 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3058 .ops = &adv7842_ctrl_ops,
3059 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3060 .name = "Free Running Color, Manual",
3061 .type = V4L2_CTRL_TYPE_BOOLEAN,
3062 .max = 1,
3063 .step = 1,
3064 .def = 1,
3065 };
3066
3067 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3068 .ops = &adv7842_ctrl_ops,
3069 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3070 .name = "Free Running Color",
3071 .type = V4L2_CTRL_TYPE_INTEGER,
3072 .max = 0xffffff,
3073 .step = 0x1,
3074 };
3075
3076
3077 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3078 {
3079 struct adv7842_state *state = to_state(sd);
3080 if (state->i2c_avlink)
3081 i2c_unregister_device(state->i2c_avlink);
3082 if (state->i2c_cec)
3083 i2c_unregister_device(state->i2c_cec);
3084 if (state->i2c_infoframe)
3085 i2c_unregister_device(state->i2c_infoframe);
3086 if (state->i2c_sdp_io)
3087 i2c_unregister_device(state->i2c_sdp_io);
3088 if (state->i2c_sdp)
3089 i2c_unregister_device(state->i2c_sdp);
3090 if (state->i2c_afe)
3091 i2c_unregister_device(state->i2c_afe);
3092 if (state->i2c_repeater)
3093 i2c_unregister_device(state->i2c_repeater);
3094 if (state->i2c_edid)
3095 i2c_unregister_device(state->i2c_edid);
3096 if (state->i2c_hdmi)
3097 i2c_unregister_device(state->i2c_hdmi);
3098 if (state->i2c_cp)
3099 i2c_unregister_device(state->i2c_cp);
3100 if (state->i2c_vdp)
3101 i2c_unregister_device(state->i2c_vdp);
3102
3103 state->i2c_avlink = NULL;
3104 state->i2c_cec = NULL;
3105 state->i2c_infoframe = NULL;
3106 state->i2c_sdp_io = NULL;
3107 state->i2c_sdp = NULL;
3108 state->i2c_afe = NULL;
3109 state->i2c_repeater = NULL;
3110 state->i2c_edid = NULL;
3111 state->i2c_hdmi = NULL;
3112 state->i2c_cp = NULL;
3113 state->i2c_vdp = NULL;
3114 }
3115
3116 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3117 u8 addr, u8 io_reg)
3118 {
3119 struct i2c_client *client = v4l2_get_subdevdata(sd);
3120 struct i2c_client *cp;
3121
3122 io_write(sd, io_reg, addr << 1);
3123
3124 if (addr == 0) {
3125 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3126 return NULL;
3127 }
3128
3129 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
3130 if (!cp)
3131 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
3132
3133 return cp;
3134 }
3135
3136 static int adv7842_register_clients(struct v4l2_subdev *sd)
3137 {
3138 struct adv7842_state *state = to_state(sd);
3139 struct adv7842_platform_data *pdata = &state->pdata;
3140
3141 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3142 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3143 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3144 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3145 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3146 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3147 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3148 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3149 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3150 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3151 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3152
3153 if (!state->i2c_avlink ||
3154 !state->i2c_cec ||
3155 !state->i2c_infoframe ||
3156 !state->i2c_sdp_io ||
3157 !state->i2c_sdp ||
3158 !state->i2c_afe ||
3159 !state->i2c_repeater ||
3160 !state->i2c_edid ||
3161 !state->i2c_hdmi ||
3162 !state->i2c_cp ||
3163 !state->i2c_vdp)
3164 return -1;
3165
3166 return 0;
3167 }
3168
3169 static int adv7842_probe(struct i2c_client *client,
3170 const struct i2c_device_id *id)
3171 {
3172 struct adv7842_state *state;
3173 static const struct v4l2_dv_timings cea640x480 =
3174 V4L2_DV_BT_CEA_640X480P59_94;
3175 struct adv7842_platform_data *pdata = client->dev.platform_data;
3176 struct v4l2_ctrl_handler *hdl;
3177 struct v4l2_subdev *sd;
3178 u16 rev;
3179 int err;
3180
3181 /* Check if the adapter supports the needed features */
3182 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3183 return -EIO;
3184
3185 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3186 client->addr << 1);
3187
3188 if (!pdata) {
3189 v4l_err(client, "No platform data!\n");
3190 return -ENODEV;
3191 }
3192
3193 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
3194 if (!state) {
3195 v4l_err(client, "Could not allocate adv7842_state memory!\n");
3196 return -ENOMEM;
3197 }
3198
3199 /* platform data */
3200 state->pdata = *pdata;
3201 state->timings = cea640x480;
3202 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3203
3204 sd = &state->sd;
3205 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3206 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
3207 state->mode = pdata->mode;
3208
3209 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3210 state->restart_stdi_once = true;
3211
3212 /* i2c access to adv7842? */
3213 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3214 adv_smbus_read_byte_data_check(client, 0xeb, false);
3215 if (rev != 0x2012) {
3216 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3217 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3218 adv_smbus_read_byte_data_check(client, 0xeb, false);
3219 }
3220 if (rev != 0x2012) {
3221 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3222 client->addr << 1, rev);
3223 return -ENODEV;
3224 }
3225
3226 if (pdata->chip_reset)
3227 main_reset(sd);
3228
3229 /* control handlers */
3230 hdl = &state->hdl;
3231 v4l2_ctrl_handler_init(hdl, 6);
3232
3233 /* add in ascending ID order */
3234 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3235 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3236 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3237 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3238 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3239 V4L2_CID_SATURATION, 0, 255, 1, 128);
3240 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3241 V4L2_CID_HUE, 0, 128, 1, 0);
3242
3243 /* custom controls */
3244 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3245 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3246 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3247 &adv7842_ctrl_analog_sampling_phase, NULL);
3248 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3249 &adv7842_ctrl_free_run_color_manual, NULL);
3250 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3251 &adv7842_ctrl_free_run_color, NULL);
3252 state->rgb_quantization_range_ctrl =
3253 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3254 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3255 0, V4L2_DV_RGB_RANGE_AUTO);
3256 sd->ctrl_handler = hdl;
3257 if (hdl->error) {
3258 err = hdl->error;
3259 goto err_hdl;
3260 }
3261 state->detect_tx_5v_ctrl->is_private = true;
3262 state->rgb_quantization_range_ctrl->is_private = true;
3263 state->analog_sampling_phase_ctrl->is_private = true;
3264 state->free_run_color_ctrl_manual->is_private = true;
3265 state->free_run_color_ctrl->is_private = true;
3266
3267 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3268 err = -ENODEV;
3269 goto err_hdl;
3270 }
3271
3272 if (adv7842_register_clients(sd) < 0) {
3273 err = -ENOMEM;
3274 v4l2_err(sd, "failed to create all i2c clients\n");
3275 goto err_i2c;
3276 }
3277
3278 /* work queues */
3279 state->work_queues = create_singlethread_workqueue(client->name);
3280 if (!state->work_queues) {
3281 v4l2_err(sd, "Could not create work queue\n");
3282 err = -ENOMEM;
3283 goto err_i2c;
3284 }
3285
3286 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3287 adv7842_delayed_work_enable_hotplug);
3288
3289 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3290 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
3291 if (err)
3292 goto err_work_queues;
3293
3294 err = adv7842_core_init(sd);
3295 if (err)
3296 goto err_entity;
3297
3298 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3299 client->addr << 1, client->adapter->name);
3300 return 0;
3301
3302 err_entity:
3303 media_entity_cleanup(&sd->entity);
3304 err_work_queues:
3305 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3306 destroy_workqueue(state->work_queues);
3307 err_i2c:
3308 adv7842_unregister_clients(sd);
3309 err_hdl:
3310 v4l2_ctrl_handler_free(hdl);
3311 return err;
3312 }
3313
3314 /* ----------------------------------------------------------------------- */
3315
3316 static int adv7842_remove(struct i2c_client *client)
3317 {
3318 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3319 struct adv7842_state *state = to_state(sd);
3320
3321 adv7842_irq_enable(sd, false);
3322
3323 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3324 destroy_workqueue(state->work_queues);
3325 v4l2_device_unregister_subdev(sd);
3326 media_entity_cleanup(&sd->entity);
3327 adv7842_unregister_clients(sd);
3328 v4l2_ctrl_handler_free(sd->ctrl_handler);
3329 return 0;
3330 }
3331
3332 /* ----------------------------------------------------------------------- */
3333
3334 static struct i2c_device_id adv7842_id[] = {
3335 { "adv7842", 0 },
3336 { }
3337 };
3338 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3339
3340 /* ----------------------------------------------------------------------- */
3341
3342 static struct i2c_driver adv7842_driver = {
3343 .driver = {
3344 .owner = THIS_MODULE,
3345 .name = "adv7842",
3346 },
3347 .probe = adv7842_probe,
3348 .remove = adv7842_remove,
3349 .id_table = adv7842_id,
3350 };
3351
3352 module_i2c_driver(adv7842_driver);
ubuntu-zesty-kernel mirror