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[mirror_ubuntu-jammy-kernel.git] / drivers / media / i2c / hm11b1.c
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020-2021 Intel Corporation.
3
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
13 #include "power_ctrl_logic.h"
14
15 #define HM11B1_LINK_FREQ_384MHZ 384000000ULL
16 #define HM11B1_SCLK 72000000LL
17 #define HM11B1_MCLK 19200000
18 #define HM11B1_DATA_LANES 1
19 #define HM11B1_RGB_DEPTH 10
20
21 #define HM11B1_REG_CHIP_ID 0x0000
22 #define HM11B1_CHIP_ID 0x11B1
23
24 #define HM11B1_REG_MODE_SELECT 0x0100
25 #define HM11B1_MODE_STANDBY 0x00
26 #define HM11B1_MODE_STREAMING 0x01
27
28 /* vertical-timings from sensor */
29 #define HM11B1_REG_VTS 0x3402
30 #define HM11B1_VTS_DEF 0x037d
31 #define HM11B1_VTS_MIN 0x0346
32 #define HM11B1_VTS_MAX 0xffff
33
34 /* horizontal-timings from sensor */
35 #define HM11B1_REG_HTS 0x3404
36
37 /* Exposure controls from sensor */
38 #define HM11B1_REG_EXPOSURE 0x0202
39 #define HM11B1_EXPOSURE_MIN 2
40 #define HM11B1_EXPOSURE_MAX_MARGIN 2
41 #define HM11B1_EXPOSURE_STEP 1
42
43 /* Analog gain controls from sensor */
44 #define HM11B1_REG_ANALOG_GAIN 0x0205
45 #define HM11B1_REG_ANALOG_GAIN_IR 0x0206
46 #define HM11B1_ANAL_GAIN_MIN 0
47 #define HM11B1_ANAL_GAIN_MAX 0xFF
48 #define HM11B1_ANAL_GAIN_STEP 1
49
50 /* Digital gain controls from sensor */
51 #define HM11B1_REG_DGTL_GAIN 0x0207
52 #define HM11B1_REG_DGTL_GAIN_IR 0x0209
53 #define HM11B1_DGTL_GAIN_MIN 0x0
54 #define HM11B1_DGTL_GAIN_MAX 0x3FF
55 #define HM11B1_DGTL_GAIN_STEP 1
56 #define HM11B1_DGTL_GAIN_DEFAULT 0x100
57 /* register update control */
58 #define HM11B1_REG_COMMAND_UPDATE 0x104
59
60 /* Test Pattern Control */
61 #define HM11B1_REG_TEST_PATTERN 0x0601
62 #define HM11B1_TEST_PATTERN_ENABLE 1
63 #define HM11B1_TEST_PATTERN_BAR_SHIFT 1
64
65 enum {
66 HM11B1_LINK_FREQ_384MHZ_INDEX,
67 };
68
69 struct hm11b1_reg {
70 u16 address;
71 u8 val;
72 };
73
74 struct hm11b1_reg_list {
75 u32 num_of_regs;
76 const struct hm11b1_reg *regs;
77 };
78
79 struct hm11b1_link_freq_config {
80 const struct hm11b1_reg_list reg_list;
81 };
82
83 struct hm11b1_mode {
84 /* Frame width in pixels */
85 u32 width;
86
87 /* Frame height in pixels */
88 u32 height;
89
90 /* Horizontal timining size */
91 u32 hts;
92
93 /* Default vertical timining size */
94 u32 vts_def;
95
96 /* Min vertical timining size */
97 u32 vts_min;
98
99 /* Link frequency needed for this resolution */
100 u32 link_freq_index;
101
102 /* Sensor register settings for this resolution */
103 const struct hm11b1_reg_list reg_list;
104 };
105
106 static const struct hm11b1_reg mipi_data_rate_384mbps[] = {
107 };
108
109 //RAW 10bit 1292x800_30fps_MIPI 384Mbps/lane
110 static const struct hm11b1_reg sensor_1292x800_30fps_setting[] = {
111 {0x0103, 0x00},
112 {0x0102, 0x01},
113 {0x0202, 0x03},
114 {0x0203, 0x7C},
115 {0x0205, 0x20},
116 {0x0207, 0x01},
117 {0x0208, 0x00},
118 {0x0209, 0x01},
119 {0x020A, 0x00},
120 {0x0300, 0x91},
121 {0x0301, 0x0A},
122 {0x0302, 0x02},
123 {0x0303, 0x2E},
124 {0x0304, 0x43},
125 {0x0306, 0x00},
126 {0x0307, 0x00},
127 {0x0340, 0x03},
128 {0x0341, 0x60},
129 {0x0342, 0x05},
130 {0x0343, 0xA0},
131 {0x0344, 0x00},
132 {0x0345, 0x00},
133 {0x0346, 0x03},
134 {0x0347, 0x2F},
135 {0x0350, 0xFF},
136 {0x0351, 0x00},
137 {0x0352, 0x00},
138 {0x0370, 0x00},
139 {0x0371, 0x00},
140 {0x0380, 0x00},
141 {0x0381, 0x00},
142 {0x0382, 0x00},
143 {0x1000, 0xC3},
144 {0x1001, 0xD0},
145 {0x100A, 0x13},
146 {0x2000, 0x00},
147 {0x2061, 0x01},
148 {0x2062, 0x00},
149 {0x2063, 0xC8},
150 {0x2100, 0x03},
151 {0x2101, 0xF0},
152 {0x2102, 0xF0},
153 {0x2103, 0x01},
154 {0x2104, 0x10},
155 {0x2105, 0x10},
156 {0x2106, 0x02},
157 {0x2107, 0x0A},
158 {0x2108, 0x10},
159 {0x2109, 0x15},
160 {0x210A, 0x1A},
161 {0x210B, 0x20},
162 {0x210C, 0x08},
163 {0x210D, 0x0A},
164 {0x210E, 0x0F},
165 {0x210F, 0x12},
166 {0x2110, 0x1C},
167 {0x2111, 0x20},
168 {0x2112, 0x23},
169 {0x2113, 0x2A},
170 {0x2114, 0x30},
171 {0x2115, 0x10},
172 {0x2116, 0x00},
173 {0x2117, 0x01},
174 {0x2118, 0x00},
175 {0x2119, 0x06},
176 {0x211A, 0x00},
177 {0x211B, 0x00},
178 {0x2615, 0x08},
179 {0x2616, 0x00},
180 {0x2700, 0x01},
181 {0x2711, 0x01},
182 {0x272F, 0x01},
183 {0x2800, 0x29},
184 {0x2821, 0xCE},
185 {0x2839, 0x27},
186 {0x283A, 0x01},
187 {0x2842, 0x01},
188 {0x2843, 0x00},
189 {0x3022, 0x11},
190 {0x3024, 0x30},
191 {0x3025, 0x12},
192 {0x3026, 0x00},
193 {0x3027, 0x81},
194 {0x3028, 0x01},
195 {0x3029, 0x00},
196 {0x302A, 0x30},
197 {0x3030, 0x00},
198 {0x3032, 0x00},
199 {0x3035, 0x01},
200 {0x303E, 0x00},
201 {0x3051, 0x00},
202 {0x3082, 0x0E},
203 {0x3084, 0x0D},
204 {0x30A8, 0x03},
205 {0x30C4, 0xA0},
206 {0x30D5, 0xC1},
207 {0x30D8, 0x00},
208 {0x30D9, 0x0D},
209 {0x30DB, 0xC2},
210 {0x30DE, 0x25},
211 {0x30E1, 0xC3},
212 {0x30E4, 0x25},
213 {0x30E7, 0xC4},
214 {0x30EA, 0x25},
215 {0x30ED, 0xC5},
216 {0x30F0, 0x25},
217 {0x30F2, 0x0C},
218 {0x30F3, 0x85},
219 {0x30F6, 0x25},
220 {0x30F8, 0x0C},
221 {0x30F9, 0x05},
222 {0x30FB, 0x40},
223 {0x30FC, 0x25},
224 {0x30FD, 0x54},
225 {0x30FE, 0x0C},
226 {0x3100, 0xC2},
227 {0x3103, 0x00},
228 {0x3104, 0x2B},
229 {0x3106, 0xC3},
230 {0x3109, 0x25},
231 {0x310C, 0xC4},
232 {0x310F, 0x25},
233 {0x3112, 0xC5},
234 {0x3115, 0x25},
235 {0x3117, 0x0C},
236 {0x3118, 0x85},
237 {0x311B, 0x25},
238 {0x311D, 0x0C},
239 {0x311E, 0x05},
240 {0x3121, 0x25},
241 {0x3123, 0x0C},
242 {0x3124, 0x0D},
243 {0x3126, 0x40},
244 {0x3127, 0x25},
245 {0x3128, 0x54},
246 {0x3129, 0x0C},
247 {0x3130, 0x20},
248 {0x3134, 0x60},
249 {0x3135, 0xC2},
250 {0x3139, 0x12},
251 {0x313A, 0x07},
252 {0x313F, 0x52},
253 {0x3140, 0x34},
254 {0x3141, 0x2E},
255 {0x314F, 0x07},
256 {0x3151, 0x47},
257 {0x3153, 0xB0},
258 {0x3154, 0x4A},
259 {0x3155, 0xC0},
260 {0x3157, 0x55},
261 {0x3158, 0x01},
262 {0x3165, 0xFF},
263 {0x316B, 0x12},
264 {0x316E, 0x12},
265 {0x3176, 0x12},
266 {0x3178, 0x01},
267 {0x317C, 0x10},
268 {0x317D, 0x05},
269 {0x317F, 0x07},
270 {0x3182, 0x07},
271 {0x3183, 0x11},
272 {0x3184, 0x88},
273 {0x3186, 0x28},
274 {0x3191, 0x00},
275 {0x3192, 0x20},
276 {0x3400, 0x48},
277 {0x3401, 0x00},
278 {0x3402, 0x06},
279 {0x3403, 0xFA},
280 {0x3404, 0x05},
281 {0x3405, 0x40},
282 {0x3406, 0x00},
283 {0x3407, 0x00},
284 {0x3408, 0x03},
285 {0x3409, 0x2F},
286 {0x340A, 0x00},
287 {0x340B, 0x00},
288 {0x340C, 0x00},
289 {0x340D, 0x00},
290 {0x340E, 0x00},
291 {0x340F, 0x00},
292 {0x3410, 0x00},
293 {0x3411, 0x01},
294 {0x3412, 0x00},
295 {0x3413, 0x03},
296 {0x3414, 0xB0},
297 {0x3415, 0x4A},
298 {0x3416, 0xC0},
299 {0x3418, 0x55},
300 {0x3419, 0x03},
301 {0x341B, 0x7D},
302 {0x341C, 0x00},
303 {0x341F, 0x03},
304 {0x3420, 0x00},
305 {0x3421, 0x02},
306 {0x3422, 0x00},
307 {0x3423, 0x02},
308 {0x3424, 0x01},
309 {0x3425, 0x02},
310 {0x3426, 0x00},
311 {0x3427, 0xA2},
312 {0x3428, 0x01},
313 {0x3429, 0x06},
314 {0x342A, 0xF8},
315 {0x3440, 0x01},
316 {0x3441, 0xBE},
317 {0x3442, 0x02},
318 {0x3443, 0x18},
319 {0x3444, 0x03},
320 {0x3445, 0x0C},
321 {0x3446, 0x06},
322 {0x3447, 0x18},
323 {0x3448, 0x09},
324 {0x3449, 0x24},
325 {0x344A, 0x08},
326 {0x344B, 0x08},
327 {0x345C, 0x00},
328 {0x345D, 0x44},
329 {0x345E, 0x02},
330 {0x345F, 0x43},
331 {0x3460, 0x04},
332 {0x3461, 0x3B},
333 {0x3466, 0xF8},
334 {0x3467, 0x43},
335 {0x347D, 0x02},
336 {0x3483, 0x05},
337 {0x3484, 0x0C},
338 {0x3485, 0x03},
339 {0x3486, 0x20},
340 {0x3487, 0x00},
341 {0x3488, 0x00},
342 {0x3489, 0x00},
343 {0x348A, 0x09},
344 {0x348B, 0x00},
345 {0x348C, 0x00},
346 {0x348D, 0x02},
347 {0x348E, 0x01},
348 {0x348F, 0x40},
349 {0x3490, 0x00},
350 {0x3491, 0xC8},
351 {0x3492, 0x00},
352 {0x3493, 0x02},
353 {0x3494, 0x00},
354 {0x3495, 0x02},
355 {0x3496, 0x02},
356 {0x3497, 0x06},
357 {0x3498, 0x05},
358 {0x3499, 0x04},
359 {0x349A, 0x09},
360 {0x349B, 0x05},
361 {0x349C, 0x17},
362 {0x349D, 0x05},
363 {0x349E, 0x00},
364 {0x349F, 0x00},
365 {0x34A0, 0x00},
366 {0x34A1, 0x00},
367 {0x34A2, 0x08},
368 {0x34A3, 0x08},
369 {0x34A4, 0x00},
370 {0x34A5, 0x0B},
371 {0x34A6, 0x0C},
372 {0x34A7, 0x32},
373 {0x34A8, 0x10},
374 {0x34A9, 0xE0},
375 {0x34AA, 0x52},
376 {0x34AB, 0x00},
377 {0x34AC, 0x60},
378 {0x34AD, 0x2B},
379 {0x34AE, 0x25},
380 {0x34AF, 0x48},
381 {0x34B1, 0x06},
382 {0x34B2, 0xF8},
383 {0x34C3, 0xB0},
384 {0x34C4, 0x4A},
385 {0x34C5, 0xC0},
386 {0x34C7, 0x55},
387 {0x34C8, 0x03},
388 {0x34CB, 0x00},
389 {0x353A, 0x00},
390 {0x355E, 0x48},
391 {0x3572, 0xB0},
392 {0x3573, 0x4A},
393 {0x3574, 0xC0},
394 {0x3576, 0x55},
395 {0x3577, 0x03},
396 {0x357A, 0x00},
397 {0x35DA, 0x00},
398 {0x4003, 0x02},
399 {0x4004, 0x02},
400 };
401
402 static const char * const hm11b1_test_pattern_menu[] = {
403 "Disabled",
404 "Solid Color",
405 "Color Bar",
406 "Color Bar Blending",
407 "PN11",
408 };
409
410 static const s64 link_freq_menu_items[] = {
411 HM11B1_LINK_FREQ_384MHZ,
412 };
413
414 static const struct hm11b1_link_freq_config link_freq_configs[] = {
415 [HM11B1_LINK_FREQ_384MHZ_INDEX] = {
416 .reg_list = {
417 .num_of_regs = ARRAY_SIZE(mipi_data_rate_384mbps),
418 .regs = mipi_data_rate_384mbps,
419 }
420 },
421 };
422
423 static const struct hm11b1_mode supported_modes[] = {
424 {
425 .width = 1292,
426 .height = 800,
427 .hts = 1344,
428 .vts_def = HM11B1_VTS_DEF,
429 .vts_min = HM11B1_VTS_MIN,
430 .reg_list = {
431 .num_of_regs =
432 ARRAY_SIZE(sensor_1292x800_30fps_setting),
433 .regs = sensor_1292x800_30fps_setting,
434 },
435 .link_freq_index = HM11B1_LINK_FREQ_384MHZ_INDEX,
436 },
437 };
438
439 struct hm11b1 {
440 struct v4l2_subdev sd;
441 struct media_pad pad;
442 struct v4l2_ctrl_handler ctrl_handler;
443
444 /* V4L2 Controls */
445 struct v4l2_ctrl *link_freq;
446 struct v4l2_ctrl *pixel_rate;
447 struct v4l2_ctrl *vblank;
448 struct v4l2_ctrl *hblank;
449 struct v4l2_ctrl *exposure;
450
451 /* Current mode */
452 const struct hm11b1_mode *cur_mode;
453
454 /* To serialize asynchronus callbacks */
455 struct mutex mutex;
456
457 /* Streaming on/off */
458 bool streaming;
459 };
460
461 static inline struct hm11b1 *to_hm11b1(struct v4l2_subdev *subdev)
462 {
463 return container_of(subdev, struct hm11b1, sd);
464 }
465
466 static u64 to_pixel_rate(u32 f_index)
467 {
468 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * HM11B1_DATA_LANES;
469
470 do_div(pixel_rate, HM11B1_RGB_DEPTH);
471
472 return pixel_rate;
473 }
474
475 static u64 to_pixels_per_line(u32 hts, u32 f_index)
476 {
477 u64 ppl = hts * to_pixel_rate(f_index);
478
479 do_div(ppl, HM11B1_SCLK);
480
481 return ppl;
482 }
483
484 static int hm11b1_read_reg(struct hm11b1 *hm11b1, u16 reg, u16 len, u32 *val)
485 {
486 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
487 struct i2c_msg msgs[2];
488 u8 addr_buf[2];
489 u8 data_buf[4] = {0};
490 int ret = 0;
491
492 if (len > sizeof(data_buf))
493 return -EINVAL;
494
495 put_unaligned_be16(reg, addr_buf);
496 msgs[0].addr = client->addr;
497 msgs[0].flags = 0;
498 msgs[0].len = sizeof(addr_buf);
499 msgs[0].buf = addr_buf;
500 msgs[1].addr = client->addr;
501 msgs[1].flags = I2C_M_RD;
502 msgs[1].len = len;
503 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
504
505 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
506 if (ret != ARRAY_SIZE(msgs))
507 return ret < 0 ? ret : -EIO;
508
509 *val = get_unaligned_be32(data_buf);
510
511 return 0;
512 }
513
514 static int hm11b1_write_reg(struct hm11b1 *hm11b1, u16 reg, u16 len, u32 val)
515 {
516 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
517 u8 buf[6];
518 int ret = 0;
519
520 if (len > 4)
521 return -EINVAL;
522
523 put_unaligned_be16(reg, buf);
524 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
525
526 ret = i2c_master_send(client, buf, len + 2);
527 if (ret != len + 2)
528 return ret < 0 ? ret : -EIO;
529
530 return 0;
531 }
532
533 static int hm11b1_write_reg_list(struct hm11b1 *hm11b1,
534 const struct hm11b1_reg_list *r_list)
535 {
536 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
537 unsigned int i;
538 int ret = 0;
539
540 for (i = 0; i < r_list->num_of_regs; i++) {
541 ret = hm11b1_write_reg(hm11b1, r_list->regs[i].address, 1,
542 r_list->regs[i].val);
543 if (ret) {
544 dev_err_ratelimited(&client->dev,
545 "write reg 0x%4.4x return err = %d",
546 r_list->regs[i].address, ret);
547 return ret;
548 }
549 }
550
551 return 0;
552 }
553
554 static int hm11b1_update_digital_gain(struct hm11b1 *hm11b1, u32 d_gain)
555 {
556 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
557 int ret = 0;
558
559 ret = hm11b1_write_reg(hm11b1, HM11B1_REG_DGTL_GAIN, 2, d_gain);
560 if (ret) {
561 dev_err(&client->dev, "failed to set HM11B1_REG_DGTL_GAIN");
562 return ret;
563 }
564
565 ret = hm11b1_write_reg(hm11b1, HM11B1_REG_DGTL_GAIN_IR, 2, d_gain);
566 if (ret) {
567 dev_err(&client->dev, "failed to set HM11B1_REG_DGTL_GAIN_IR");
568 return ret;
569 }
570
571 return ret;
572 }
573
574 static int hm11b1_test_pattern(struct hm11b1 *hm11b1, u32 pattern)
575 {
576 if (pattern)
577 pattern = pattern << HM11B1_TEST_PATTERN_BAR_SHIFT |
578 HM11B1_TEST_PATTERN_ENABLE;
579
580 return hm11b1_write_reg(hm11b1, HM11B1_REG_TEST_PATTERN, 1, pattern);
581 }
582
583 static int hm11b1_set_ctrl(struct v4l2_ctrl *ctrl)
584 {
585 struct hm11b1 *hm11b1 = container_of(ctrl->handler,
586 struct hm11b1, ctrl_handler);
587 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
588 s64 exposure_max;
589 int ret = 0;
590
591 /* Propagate change of current control to all related controls */
592 if (ctrl->id == V4L2_CID_VBLANK) {
593 /* Update max exposure while meeting expected vblanking */
594 exposure_max = hm11b1->cur_mode->height + ctrl->val -
595 HM11B1_EXPOSURE_MAX_MARGIN;
596 __v4l2_ctrl_modify_range(hm11b1->exposure,
597 hm11b1->exposure->minimum,
598 exposure_max, hm11b1->exposure->step,
599 exposure_max);
600 }
601
602 /* V4L2 controls values will be applied only when power is already up */
603 if (!pm_runtime_get_if_in_use(&client->dev))
604 return 0;
605
606 ret = hm11b1_write_reg(hm11b1, HM11B1_REG_COMMAND_UPDATE, 1, 1);
607 if (ret) {
608 dev_err(&client->dev, "failed to enable HM11B1_REG_COMMAND_UPDATE");
609 pm_runtime_put(&client->dev);
610 return ret;
611 }
612 switch (ctrl->id) {
613 case V4L2_CID_ANALOGUE_GAIN:
614 ret = hm11b1_write_reg(hm11b1, HM11B1_REG_ANALOG_GAIN, 1,
615 ctrl->val);
616 ret |= hm11b1_write_reg(hm11b1, HM11B1_REG_ANALOG_GAIN_IR, 1,
617 ctrl->val);
618 break;
619
620 case V4L2_CID_DIGITAL_GAIN:
621 ret = hm11b1_update_digital_gain(hm11b1, ctrl->val);
622 break;
623
624 case V4L2_CID_EXPOSURE:
625 /* 4 least significant bits of expsoure are fractional part */
626 ret = hm11b1_write_reg(hm11b1, HM11B1_REG_EXPOSURE, 2,
627 ctrl->val);
628 break;
629
630 case V4L2_CID_VBLANK:
631 ret = hm11b1_write_reg(hm11b1, HM11B1_REG_VTS, 2,
632 hm11b1->cur_mode->height + ctrl->val);
633 break;
634
635 case V4L2_CID_TEST_PATTERN:
636 ret = hm11b1_test_pattern(hm11b1, ctrl->val);
637 break;
638
639 default:
640 ret = -EINVAL;
641 break;
642 }
643
644 ret |= hm11b1_write_reg(hm11b1, HM11B1_REG_COMMAND_UPDATE, 1, 0);
645 pm_runtime_put(&client->dev);
646
647 return ret;
648 }
649
650 static const struct v4l2_ctrl_ops hm11b1_ctrl_ops = {
651 .s_ctrl = hm11b1_set_ctrl,
652 };
653
654 static int hm11b1_init_controls(struct hm11b1 *hm11b1)
655 {
656 struct v4l2_ctrl_handler *ctrl_hdlr;
657 const struct hm11b1_mode *cur_mode;
658 s64 exposure_max, h_blank, pixel_rate;
659 u32 vblank_min, vblank_max, vblank_default;
660 int size;
661 int ret = 0;
662
663 ctrl_hdlr = &hm11b1->ctrl_handler;
664 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
665 if (ret)
666 return ret;
667
668 ctrl_hdlr->lock = &hm11b1->mutex;
669 cur_mode = hm11b1->cur_mode;
670 size = ARRAY_SIZE(link_freq_menu_items);
671
672 hm11b1->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &hm11b1_ctrl_ops,
673 V4L2_CID_LINK_FREQ,
674 size - 1, 0,
675 link_freq_menu_items);
676 if (hm11b1->link_freq)
677 hm11b1->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
678
679 pixel_rate = to_pixel_rate(HM11B1_LINK_FREQ_384MHZ_INDEX);
680 hm11b1->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &hm11b1_ctrl_ops,
681 V4L2_CID_PIXEL_RATE, 0,
682 pixel_rate, 1, pixel_rate);
683
684 vblank_min = cur_mode->vts_min - cur_mode->height;
685 vblank_max = HM11B1_VTS_MAX - cur_mode->height;
686 vblank_default = cur_mode->vts_def - cur_mode->height;
687 hm11b1->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &hm11b1_ctrl_ops,
688 V4L2_CID_VBLANK, vblank_min,
689 vblank_max, 1, vblank_default);
690
691 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
692 h_blank -= cur_mode->width;
693 hm11b1->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &hm11b1_ctrl_ops,
694 V4L2_CID_HBLANK, h_blank, h_blank, 1,
695 h_blank);
696 if (hm11b1->hblank)
697 hm11b1->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
698
699 v4l2_ctrl_new_std(ctrl_hdlr, &hm11b1_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
700 HM11B1_ANAL_GAIN_MIN, HM11B1_ANAL_GAIN_MAX,
701 HM11B1_ANAL_GAIN_STEP, HM11B1_ANAL_GAIN_MIN);
702 v4l2_ctrl_new_std(ctrl_hdlr, &hm11b1_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
703 HM11B1_DGTL_GAIN_MIN, HM11B1_DGTL_GAIN_MAX,
704 HM11B1_DGTL_GAIN_STEP, HM11B1_DGTL_GAIN_DEFAULT);
705 exposure_max = cur_mode->vts_def - HM11B1_EXPOSURE_MAX_MARGIN;
706 hm11b1->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &hm11b1_ctrl_ops,
707 V4L2_CID_EXPOSURE,
708 HM11B1_EXPOSURE_MIN, exposure_max,
709 HM11B1_EXPOSURE_STEP,
710 exposure_max);
711 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &hm11b1_ctrl_ops,
712 V4L2_CID_TEST_PATTERN,
713 ARRAY_SIZE(hm11b1_test_pattern_menu) - 1,
714 0, 0, hm11b1_test_pattern_menu);
715 if (ctrl_hdlr->error)
716 return ctrl_hdlr->error;
717
718 hm11b1->sd.ctrl_handler = ctrl_hdlr;
719
720 return 0;
721 }
722
723 static void hm11b1_update_pad_format(const struct hm11b1_mode *mode,
724 struct v4l2_mbus_framefmt *fmt)
725 {
726 fmt->width = mode->width;
727 fmt->height = mode->height;
728 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
729 fmt->field = V4L2_FIELD_NONE;
730 }
731
732 static int hm11b1_start_streaming(struct hm11b1 *hm11b1)
733 {
734 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
735 const struct hm11b1_reg_list *reg_list;
736 int link_freq_index;
737 int ret = 0;
738
739 power_ctrl_logic_set_power(1);
740 link_freq_index = hm11b1->cur_mode->link_freq_index;
741 reg_list = &link_freq_configs[link_freq_index].reg_list;
742 ret = hm11b1_write_reg_list(hm11b1, reg_list);
743 if (ret) {
744 dev_err(&client->dev, "failed to set plls");
745 return ret;
746 }
747
748 reg_list = &hm11b1->cur_mode->reg_list;
749 ret = hm11b1_write_reg_list(hm11b1, reg_list);
750 if (ret) {
751 dev_err(&client->dev, "failed to set mode");
752 return ret;
753 }
754
755 ret = __v4l2_ctrl_handler_setup(hm11b1->sd.ctrl_handler);
756 if (ret)
757 return ret;
758
759 ret = hm11b1_write_reg(hm11b1, HM11B1_REG_MODE_SELECT, 1,
760 HM11B1_MODE_STREAMING);
761 if (ret)
762 dev_err(&client->dev, "failed to start streaming");
763
764 return ret;
765 }
766
767 static void hm11b1_stop_streaming(struct hm11b1 *hm11b1)
768 {
769 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
770
771 if (hm11b1_write_reg(hm11b1, HM11B1_REG_MODE_SELECT, 1,
772 HM11B1_MODE_STANDBY))
773 dev_err(&client->dev, "failed to stop streaming");
774 power_ctrl_logic_set_power(0);
775 }
776
777 static int hm11b1_set_stream(struct v4l2_subdev *sd, int enable)
778 {
779 struct hm11b1 *hm11b1 = to_hm11b1(sd);
780 struct i2c_client *client = v4l2_get_subdevdata(sd);
781 int ret = 0;
782
783 if (hm11b1->streaming == enable)
784 return 0;
785
786 mutex_lock(&hm11b1->mutex);
787 if (enable) {
788 ret = pm_runtime_get_sync(&client->dev);
789 if (ret < 0) {
790 pm_runtime_put_noidle(&client->dev);
791 mutex_unlock(&hm11b1->mutex);
792 return ret;
793 }
794
795 ret = hm11b1_start_streaming(hm11b1);
796 if (ret) {
797 enable = 0;
798 hm11b1_stop_streaming(hm11b1);
799 pm_runtime_put(&client->dev);
800 }
801 } else {
802 hm11b1_stop_streaming(hm11b1);
803 pm_runtime_put(&client->dev);
804 }
805
806 hm11b1->streaming = enable;
807 mutex_unlock(&hm11b1->mutex);
808
809 return ret;
810 }
811
812 static int __maybe_unused hm11b1_suspend(struct device *dev)
813 {
814 struct i2c_client *client = to_i2c_client(dev);
815 struct v4l2_subdev *sd = i2c_get_clientdata(client);
816 struct hm11b1 *hm11b1 = to_hm11b1(sd);
817
818 mutex_lock(&hm11b1->mutex);
819 if (hm11b1->streaming)
820 hm11b1_stop_streaming(hm11b1);
821
822 mutex_unlock(&hm11b1->mutex);
823
824 return 0;
825 }
826
827 static int __maybe_unused hm11b1_resume(struct device *dev)
828 {
829 struct i2c_client *client = to_i2c_client(dev);
830 struct v4l2_subdev *sd = i2c_get_clientdata(client);
831 struct hm11b1 *hm11b1 = to_hm11b1(sd);
832 int ret = 0;
833
834 mutex_lock(&hm11b1->mutex);
835 if (!hm11b1->streaming)
836 goto exit;
837
838 ret = hm11b1_start_streaming(hm11b1);
839 if (ret) {
840 hm11b1->streaming = false;
841 hm11b1_stop_streaming(hm11b1);
842 }
843
844 exit:
845 mutex_unlock(&hm11b1->mutex);
846 return ret;
847 }
848
849 static int hm11b1_set_format(struct v4l2_subdev *sd,
850 struct v4l2_subdev_pad_config *cfg,
851 struct v4l2_subdev_format *fmt)
852 {
853 struct hm11b1 *hm11b1 = to_hm11b1(sd);
854 const struct hm11b1_mode *mode;
855 s32 vblank_def, h_blank;
856
857 mode = v4l2_find_nearest_size(supported_modes,
858 ARRAY_SIZE(supported_modes), width,
859 height, fmt->format.width,
860 fmt->format.height);
861
862 mutex_lock(&hm11b1->mutex);
863 hm11b1_update_pad_format(mode, &fmt->format);
864 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
865 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
866 } else {
867 hm11b1->cur_mode = mode;
868 __v4l2_ctrl_s_ctrl(hm11b1->link_freq, mode->link_freq_index);
869 __v4l2_ctrl_s_ctrl_int64(hm11b1->pixel_rate,
870 to_pixel_rate(mode->link_freq_index));
871
872 /* Update limits and set FPS to default */
873 vblank_def = mode->vts_def - mode->height;
874 __v4l2_ctrl_modify_range(hm11b1->vblank,
875 mode->vts_min - mode->height,
876 HM11B1_VTS_MAX - mode->height, 1,
877 vblank_def);
878 __v4l2_ctrl_s_ctrl(hm11b1->vblank, vblank_def);
879 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
880 mode->width;
881 __v4l2_ctrl_modify_range(hm11b1->hblank, h_blank, h_blank, 1,
882 h_blank);
883 }
884 mutex_unlock(&hm11b1->mutex);
885
886 return 0;
887 }
888
889 static int hm11b1_get_format(struct v4l2_subdev *sd,
890 struct v4l2_subdev_pad_config *cfg,
891 struct v4l2_subdev_format *fmt)
892 {
893 struct hm11b1 *hm11b1 = to_hm11b1(sd);
894
895 mutex_lock(&hm11b1->mutex);
896 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
897 fmt->format = *v4l2_subdev_get_try_format(&hm11b1->sd, cfg,
898 fmt->pad);
899 else
900 hm11b1_update_pad_format(hm11b1->cur_mode, &fmt->format);
901
902 mutex_unlock(&hm11b1->mutex);
903
904 return 0;
905 }
906
907 static int hm11b1_enum_mbus_code(struct v4l2_subdev *sd,
908 struct v4l2_subdev_pad_config *cfg,
909 struct v4l2_subdev_mbus_code_enum *code)
910 {
911 if (code->index > 0)
912 return -EINVAL;
913
914 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
915
916 return 0;
917 }
918
919 static int hm11b1_enum_frame_size(struct v4l2_subdev *sd,
920 struct v4l2_subdev_pad_config *cfg,
921 struct v4l2_subdev_frame_size_enum *fse)
922 {
923 if (fse->index >= ARRAY_SIZE(supported_modes))
924 return -EINVAL;
925
926 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
927 return -EINVAL;
928
929 fse->min_width = supported_modes[fse->index].width;
930 fse->max_width = fse->min_width;
931 fse->min_height = supported_modes[fse->index].height;
932 fse->max_height = fse->min_height;
933
934 return 0;
935 }
936
937 static int hm11b1_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
938 {
939 struct hm11b1 *hm11b1 = to_hm11b1(sd);
940
941 mutex_lock(&hm11b1->mutex);
942 hm11b1_update_pad_format(&supported_modes[0],
943 v4l2_subdev_get_try_format(sd, fh->pad, 0));
944 mutex_unlock(&hm11b1->mutex);
945
946 return 0;
947 }
948
949 static const struct v4l2_subdev_video_ops hm11b1_video_ops = {
950 .s_stream = hm11b1_set_stream,
951 };
952
953 static const struct v4l2_subdev_pad_ops hm11b1_pad_ops = {
954 .set_fmt = hm11b1_set_format,
955 .get_fmt = hm11b1_get_format,
956 .enum_mbus_code = hm11b1_enum_mbus_code,
957 .enum_frame_size = hm11b1_enum_frame_size,
958 };
959
960 static const struct v4l2_subdev_ops hm11b1_subdev_ops = {
961 .video = &hm11b1_video_ops,
962 .pad = &hm11b1_pad_ops,
963 };
964
965 static const struct media_entity_operations hm11b1_subdev_entity_ops = {
966 .link_validate = v4l2_subdev_link_validate,
967 };
968
969 static const struct v4l2_subdev_internal_ops hm11b1_internal_ops = {
970 .open = hm11b1_open,
971 };
972
973 static int hm11b1_identify_module(struct hm11b1 *hm11b1)
974 {
975 struct i2c_client *client = v4l2_get_subdevdata(&hm11b1->sd);
976 int ret;
977 u32 val;
978
979 ret = hm11b1_read_reg(hm11b1, HM11B1_REG_CHIP_ID, 2, &val);
980 if (ret)
981 return ret;
982
983 if (val != HM11B1_CHIP_ID) {
984 dev_err(&client->dev, "chip id mismatch: %x!=%x",
985 HM11B1_CHIP_ID, val);
986 return -ENXIO;
987 }
988
989 return 0;
990 }
991
992 static int hm11b1_remove(struct i2c_client *client)
993 {
994 struct v4l2_subdev *sd = i2c_get_clientdata(client);
995 struct hm11b1 *hm11b1 = to_hm11b1(sd);
996
997 v4l2_async_unregister_subdev(sd);
998 media_entity_cleanup(&sd->entity);
999 v4l2_ctrl_handler_free(sd->ctrl_handler);
1000 pm_runtime_disable(&client->dev);
1001 mutex_destroy(&hm11b1->mutex);
1002
1003 return 0;
1004 }
1005
1006 static int hm11b1_probe(struct i2c_client *client)
1007 {
1008 struct hm11b1 *hm11b1;
1009 int ret = 0;
1010
1011 hm11b1 = devm_kzalloc(&client->dev, sizeof(*hm11b1), GFP_KERNEL);
1012 if (!hm11b1)
1013 return -ENOMEM;
1014
1015 v4l2_i2c_subdev_init(&hm11b1->sd, client, &hm11b1_subdev_ops);
1016 power_ctrl_logic_set_power(0);
1017 power_ctrl_logic_set_power(1);
1018 ret = hm11b1_identify_module(hm11b1);
1019 if (ret) {
1020 dev_err(&client->dev, "failed to find sensor: %d", ret);
1021 return ret;
1022 }
1023
1024 mutex_init(&hm11b1->mutex);
1025 hm11b1->cur_mode = &supported_modes[0];
1026 ret = hm11b1_init_controls(hm11b1);
1027 if (ret) {
1028 dev_err(&client->dev, "failed to init controls: %d", ret);
1029 goto probe_error_v4l2_ctrl_handler_free;
1030 }
1031
1032 hm11b1->sd.internal_ops = &hm11b1_internal_ops;
1033 hm11b1->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1034 hm11b1->sd.entity.ops = &hm11b1_subdev_entity_ops;
1035 hm11b1->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1036 hm11b1->pad.flags = MEDIA_PAD_FL_SOURCE;
1037 ret = media_entity_pads_init(&hm11b1->sd.entity, 1, &hm11b1->pad);
1038 if (ret) {
1039 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1040 goto probe_error_v4l2_ctrl_handler_free;
1041 }
1042
1043 ret = v4l2_async_register_subdev_sensor(&hm11b1->sd);
1044 if (ret < 0) {
1045 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1046 ret);
1047 goto probe_error_media_entity_cleanup;
1048 }
1049
1050 /*
1051 * Device is already turned on by i2c-core with ACPI domain PM.
1052 * Enable runtime PM and turn off the device.
1053 */
1054 pm_runtime_set_active(&client->dev);
1055 pm_runtime_enable(&client->dev);
1056 pm_runtime_idle(&client->dev);
1057
1058 power_ctrl_logic_set_power(0);
1059 return 0;
1060
1061 probe_error_media_entity_cleanup:
1062 media_entity_cleanup(&hm11b1->sd.entity);
1063
1064 probe_error_v4l2_ctrl_handler_free:
1065 v4l2_ctrl_handler_free(hm11b1->sd.ctrl_handler);
1066 mutex_destroy(&hm11b1->mutex);
1067
1068 return ret;
1069 }
1070
1071 static const struct dev_pm_ops hm11b1_pm_ops = {
1072 SET_SYSTEM_SLEEP_PM_OPS(hm11b1_suspend, hm11b1_resume)
1073 };
1074
1075 #ifdef CONFIG_ACPI
1076 static const struct acpi_device_id hm11b1_acpi_ids[] = {
1077 {"HIMX11B1"},
1078 {}
1079 };
1080
1081 MODULE_DEVICE_TABLE(acpi, hm11b1_acpi_ids);
1082 #endif
1083
1084 static struct i2c_driver hm11b1_i2c_driver = {
1085 .driver = {
1086 .name = "hm11b1",
1087 .pm = &hm11b1_pm_ops,
1088 .acpi_match_table = ACPI_PTR(hm11b1_acpi_ids),
1089 },
1090 .probe_new = hm11b1_probe,
1091 .remove = hm11b1_remove,
1092 };
1093
1094 module_i2c_driver(hm11b1_i2c_driver);
1095
1096 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1097 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1098 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1099 MODULE_AUTHOR("Lai, Jim <jim.lai@intel.com>");
1100 MODULE_DESCRIPTION("Himax HM11B1 sensor driver");
1101 MODULE_LICENSE("GPL v2");
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