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UBUNTU: SAUCE: IPU6: 2022-03-11 alpha release for Andrews MLK
[mirror_ubuntu-jammy-kernel.git] / drivers / media / i2c / ov01a10.c
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020-2021 Intel Corporation.
3
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/version.h>
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-fwnode.h>
14 #include <linux/vsc.h>
15
16 #define OV01A10_LINK_FREQ_400MHZ 400000000ULL
17 #define OV01A10_SCLK 40000000LL
18 #define OV01A10_MCLK 19200000
19 #define OV01A10_DATA_LANES 1
20 #define OV01A10_RGB_DEPTH 10
21
22 #define OV01A10_REG_CHIP_ID 0x300a
23 #define OV01A10_CHIP_ID 0x560141
24
25 #define OV01A10_REG_MODE_SELECT 0x0100
26 #define OV01A10_MODE_STANDBY 0x00
27 #define OV01A10_MODE_STREAMING 0x01
28
29 /* vertical-timings from sensor */
30 #define OV01A10_REG_VTS 0x380e
31 #define OV01A10_VTS_DEF 0x0380
32 #define OV01A10_VTS_MIN 0x0380
33 #define OV01A10_VTS_MAX 0xffff
34
35 /* Exposure controls from sensor */
36 #define OV01A10_REG_EXPOSURE 0x3501
37 #define OV01A10_EXPOSURE_MIN 4
38 #define OV01A10_EXPOSURE_MAX_MARGIN 8
39 #define OV01A10_EXPOSURE_STEP 1
40
41 /* Analog gain controls from sensor */
42 #define OV01A10_REG_ANALOG_GAIN 0x3508
43 #define OV01A10_ANAL_GAIN_MIN 0x100
44 #define OV01A10_ANAL_GAIN_MAX 0xffff
45 #define OV01A10_ANAL_GAIN_STEP 1
46
47 /* Digital gain controls from sensor */
48 #define OV01A10_REG_DIGILAL_GAIN_B 0x350A
49 #define OV01A10_REG_DIGITAL_GAIN_GB 0x3510
50 #define OV01A10_REG_DIGITAL_GAIN_GR 0x3513
51 #define OV01A10_REG_DIGITAL_GAIN_R 0x3516
52 #define OV01A10_DGTL_GAIN_MIN 0
53 #define OV01A10_DGTL_GAIN_MAX 0x3ffff
54 #define OV01A10_DGTL_GAIN_STEP 1
55 #define OV01A10_DGTL_GAIN_DEFAULT 1024
56
57 /* Test Pattern Control */
58 #define OV01A10_REG_TEST_PATTERN 0x4503
59 #define OV01A10_TEST_PATTERN_ENABLE BIT(7)
60 #define OV01A10_TEST_PATTERN_BAR_SHIFT 0
61
62 enum {
63 OV01A10_LINK_FREQ_400MHZ_INDEX,
64 };
65
66 struct ov01a10_reg {
67 u16 address;
68 u8 val;
69 };
70
71 struct ov01a10_reg_list {
72 u32 num_of_regs;
73 const struct ov01a10_reg *regs;
74 };
75
76 struct ov01a10_link_freq_config {
77 const struct ov01a10_reg_list reg_list;
78 };
79
80 struct ov01a10_mode {
81 /* Frame width in pixels */
82 u32 width;
83
84 /* Frame height in pixels */
85 u32 height;
86
87 /* Horizontal timining size */
88 u32 hts;
89
90 /* Default vertical timining size */
91 u32 vts_def;
92
93 /* Min vertical timining size */
94 u32 vts_min;
95
96 /* Link frequency needed for this resolution */
97 u32 link_freq_index;
98
99 /* Sensor register settings for this resolution */
100 const struct ov01a10_reg_list reg_list;
101 };
102
103 static const struct ov01a10_reg mipi_data_rate_720mbps[] = {
104 };
105
106 static const struct ov01a10_reg sensor_1280x800_setting[] = {
107 {0x0103, 0x01},
108 {0x0302, 0x00},
109 {0x0303, 0x06},
110 {0x0304, 0x01},
111 {0x0305, 0xe0},
112 {0x0306, 0x00},
113 {0x0308, 0x01},
114 {0x0309, 0x00},
115 {0x030c, 0x01},
116 {0x0322, 0x01},
117 {0x0323, 0x06},
118 {0x0324, 0x01},
119 {0x0325, 0x68},
120 {0x3002, 0xa1},
121 {0x301e, 0xf0},
122 {0x3022, 0x01},
123 {0x3501, 0x03},
124 {0x3502, 0x78},
125 {0x3504, 0x0c},
126 {0x3508, 0x01},
127 {0x3509, 0x00},
128 {0x3601, 0xc0},
129 {0x3603, 0x71},
130 {0x3610, 0x68},
131 {0x3611, 0x86},
132 {0x3640, 0x10},
133 {0x3641, 0x80},
134 {0x3642, 0xdc},
135 {0x3646, 0x55},
136 {0x3647, 0x57},
137 {0x364b, 0x00},
138 {0x3653, 0x10},
139 {0x3655, 0x00},
140 {0x3656, 0x00},
141 {0x365f, 0x0f},
142 {0x3661, 0x45},
143 {0x3662, 0x24},
144 {0x3663, 0x11},
145 {0x3664, 0x07},
146 {0x3709, 0x34},
147 {0x370b, 0x6f},
148 {0x3714, 0x22},
149 {0x371b, 0x27},
150 {0x371c, 0x67},
151 {0x371d, 0xa7},
152 {0x371e, 0xe7},
153 {0x3730, 0x81},
154 {0x3733, 0x10},
155 {0x3734, 0x40},
156 {0x3737, 0x04},
157 {0x3739, 0x1c},
158 {0x3767, 0x00},
159 {0x376c, 0x81},
160 {0x3772, 0x14},
161 {0x37c2, 0x04},
162 {0x37d8, 0x03},
163 {0x37d9, 0x0c},
164 {0x37e0, 0x00},
165 {0x37e1, 0x08},
166 {0x37e2, 0x10},
167 {0x37e3, 0x04},
168 {0x37e4, 0x04},
169 {0x37e5, 0x03},
170 {0x37e6, 0x04},
171 {0x3800, 0x00},
172 {0x3801, 0x00},
173 {0x3802, 0x00},
174 {0x3803, 0x00},
175 {0x3804, 0x05},
176 {0x3805, 0x0f},
177 {0x3806, 0x03},
178 {0x3807, 0x2f},
179 {0x3808, 0x05},
180 {0x3809, 0x00},
181 {0x380a, 0x03},
182 {0x380b, 0x20},
183 {0x380c, 0x02},
184 {0x380d, 0xe8},
185 {0x380e, 0x03},
186 {0x380f, 0x80},
187 {0x3810, 0x00},
188 {0x3811, 0x09},
189 {0x3812, 0x00},
190 {0x3813, 0x08},
191 {0x3814, 0x01},
192 {0x3815, 0x01},
193 {0x3816, 0x01},
194 {0x3817, 0x01},
195 {0x3820, 0xa8},
196 {0x3822, 0x13},
197 {0x3832, 0x28},
198 {0x3833, 0x10},
199 {0x3b00, 0x00},
200 {0x3c80, 0x00},
201 {0x3c88, 0x02},
202 {0x3c8c, 0x07},
203 {0x3c8d, 0x40},
204 {0x3cc7, 0x80},
205 {0x4000, 0xc3},
206 {0x4001, 0xe0},
207 {0x4003, 0x40},
208 {0x4008, 0x02},
209 {0x4009, 0x19},
210 {0x400a, 0x01},
211 {0x400b, 0x6c},
212 {0x4011, 0x00},
213 {0x4041, 0x00},
214 {0x4300, 0xff},
215 {0x4301, 0x00},
216 {0x4302, 0x0f},
217 {0x4503, 0x00},
218 {0x4601, 0x50},
219 {0x4800, 0x64},
220 {0x481f, 0x34},
221 {0x4825, 0x33},
222 {0x4837, 0x11},
223 {0x4881, 0x40},
224 {0x4883, 0x01},
225 {0x4890, 0x00},
226 {0x4901, 0x00},
227 {0x4902, 0x00},
228 {0x4b00, 0x2a},
229 {0x4b0d, 0x00},
230 {0x450a, 0x04},
231 {0x450b, 0x00},
232 {0x5000, 0x65},
233 {0x5200, 0x18},
234 {0x5004, 0x00},
235 {0x5080, 0x40},
236 {0x0305, 0xf4},
237 {0x0325, 0xc2},
238 {0x380c, 0x05},
239 {0x380d, 0xd0},
240 };
241
242 static const char * const ov01a10_test_pattern_menu[] = {
243 "Disabled",
244 "Color Bar",
245 "Top-Bottom Darker Color Bar",
246 "Right-Left Darker Color Bar",
247 "Color Bar type 4",
248 };
249
250 static const s64 link_freq_menu_items[] = {
251 OV01A10_LINK_FREQ_400MHZ,
252 };
253
254 static const struct ov01a10_link_freq_config link_freq_configs[] = {
255 [OV01A10_LINK_FREQ_400MHZ_INDEX] = {
256 .reg_list = {
257 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
258 .regs = mipi_data_rate_720mbps,
259 }
260 },
261 };
262
263 static const struct ov01a10_mode supported_modes[] = {
264 {
265 .width = 1280,
266 .height = 800,
267 .hts = 1488,
268 .vts_def = OV01A10_VTS_DEF,
269 .vts_min = OV01A10_VTS_MIN,
270 .reg_list = {
271 .num_of_regs = ARRAY_SIZE(sensor_1280x800_setting),
272 .regs = sensor_1280x800_setting,
273 },
274 .link_freq_index = OV01A10_LINK_FREQ_400MHZ_INDEX,
275 },
276 };
277
278 struct ov01a10 {
279 struct v4l2_subdev sd;
280 struct media_pad pad;
281 struct v4l2_ctrl_handler ctrl_handler;
282
283 /* V4L2 Controls */
284 struct v4l2_ctrl *link_freq;
285 struct v4l2_ctrl *pixel_rate;
286 struct v4l2_ctrl *vblank;
287 struct v4l2_ctrl *hblank;
288 struct v4l2_ctrl *exposure;
289
290 /* Current mode */
291 const struct ov01a10_mode *cur_mode;
292
293 /* To serialize asynchronus callbacks */
294 struct mutex mutex;
295
296 /* Streaming on/off */
297 bool streaming;
298 };
299
300 static inline struct ov01a10 *to_ov01a10(struct v4l2_subdev *subdev)
301 {
302 return container_of(subdev, struct ov01a10, sd);
303 }
304
305 static int ov01a10_read_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 *val)
306 {
307 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
308 struct i2c_msg msgs[2];
309 u8 addr_buf[2];
310 u8 data_buf[4] = {0};
311 int ret = 0;
312
313 if (len > sizeof(data_buf))
314 return -EINVAL;
315
316 put_unaligned_be16(reg, addr_buf);
317 msgs[0].addr = client->addr;
318 msgs[0].flags = 0;
319 msgs[0].len = sizeof(addr_buf);
320 msgs[0].buf = addr_buf;
321 msgs[1].addr = client->addr;
322 msgs[1].flags = I2C_M_RD;
323 msgs[1].len = len;
324 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
325
326 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
327
328 if (ret != ARRAY_SIZE(msgs))
329 return ret < 0 ? ret : -EIO;
330
331 *val = get_unaligned_be32(data_buf);
332
333 return 0;
334 }
335
336 static int ov01a10_write_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 val)
337 {
338 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
339 u8 buf[6];
340 int ret = 0;
341
342 if (len > 4)
343 return -EINVAL;
344
345 put_unaligned_be16(reg, buf);
346 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
347
348 ret = i2c_master_send(client, buf, len + 2);
349 if (ret != len + 2)
350 return ret < 0 ? ret : -EIO;
351
352 return 0;
353 }
354
355 static int ov01a10_write_reg_list(struct ov01a10 *ov01a10,
356 const struct ov01a10_reg_list *r_list)
357 {
358 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
359 unsigned int i;
360 int ret = 0;
361
362 for (i = 0; i < r_list->num_of_regs; i++) {
363 ret = ov01a10_write_reg(ov01a10, r_list->regs[i].address, 1,
364 r_list->regs[i].val);
365 if (ret) {
366 dev_err_ratelimited(&client->dev,
367 "write reg 0x%4.4x return err = %d",
368 r_list->regs[i].address, ret);
369 return ret;
370 }
371 }
372
373 return 0;
374 }
375
376 static int ov01a10_update_digital_gain(struct ov01a10 *ov01a10, u32 d_gain)
377 {
378 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
379 u32 real = d_gain << 6;
380 int ret = 0;
381
382 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGILAL_GAIN_B, 3, real);
383 if (ret) {
384 dev_err(&client->dev, "failed to set OV01A10_REG_DIGITAL_GAIN_B");
385 return ret;
386 }
387 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GB, 3, real);
388 if (ret) {
389 dev_err(&client->dev, "failed to set OV01A10_REG_DIGITAL_GAIN_GB");
390 return ret;
391 }
392 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GR, 3, real);
393 if (ret) {
394 dev_err(&client->dev, "failed to set OV01A10_REG_DIGITAL_GAIN_GR");
395 return ret;
396 }
397
398 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_R, 3, real);
399 if (ret) {
400 dev_err(&client->dev, "failed to set OV01A10_REG_DIGITAL_GAIN_R");
401 return ret;
402 }
403 return ret;
404 }
405
406 static int ov01a10_test_pattern(struct ov01a10 *ov01a10, u32 pattern)
407 {
408 if (pattern)
409 pattern = (pattern - 1) << OV01A10_TEST_PATTERN_BAR_SHIFT |
410 OV01A10_TEST_PATTERN_ENABLE;
411
412 return ov01a10_write_reg(ov01a10, OV01A10_REG_TEST_PATTERN, 1, pattern);
413 }
414
415 static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl)
416 {
417 struct ov01a10 *ov01a10 = container_of(ctrl->handler,
418 struct ov01a10, ctrl_handler);
419 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
420 s64 exposure_max;
421 int ret = 0;
422
423 /* Propagate change of current control to all related controls */
424 if (ctrl->id == V4L2_CID_VBLANK) {
425 /* Update max exposure while meeting expected vblanking */
426 exposure_max = ov01a10->cur_mode->height + ctrl->val -
427 OV01A10_EXPOSURE_MAX_MARGIN;
428 __v4l2_ctrl_modify_range(ov01a10->exposure,
429 ov01a10->exposure->minimum,
430 exposure_max, ov01a10->exposure->step,
431 exposure_max);
432 }
433
434 /* V4L2 controls values will be applied only when power is already up */
435 if (!pm_runtime_get_if_in_use(&client->dev))
436 return 0;
437
438 switch (ctrl->id) {
439 case V4L2_CID_ANALOGUE_GAIN:
440 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_ANALOG_GAIN, 2,
441 ctrl->val);
442 break;
443
444 case V4L2_CID_DIGITAL_GAIN:
445 ret = ov01a10_update_digital_gain(ov01a10, ctrl->val);
446 break;
447
448 case V4L2_CID_EXPOSURE:
449 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_EXPOSURE, 2,
450 ctrl->val);
451 break;
452
453 case V4L2_CID_VBLANK:
454 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_VTS, 2,
455 ov01a10->cur_mode->height + ctrl->val);
456 break;
457
458 case V4L2_CID_TEST_PATTERN:
459 ret = ov01a10_test_pattern(ov01a10, ctrl->val);
460 break;
461
462 default:
463 ret = -EINVAL;
464 break;
465 }
466
467 pm_runtime_put(&client->dev);
468
469 return ret;
470 }
471
472 static const struct v4l2_ctrl_ops ov01a10_ctrl_ops = {
473 .s_ctrl = ov01a10_set_ctrl,
474 };
475
476 static int ov01a10_init_controls(struct ov01a10 *ov01a10)
477 {
478 struct v4l2_ctrl_handler *ctrl_hdlr;
479 const struct ov01a10_mode *cur_mode;
480 s64 exposure_max, h_blank;
481 u32 vblank_min, vblank_max, vblank_default;
482 int size;
483 int ret = 0;
484
485 ctrl_hdlr = &ov01a10->ctrl_handler;
486 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
487 if (ret)
488 return ret;
489
490 ctrl_hdlr->lock = &ov01a10->mutex;
491 cur_mode = ov01a10->cur_mode;
492 size = ARRAY_SIZE(link_freq_menu_items);
493
494 ov01a10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
495 &ov01a10_ctrl_ops,
496 V4L2_CID_LINK_FREQ,
497 size - 1, 0,
498 link_freq_menu_items);
499 if (ov01a10->link_freq)
500 ov01a10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
501
502 ov01a10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
503 V4L2_CID_PIXEL_RATE, 0,
504 OV01A10_SCLK, 1, OV01A10_SCLK);
505
506 vblank_min = cur_mode->vts_min - cur_mode->height;
507 vblank_max = OV01A10_VTS_MAX - cur_mode->height;
508 vblank_default = cur_mode->vts_def - cur_mode->height;
509 ov01a10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
510 V4L2_CID_VBLANK, vblank_min,
511 vblank_max, 1, vblank_default);
512
513 h_blank = cur_mode->hts - cur_mode->width;
514 ov01a10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
515 V4L2_CID_HBLANK, h_blank, h_blank,
516 1, h_blank);
517 if (ov01a10->hblank)
518 ov01a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
519
520 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
521 OV01A10_ANAL_GAIN_MIN, OV01A10_ANAL_GAIN_MAX,
522 OV01A10_ANAL_GAIN_STEP, OV01A10_ANAL_GAIN_MIN);
523 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
524 OV01A10_DGTL_GAIN_MIN, OV01A10_DGTL_GAIN_MAX,
525 OV01A10_DGTL_GAIN_STEP, OV01A10_DGTL_GAIN_DEFAULT);
526 exposure_max = cur_mode->vts_def - OV01A10_EXPOSURE_MAX_MARGIN;
527 ov01a10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
528 V4L2_CID_EXPOSURE,
529 OV01A10_EXPOSURE_MIN,
530 exposure_max,
531 OV01A10_EXPOSURE_STEP,
532 exposure_max);
533 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov01a10_ctrl_ops,
534 V4L2_CID_TEST_PATTERN,
535 ARRAY_SIZE(ov01a10_test_pattern_menu) - 1,
536 0, 0, ov01a10_test_pattern_menu);
537 if (ctrl_hdlr->error)
538 return ctrl_hdlr->error;
539
540 ov01a10->sd.ctrl_handler = ctrl_hdlr;
541
542 return 0;
543 }
544
545 static void ov01a10_update_pad_format(const struct ov01a10_mode *mode,
546 struct v4l2_mbus_framefmt *fmt)
547 {
548 fmt->width = mode->width;
549 fmt->height = mode->height;
550 fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
551 fmt->field = V4L2_FIELD_NONE;
552 }
553
554 static int ov01a10_start_streaming(struct ov01a10 *ov01a10)
555 {
556 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
557 const struct ov01a10_reg_list *reg_list;
558 int link_freq_index;
559 int ret = 0;
560 struct vsc_mipi_config conf;
561 struct vsc_camera_status status;
562
563 conf.lane_num = OV01A10_DATA_LANES;
564 /* frequency unit 100k */
565 conf.freq = OV01A10_LINK_FREQ_400MHZ / 100000;
566 ret = vsc_acquire_camera_sensor(&conf, NULL, NULL, &status);
567 if (ret) {
568 dev_err(&client->dev, "Acquire VSC failed");
569 return ret;
570 }
571 link_freq_index = ov01a10->cur_mode->link_freq_index;
572 reg_list = &link_freq_configs[link_freq_index].reg_list;
573 ret = ov01a10_write_reg_list(ov01a10, reg_list);
574 if (ret) {
575 dev_err(&client->dev, "failed to set plls");
576 return ret;
577 }
578
579 reg_list = &ov01a10->cur_mode->reg_list;
580 ret = ov01a10_write_reg_list(ov01a10, reg_list);
581 if (ret) {
582 dev_err(&client->dev, "failed to set mode");
583 return ret;
584 }
585
586 ret = __v4l2_ctrl_handler_setup(ov01a10->sd.ctrl_handler);
587 if (ret)
588 return ret;
589
590 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
591 OV01A10_MODE_STREAMING);
592 if (ret)
593 dev_err(&client->dev, "failed to start streaming");
594
595 return ret;
596 }
597
598 static void ov01a10_stop_streaming(struct ov01a10 *ov01a10)
599 {
600 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
601 int ret = 0;
602 struct vsc_camera_status status;
603
604 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
605 OV01A10_MODE_STANDBY);
606 if (ret)
607 dev_err(&client->dev, "failed to stop streaming");
608 ret = vsc_release_camera_sensor(&status);
609 if (ret)
610 dev_err(&client->dev, "Release VSC failed");
611 }
612
613 static int ov01a10_set_stream(struct v4l2_subdev *sd, int enable)
614 {
615 struct ov01a10 *ov01a10 = to_ov01a10(sd);
616 struct i2c_client *client = v4l2_get_subdevdata(sd);
617 int ret = 0;
618
619 if (ov01a10->streaming == enable)
620 return 0;
621
622 mutex_lock(&ov01a10->mutex);
623 if (enable) {
624 ret = pm_runtime_get_sync(&client->dev);
625 if (ret < 0) {
626 pm_runtime_put_noidle(&client->dev);
627 mutex_unlock(&ov01a10->mutex);
628 return ret;
629 }
630
631 ret = ov01a10_start_streaming(ov01a10);
632 if (ret) {
633 enable = 0;
634 ov01a10_stop_streaming(ov01a10);
635 pm_runtime_put(&client->dev);
636 }
637 } else {
638 ov01a10_stop_streaming(ov01a10);
639 pm_runtime_put(&client->dev);
640 }
641
642 ov01a10->streaming = enable;
643 mutex_unlock(&ov01a10->mutex);
644
645 return ret;
646 }
647
648 static int __maybe_unused ov01a10_suspend(struct device *dev)
649 {
650 struct i2c_client *client = to_i2c_client(dev);
651 struct v4l2_subdev *sd = i2c_get_clientdata(client);
652 struct ov01a10 *ov01a10 = to_ov01a10(sd);
653
654 mutex_lock(&ov01a10->mutex);
655 if (ov01a10->streaming)
656 ov01a10_stop_streaming(ov01a10);
657
658 mutex_unlock(&ov01a10->mutex);
659
660 return 0;
661 }
662
663 static int __maybe_unused ov01a10_resume(struct device *dev)
664 {
665 struct i2c_client *client = to_i2c_client(dev);
666 struct v4l2_subdev *sd = i2c_get_clientdata(client);
667 struct ov01a10 *ov01a10 = to_ov01a10(sd);
668 int ret = 0;
669
670 mutex_lock(&ov01a10->mutex);
671 if (!ov01a10->streaming)
672 goto exit;
673
674 ret = ov01a10_start_streaming(ov01a10);
675 if (ret) {
676 ov01a10->streaming = false;
677 ov01a10_stop_streaming(ov01a10);
678 }
679
680 exit:
681 mutex_unlock(&ov01a10->mutex);
682 return ret;
683 }
684
685 static int ov01a10_set_format(struct v4l2_subdev *sd,
686 struct v4l2_subdev_state *sd_state,
687 struct v4l2_subdev_format *fmt)
688 {
689 struct ov01a10 *ov01a10 = to_ov01a10(sd);
690 const struct ov01a10_mode *mode;
691 s32 vblank_def, h_blank;
692
693 mode = v4l2_find_nearest_size(supported_modes,
694 ARRAY_SIZE(supported_modes), width,
695 height, fmt->format.width,
696 fmt->format.height);
697
698 mutex_lock(&ov01a10->mutex);
699 ov01a10_update_pad_format(mode, &fmt->format);
700 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
701 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
702 } else {
703 ov01a10->cur_mode = mode;
704 __v4l2_ctrl_s_ctrl(ov01a10->link_freq, mode->link_freq_index);
705 __v4l2_ctrl_s_ctrl_int64(ov01a10->pixel_rate, OV01A10_SCLK);
706
707 /* Update limits and set FPS to default */
708 vblank_def = mode->vts_def - mode->height;
709 __v4l2_ctrl_modify_range(ov01a10->vblank,
710 mode->vts_min - mode->height,
711 OV01A10_VTS_MAX - mode->height, 1,
712 vblank_def);
713 __v4l2_ctrl_s_ctrl(ov01a10->vblank, vblank_def);
714 h_blank = mode->hts - mode->width;
715 __v4l2_ctrl_modify_range(ov01a10->hblank, h_blank, h_blank, 1,
716 h_blank);
717 }
718 mutex_unlock(&ov01a10->mutex);
719
720 return 0;
721 }
722
723 static int ov01a10_get_format(struct v4l2_subdev *sd,
724 struct v4l2_subdev_state *sd_state,
725 struct v4l2_subdev_format *fmt)
726 {
727 struct ov01a10 *ov01a10 = to_ov01a10(sd);
728
729 mutex_lock(&ov01a10->mutex);
730 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
731 fmt->format = *v4l2_subdev_get_try_format(&ov01a10->sd,
732 sd_state, fmt->pad);
733 else
734 ov01a10_update_pad_format(ov01a10->cur_mode, &fmt->format);
735
736 mutex_unlock(&ov01a10->mutex);
737
738 return 0;
739 }
740
741 static int ov01a10_enum_mbus_code(struct v4l2_subdev *sd,
742 struct v4l2_subdev_state *sd_state,
743 struct v4l2_subdev_mbus_code_enum *code)
744 {
745 if (code->index > 0)
746 return -EINVAL;
747
748 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
749
750 return 0;
751 }
752
753 static int ov01a10_enum_frame_size(struct v4l2_subdev *sd,
754 struct v4l2_subdev_state *sd_state,
755 struct v4l2_subdev_frame_size_enum *fse)
756 {
757 if (fse->index >= ARRAY_SIZE(supported_modes))
758 return -EINVAL;
759
760 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
761 return -EINVAL;
762
763 fse->min_width = supported_modes[fse->index].width;
764 fse->max_width = fse->min_width;
765 fse->min_height = supported_modes[fse->index].height;
766 fse->max_height = fse->min_height;
767
768 return 0;
769 }
770
771 static int ov01a10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
772 {
773 struct ov01a10 *ov01a10 = to_ov01a10(sd);
774
775 mutex_lock(&ov01a10->mutex);
776 ov01a10_update_pad_format(&supported_modes[0],
777 v4l2_subdev_get_try_format(sd, fh->state, 0));
778 mutex_unlock(&ov01a10->mutex);
779
780 return 0;
781 }
782
783 static const struct v4l2_subdev_video_ops ov01a10_video_ops = {
784 .s_stream = ov01a10_set_stream,
785 };
786
787 static const struct v4l2_subdev_pad_ops ov01a10_pad_ops = {
788 .set_fmt = ov01a10_set_format,
789 .get_fmt = ov01a10_get_format,
790 .enum_mbus_code = ov01a10_enum_mbus_code,
791 .enum_frame_size = ov01a10_enum_frame_size,
792 };
793
794 static const struct v4l2_subdev_ops ov01a10_subdev_ops = {
795 .video = &ov01a10_video_ops,
796 .pad = &ov01a10_pad_ops,
797 };
798
799 static const struct media_entity_operations ov01a10_subdev_entity_ops = {
800 .link_validate = v4l2_subdev_link_validate,
801 };
802
803 static const struct v4l2_subdev_internal_ops ov01a10_internal_ops = {
804 .open = ov01a10_open,
805 };
806
807 static int ov01a10_identify_module(struct ov01a10 *ov01a10)
808 {
809 struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
810 int ret;
811 u32 val;
812
813 ret = ov01a10_read_reg(ov01a10, OV01A10_REG_CHIP_ID, 3, &val);
814 if (ret)
815 return ret;
816
817 if (val != OV01A10_CHIP_ID) {
818 dev_err(&client->dev, "chip id mismatch: %x!=%x",
819 OV01A10_CHIP_ID, val);
820 return -ENXIO;
821 }
822
823 return 0;
824 }
825
826 static int ov01a10_remove(struct i2c_client *client)
827 {
828 struct v4l2_subdev *sd = i2c_get_clientdata(client);
829 struct ov01a10 *ov01a10 = to_ov01a10(sd);
830
831 v4l2_async_unregister_subdev(sd);
832 media_entity_cleanup(&sd->entity);
833 v4l2_ctrl_handler_free(sd->ctrl_handler);
834 pm_runtime_disable(&client->dev);
835 mutex_destroy(&ov01a10->mutex);
836
837 return 0;
838 }
839
840 static int ov01a10_probe(struct i2c_client *client)
841 {
842 struct ov01a10 *ov01a10;
843 int ret = 0;
844 struct vsc_mipi_config conf;
845 struct vsc_camera_status status;
846
847 conf.lane_num = OV01A10_DATA_LANES;
848 /* frequency unit 100k */
849 conf.freq = OV01A10_LINK_FREQ_400MHZ / 100000;
850 ret = vsc_acquire_camera_sensor(&conf, NULL, NULL, &status);
851 if (ret == -EAGAIN) {
852 dev_dbg(&client->dev, "VSC not ready, will re-probe");
853 return -EPROBE_DEFER;
854 } else if (ret) {
855 dev_err(&client->dev, "Acquire VSC failed");
856 return ret;
857 }
858 ov01a10 = devm_kzalloc(&client->dev, sizeof(*ov01a10), GFP_KERNEL);
859 if (!ov01a10) {
860 ret = -ENOMEM;
861 goto probe_error_ret;
862 }
863
864 v4l2_i2c_subdev_init(&ov01a10->sd, client, &ov01a10_subdev_ops);
865
866 ret = ov01a10_identify_module(ov01a10);
867 if (ret) {
868 dev_err(&client->dev, "failed to find sensor: %d", ret);
869 goto probe_error_ret;
870 }
871
872 mutex_init(&ov01a10->mutex);
873 ov01a10->cur_mode = &supported_modes[0];
874 ret = ov01a10_init_controls(ov01a10);
875 if (ret) {
876 dev_err(&client->dev, "failed to init controls: %d", ret);
877 goto probe_error_v4l2_ctrl_handler_free;
878 }
879
880 ov01a10->sd.internal_ops = &ov01a10_internal_ops;
881 ov01a10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
882 ov01a10->sd.entity.ops = &ov01a10_subdev_entity_ops;
883 ov01a10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
884 ov01a10->pad.flags = MEDIA_PAD_FL_SOURCE;
885 ret = media_entity_pads_init(&ov01a10->sd.entity, 1, &ov01a10->pad);
886 if (ret) {
887 dev_err(&client->dev, "failed to init entity pads: %d", ret);
888 goto probe_error_v4l2_ctrl_handler_free;
889 }
890
891 ret = v4l2_async_register_subdev_sensor(&ov01a10->sd);
892 if (ret < 0) {
893 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
894 ret);
895 goto probe_error_media_entity_cleanup;
896 }
897
898 vsc_release_camera_sensor(&status);
899 /*
900 * Device is already turned on by i2c-core with ACPI domain PM.
901 * Enable runtime PM and turn off the device.
902 */
903 pm_runtime_set_active(&client->dev);
904 pm_runtime_enable(&client->dev);
905 pm_runtime_idle(&client->dev);
906
907 return 0;
908
909 probe_error_media_entity_cleanup:
910 media_entity_cleanup(&ov01a10->sd.entity);
911
912 probe_error_v4l2_ctrl_handler_free:
913 v4l2_ctrl_handler_free(ov01a10->sd.ctrl_handler);
914 mutex_destroy(&ov01a10->mutex);
915
916 probe_error_ret:
917 vsc_release_camera_sensor(&status);
918 return ret;
919 }
920
921 static const struct dev_pm_ops ov01a10_pm_ops = {
922 SET_SYSTEM_SLEEP_PM_OPS(ov01a10_suspend, ov01a10_resume)
923 };
924
925 #ifdef CONFIG_ACPI
926 static const struct acpi_device_id ov01a10_acpi_ids[] = {
927 {"OVTI01A0"},
928 {}
929 };
930
931 MODULE_DEVICE_TABLE(acpi, ov01a10_acpi_ids);
932 #endif
933
934 static struct i2c_driver ov01a10_i2c_driver = {
935 .driver = {
936 .name = "ov01a10",
937 .pm = &ov01a10_pm_ops,
938 .acpi_match_table = ACPI_PTR(ov01a10_acpi_ids),
939 },
940 .probe_new = ov01a10_probe,
941 .remove = ov01a10_remove,
942 };
943
944 module_i2c_driver(ov01a10_i2c_driver);
945
946 MODULE_AUTHOR("Wang Yating <yating.wang@intel.com>");
947 MODULE_DESCRIPTION("OmniVision OV01A10 sensor driver");
948 MODULE_LICENSE("GPL v2");
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